From patchwork Wed Oct 9 09:55:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 13828063 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D48038DD3; Wed, 9 Oct 2024 09:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467822; cv=none; b=tmDzKrfYg2AZ5iQvglHEOuKQNvCCKDNt7DbjyHFmY2I0IuaxH+PKOODa6RfWCLdO8hHnnLGnld6yPaspiflJuG0NNd1GBGty1nZSohif/YfZ8snvU1hkIFH4UDyJrZG44ZQNa7L7zjUgJo8JijTAdFZqgs2UdtCYtWucUWzt0N8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467822; c=relaxed/simple; bh=aHA0iUWPEFT3IbFR1TA1T8dPf/5fafb10xlp4mn+2Ck=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gUl0joVoFcdM2vDpzQuB+YpTFHQrAhPWqlNJx10kUT1qT5jO3OSojikSVBPAJbCko+xEtxmUMxd9Jj8cLy1AABhPW43psescKh/j5/lGC3itW/pHtC9DaMOVAtMtGuZWphSAkLMCSGiQc70yOeX9rqK2N8A4FKu5HeElcP6HFek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=BxpKC2DC; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="BxpKC2DC" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 498NLZLb000960; Wed, 9 Oct 2024 09:56:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Vz5/kcDxtEOju7Z676DeiXJmEA1JXEODXPhijTBJr1U=; b=BxpKC2DCILIOSqNk q85Wvg0QK7VBITSxXEbQKfNcLCzYBRXIpn3SoGaiyJEKIARzqqLA7cyaLcdp/imF 9oPy44y64hd3Oe4eUWsytS7VCBf6zP3vv2/o1w6Er5VRk6fr664H8XGsV1VdKrsl po0L9U++24fs+2dkaLiG0XXNr/D7UEvHIH2DpNuc38L1/NQegF93FKS56/iQ9CX1 txMZMCZs5MwzxXdYvZK55nwUyETlYPPI8kchjrOcukM/5d755tn0laqi4OPz1WLV B0kPeCno1ad4NCG/nWOPxJh9nlVvgkDEaPnhy9hHFrhjDCojjnUN5ytTfPm1iP+B +v9ksQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4252wsudcu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:56:27 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4999uQlP019039 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 09:56:26 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 02:56:20 -0700 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Jinlong Mao , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Song Chai , , Subject: [PATCH v5 RESEND 1/5] Coresight: Add support for new APB clock name Date: Wed, 9 Oct 2024 17:55:52 +0800 Message-ID: <20241009095556.1754876-2-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009095556.1754876-1-quic_jiegan@quicinc.com> References: <20241009095556.1754876-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 039dkE2RDuKlgu-D_1E1EI6ZR0XehFSG X-Proofpoint-GUID: 039dkE2RDuKlgu-D_1E1EI6ZR0XehFSG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=930 priorityscore=1501 spamscore=0 mlxscore=0 suspectscore=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090064 Add support for new APB clock-name. If the function fails to obtain the clock with the name "apb_pclk", it will attempt to acquire the clock with the name "apb". Signed-off-by: Jie Gan --- include/linux/coresight.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index c13342594278..497d2206419d 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -454,8 +454,11 @@ static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) int ret; pclk = clk_get(dev, "apb_pclk"); - if (IS_ERR(pclk)) - return NULL; + if (IS_ERR(pclk)) { + pclk = clk_get(dev, "apb"); + if (IS_ERR(pclk)) + return NULL; + } ret = clk_prepare_enable(pclk); if (ret) { From patchwork Wed Oct 9 09:55:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 13828066 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E58B18E351; Wed, 9 Oct 2024 09:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467823; cv=none; b=A/wmT39aSUOMO2ujNqNMrTZ4uwSL24+oYuEyUr8XpUdhJ6584LjAZ2/n2SRsorGjucyaRZtytV33SEdd1KxRc09zAcVVP4BB6Jaogn/nmqEIIoAnY7d55lD0mEqsSeSet1BWZxrbFUAXuM/RG/Uj+eKr1jVJqhBXTxryxTEbgWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467823; c=relaxed/simple; bh=YzlLYgQNMQsRCYBqt2nthluRVMWYhNj8fhQIEuOvPEI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XwMHraSv+k09UpGAWLL2rkxQctMUxvbVnWVCvPjICJLWsfgqP+qb1g1gUfSsm2WWwjO2gHqM8KysOBL9/NZTfDKMBfUdpZaSgrN512GEWpROMZXDbRkwckYMYqTwAhYnKgoca2C0ynvYdemGhrCzXVnxwBOvfMU6Lop0JAOSoMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aDXG2G1i; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aDXG2G1i" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4997ltHh024383; Wed, 9 Oct 2024 09:56:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= aTAVsJNMtBUHJFJnsWQCbyFT+QeZjAsFI4J74CVPKiw=; b=aDXG2G1isQ3A71ne XIwxXwPCx2Ma3kd4eFmesac6PZYEeMGUexkMNIc1WYCT3bXOwl+qTCA5tOdVKRBe zAJYgq9gEoolGbDljj9GLaaQk9/ktDa2RkTgbH7ZPQ6dmm+D7G01IUQsxW+SMvCP Wu2ftAX6Bn/AFkB1UJ3gl+VWnU685RvWItB/u9kePA/ryY3JWpgtzK2qagdDeVLv DtuMzcvA2Er6RZgUMvmBtm1vRhaYJ9oi1WVBBvK0Dua7i3D5DidstwnLLjcr9Rgo KJsb45C3/A09l+JV38SjYGExVUFR26d1kdJc7yp7h6CXJQ8GG4NOihgeMjvP4S1t DPcdDA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4258pst7k3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:56:33 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4999uWQn019090 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 09:56:32 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 02:56:26 -0700 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Jinlong Mao , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Song Chai , , Subject: [PATCH v5 RESEND 2/5] Coresight: Add trace_id function to retrieving the trace ID Date: Wed, 9 Oct 2024 17:55:53 +0800 Message-ID: <20241009095556.1754876-3-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009095556.1754876-1-quic_jiegan@quicinc.com> References: <20241009095556.1754876-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hMwtNAjizisfTKaheamSsnqKmXCDoQ9r X-Proofpoint-ORIG-GUID: hMwtNAjizisfTKaheamSsnqKmXCDoQ9r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxscore=0 bulkscore=0 impostorscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090064 Add 'trace_id' function pointer in ops. It's responsible for retrieving the device's trace ID. Add 'struct cs_sink_data' to store the data that is needed by coresight_enable_path/coresight_disable_path. The structure will be transmitted to the helper and sink device to enable related funcationalities. Depends-on: commit 743e3154674f ("coresight: Use per-sink trace ID maps for Perf sessions") Depends-on: commit 4b5809ca2a8b ("coresight: Make CPU id map a property of a trace ID map") Depends-on: commit ef050fc3606e ("coresight: Expose map arguments in trace ID API") Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 59 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etb10.c | 3 +- .../hwtracing/coresight/coresight-etm-perf.c | 37 ++++++++++-- .../coresight/coresight-etm3x-core.c | 30 ++++++++++ .../coresight/coresight-etm4x-core.c | 29 +++++++++ drivers/hwtracing/coresight/coresight-priv.h | 13 +++- drivers/hwtracing/coresight/coresight-stm.c | 22 +++++++ drivers/hwtracing/coresight/coresight-sysfs.c | 24 +++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 3 +- .../hwtracing/coresight/coresight-tmc-etr.c | 6 +- drivers/hwtracing/coresight/coresight-tpda.c | 20 +++++++ drivers/hwtracing/coresight/coresight-trbe.c | 4 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 3 +- include/linux/coresight.h | 6 ++ 14 files changed, 234 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ea38ecf26fcb..ac5dd4a43798 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -23,6 +23,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" /* * Mutex used to lock all sysfs enable and disable actions and loading and @@ -297,12 +298,12 @@ static int coresight_enable_helper(struct coresight_device *csdev, return helper_ops(csdev)->enable(csdev, mode, data); } -static void coresight_disable_helper(struct coresight_device *csdev) +static void coresight_disable_helper(struct coresight_device *csdev, void *data) { - helper_ops(csdev)->disable(csdev, NULL); + helper_ops(csdev)->disable(csdev, data); } -static void coresight_disable_helpers(struct coresight_device *csdev) +static void coresight_disable_helpers(struct coresight_device *csdev, void *data) { int i; struct coresight_device *helper; @@ -310,7 +311,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) for (i = 0; i < csdev->pdata->nr_outconns; ++i) { helper = csdev->pdata->out_conns[i]->dest_dev; if (helper && coresight_is_helper(helper)) - coresight_disable_helper(helper); + coresight_disable_helper(helper, data); } } @@ -327,7 +328,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) void coresight_disable_source(struct coresight_device *csdev, void *data) { source_ops(csdev)->disable(csdev, data); - coresight_disable_helpers(csdev); + coresight_disable_helpers(csdev, NULL); } EXPORT_SYMBOL_GPL(coresight_disable_source); @@ -337,7 +338,8 @@ EXPORT_SYMBOL_GPL(coresight_disable_source); * disabled. */ static void coresight_disable_path_from(struct list_head *path, - struct coresight_node *nd) + struct coresight_node *nd, + void *sink_data) { u32 type; struct coresight_device *csdev, *parent, *child; @@ -382,13 +384,13 @@ static void coresight_disable_path_from(struct list_head *path, } /* Disable all helpers adjacent along the path last */ - coresight_disable_helpers(csdev); + coresight_disable_helpers(csdev, sink_data); } } -void coresight_disable_path(struct list_head *path) +void coresight_disable_path(struct list_head *path, void *sink_data) { - coresight_disable_path_from(path, NULL); + coresight_disable_path_from(path, NULL, sink_data); } EXPORT_SYMBOL_GPL(coresight_disable_path); @@ -468,10 +470,47 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode, out: return ret; err: - coresight_disable_path_from(path, nd); + coresight_disable_path_from(path, nd, sink_data); goto out; } +int coresight_read_traceid(struct list_head *path, enum cs_mode mode, + struct coresight_trace_id_map *id_map) +{ + int trace_id, type; + struct coresight_device *csdev; + struct coresight_node *nd; + + list_for_each_entry(nd, path, link) { + csdev = nd->csdev; + type = csdev->type; + + switch (type) { + case CORESIGHT_DEV_TYPE_SOURCE: + if (source_ops(csdev)->trace_id != NULL) { + trace_id = source_ops(csdev)->trace_id(csdev, + mode, + id_map); + if (IS_VALID_CS_TRACE_ID(trace_id)) + goto out; + } + break; + case CORESIGHT_DEV_TYPE_LINK: + if (link_ops(csdev)->trace_id != NULL) { + trace_id = link_ops(csdev)->trace_id(csdev); + if (IS_VALID_CS_TRACE_ID(trace_id)) + goto out; + } + break; + default: + break; + } + } + return -EINVAL; +out: + return trace_id; +} + struct coresight_device *coresight_get_sink(struct list_head *path) { struct coresight_device *csdev; diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 7edd3f1d0d46..05e620529c14 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -173,7 +173,8 @@ static int etb_enable_perf(struct coresight_device *csdev, void *data) pid_t pid; unsigned long flags; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index ad6a8f4b70b6..e676edd42ddc 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -459,6 +459,7 @@ static void etm_event_start(struct perf_event *event, int flags) struct perf_output_handle *handle = &ctxt->handle; struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); struct list_head *path; + struct cs_sink_data *sink_data = NULL; u64 hw_id; u8 trace_id; @@ -498,9 +499,20 @@ static void etm_event_start(struct perf_event *event, int flags) if (WARN_ON_ONCE(!sink)) goto fail_end_stop; + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) + goto fail_end_stop; + + sink_data->sink = sink; + sink_data->traceid = coresight_read_traceid(path, CS_MODE_PERF, + &sink->perf_sink_id_map); + sink_data->handle = handle; + /* Nothing will happen without a path */ - if (coresight_enable_path(path, CS_MODE_PERF, handle)) + if (coresight_enable_path(path, CS_MODE_PERF, sink_data)) { + kfree(sink_data); goto fail_end_stop; + } /* Finally enable the tracer */ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, @@ -526,6 +538,7 @@ static void etm_event_start(struct perf_event *event, int flags) perf_report_aux_output_id(event, hw_id); } + kfree(sink_data); out: /* Tell the perf core the event is alive */ event->hw.state = 0; @@ -534,7 +547,8 @@ static void etm_event_start(struct perf_event *event, int flags) return; fail_disable_path: - coresight_disable_path(path); + coresight_disable_path(path, sink_data); + kfree(sink_data); fail_end_stop: /* * Check if the handle is still associated with the event, @@ -559,6 +573,7 @@ static void etm_event_stop(struct perf_event *event, int mode) struct perf_output_handle *handle = &ctxt->handle; struct etm_event_data *event_data; struct list_head *path; + struct cs_sink_data *sink_data = NULL; /* * If we still have access to the event_data via handle, @@ -603,6 +618,10 @@ static void etm_event_stop(struct perf_event *event, int mode) if (!sink) return; + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) + return; + /* stop tracer */ coresight_disable_source(csdev, event); @@ -616,12 +635,16 @@ static void etm_event_stop(struct perf_event *event, int mode) * have to do anything here. */ if (handle->event && (mode & PERF_EF_UPDATE)) { - if (WARN_ON_ONCE(handle->event != event)) + if (WARN_ON_ONCE(handle->event != event)) { + kfree(sink_data); return; + } /* update trace information */ - if (!sink_ops(sink)->update_buffer) + if (!sink_ops(sink)->update_buffer) { + kfree(sink_data); return; + } size = sink_ops(sink)->update_buffer(sink, handle, event_data->snk_config); @@ -642,8 +665,12 @@ static void etm_event_stop(struct perf_event *event, int mode) WARN_ON(size); } + sink_data->sink = sink; + sink_data->traceid = coresight_read_traceid(path, CS_MODE_PERF, + &sink->perf_sink_id_map); /* Disabling the path make its elements available to other sessions */ - coresight_disable_path(path); + coresight_disable_path(path, sink_data); + kfree(sink_data); } static int etm_event_add(struct perf_event *event, int mode) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index c103f4c70f5d..0f095fab7e0a 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -697,10 +697,40 @@ static void etm_disable(struct coresight_device *csdev, coresight_set_mode(csdev, CS_MODE_DISABLED); } +static int etm_trace_id(struct coresight_device *csdev, + enum cs_mode mode, + struct coresight_trace_id_map *id_map) +{ + int trace_id; + struct etm_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + switch (mode) { + case CS_MODE_SYSFS: + trace_id = etm_read_alloc_trace_id(drvdata); + break; + case CS_MODE_PERF: + trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->traceid = (u8)trace_id; + break; + default: + trace_id = -EINVAL; + break; + } + + return trace_id; +} + + static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, .enable = etm_enable, .disable = etm_disable, + .trace_id = etm_trace_id, }; static const struct coresight_ops etm_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 66d44a404ad0..665611ab57a9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1025,10 +1025,39 @@ static void etm4_disable(struct coresight_device *csdev, coresight_set_mode(csdev, CS_MODE_DISABLED); } +static int etm4_trace_id(struct coresight_device *csdev, + enum cs_mode mode, + struct coresight_trace_id_map *id_map) +{ + int trace_id; + struct etmv4_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + switch (mode) { + case CS_MODE_SYSFS: + trace_id = etm4_read_alloc_trace_id(drvdata); + break; + case CS_MODE_PERF: + trace_id = coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->trcid = (u8)trace_id; + break; + default: + trace_id = -EINVAL; + break; + } + + return trace_id; +} + static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, .enable = etm4_enable, .disable = etm4_disable, + .trace_id = etm4_trace_id, }; static const struct coresight_ops etm4_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 05f891ca6b5c..6a95a3ba9339 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -105,6 +105,15 @@ struct cs_buffers { void **data_pages; }; +/** + * struct cs_sink_data - data used by coresight_enable_path/coresight_disable_path + */ +struct cs_sink_data { + struct perf_output_handle *handle; + struct coresight_device *sink; + u8 traceid; +}; + static inline void coresight_insert_barrier_packet(void *buf) { if (buf) @@ -129,9 +138,11 @@ static inline void CS_UNLOCK(void __iomem *addr) } while (0); } -void coresight_disable_path(struct list_head *path); +void coresight_disable_path(struct list_head *path, void *sink_data); int coresight_enable_path(struct list_head *path, enum cs_mode mode, void *sink_data); +int coresight_read_traceid(struct list_head *path, enum cs_mode mode, + struct coresight_trace_id_map *id_map); struct coresight_device *coresight_get_sink(struct list_head *path); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index cb3e04755c99..4975c1981f5d 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -281,9 +281,31 @@ static void stm_disable(struct coresight_device *csdev, } } +static int stm_trace_id(struct coresight_device *csdev, + enum cs_mode mode, + struct coresight_trace_id_map *id_map) +{ + int trace_id; + struct stm_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + trace_id = drvdata->traceid; + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + trace_id = coresight_trace_id_get_system_id(); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->traceid = (u8)trace_id; + } + + return trace_id; +} + static const struct coresight_ops_source stm_source_ops = { .enable = stm_enable, .disable = stm_disable, + .trace_id = stm_trace_id, }; static const struct coresight_ops stm_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index a01c9e54e2ed..8816bccba374 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -168,6 +168,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev) int cpu, ret = 0; struct coresight_device *sink; struct list_head *path; + struct cs_sink_data *sink_data; enum coresight_dev_subtype_source subtype; u32 hash; @@ -209,7 +210,14 @@ int coresight_enable_sysfs(struct coresight_device *csdev) goto out; } - ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL); + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) { + ret = -ENOMEM; + goto out; + } + sink_data->traceid = coresight_read_traceid(path, CS_MODE_SYSFS, NULL); + sink_data->sink = sink; + ret = coresight_enable_path(path, CS_MODE_SYSFS, sink_data); if (ret) goto err_path; @@ -246,15 +254,17 @@ int coresight_enable_sysfs(struct coresight_device *csdev) break; } + kfree(sink_data); out: mutex_unlock(&coresight_mutex); return ret; err_source: - coresight_disable_path(path); + coresight_disable_path(path, sink_data); err_path: coresight_release_path(path); + kfree(sink_data); goto out; } EXPORT_SYMBOL_GPL(coresight_enable_sysfs); @@ -263,6 +273,7 @@ void coresight_disable_sysfs(struct coresight_device *csdev) { int cpu, ret; struct list_head *path = NULL; + struct cs_sink_data *sink_data = NULL; u32 hash; mutex_lock(&coresight_mutex); @@ -274,6 +285,10 @@ void coresight_disable_sysfs(struct coresight_device *csdev) if (!coresight_disable_source_sysfs(csdev, NULL)) goto out; + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) + goto out; + switch (csdev->subtype.source_subtype) { case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: cpu = source_ops(csdev)->cpu_id(csdev); @@ -297,8 +312,11 @@ void coresight_disable_sysfs(struct coresight_device *csdev) break; } - coresight_disable_path(path); + sink_data->sink = coresight_find_activated_sysfs_sink(csdev); + sink_data->traceid = coresight_read_traceid(path, CS_MODE_SYSFS, NULL); + coresight_disable_path(path, sink_data); coresight_release_path(path); + kfree(sink_data); out: mutex_unlock(&coresight_mutex); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d4f641cd9de6..7dc536eba3e2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -250,7 +250,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 8962fc27d04f..73bb722e88b0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1254,7 +1254,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, void *data) { - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct etr_perf_buffer *etr_perf; switch (mode) { @@ -1648,7 +1649,8 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index bfca103f9f84..0f47f85811f4 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -232,9 +232,29 @@ static void tpda_disable(struct coresight_device *csdev, dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); } +static int tpda_trace_id(struct coresight_device *csdev) +{ + int trace_id; + struct tpda_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + trace_id = drvdata->atid; + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + trace_id = coresight_trace_id_get_system_id(); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->atid = (u8)trace_id; + } + + return trace_id; +} + static const struct coresight_ops_link tpda_link_ops = { .enable = tpda_enable, .disable = tpda_disable, + .trace_id = tpda_trace_id, }; static const struct coresight_ops tpda_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 96a32b213669..7f4560b067a8 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -21,6 +21,7 @@ #include "coresight-self-hosted-trace.h" #include "coresight-trbe.h" +#include "coresight-priv.h" #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT)) @@ -1012,7 +1013,8 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode, { struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct trbe_buf *buf = etm_perf_sink_config(handle); WARN_ON(cpudata->cpu != smp_processor_id()); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c index f9ebf20c91e6..92d8a9fb844e 100644 --- a/drivers/hwtracing/coresight/ultrasoc-smb.c +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -217,7 +217,8 @@ static void smb_enable_sysfs(struct coresight_device *csdev) static int smb_enable_perf(struct coresight_device *csdev, void *data) { struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); pid_t pid; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 497d2206419d..22b977908f4f 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -363,6 +363,7 @@ struct coresight_ops_sink { * Operations available for links. * @enable: enables flow between iport and oport. * @disable: disables flow between iport and oport. + * @trace_id: Collect the traceid. */ struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, @@ -371,6 +372,7 @@ struct coresight_ops_link { void (*disable)(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out); + int (*trace_id)(struct coresight_device *csdev); }; /** @@ -380,6 +382,7 @@ struct coresight_ops_link { * is associated to. * @enable: enables tracing for a source. * @disable: disables tracing for a source. + * @trace_id: collect the traceid. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); @@ -387,6 +390,9 @@ struct coresight_ops_source { enum cs_mode mode, struct coresight_trace_id_map *id_map); void (*disable)(struct coresight_device *csdev, struct perf_event *event); + int (*trace_id)(struct coresight_device *csdev, + enum cs_mode mode, + struct coresight_trace_id_map *id_map); }; /** From patchwork Wed Oct 9 09:55:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 13828065 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDEDE18DF62; Wed, 9 Oct 2024 09:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467822; cv=none; b=ud3y7CDTxqdXL1MPoWCazGzSkyg0B2hBBRt+X45lZYvIUsK2JO4cSgSAgRgZGm6kEzORCkQ0HaXEMekXz3sPFZJR1I1sIp0LmPPh31sXf3pADPkAKfoeCWvArY6GinHEutMp+1aMhmNYE6oDp+6LUAY2Gxw5BHHP1r08ZkyouVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467822; c=relaxed/simple; bh=HEEcfnOq54LR0U51mqX/+LvcTri4c03Xzg8uUxcuZx0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tDwWVwW3K7l052P4lcSdHQb0jkelZ/uMpa22JdMfaqGe46g349kuWPhK45kFYHSQ3xPOIOvz/AMW+ZCpvQjdfkbQPNtb4F9CGUxzxFvnmf3VsMqHTgIogdlVZUeQGOdCmY+HAbg48cv4wahBape8JWW8OVqCfRyqTtcR1H/1rGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=A1431uoF; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="A1431uoF" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4995cA3b022378; Wed, 9 Oct 2024 09:56:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9T6vDCQgh1gIYQoLsdnmEUZ+H4oulTkXaYpu8/f4F1Q=; b=A1431uoFL/8i4WTN HcfVDynIeT7hDms+zyiKbBTe+EUXiKIlQA7Riy66O4eSw27+y4CNLND+GM7OIgR9 fNHJmQMErMe4zLF9zRwtahNlXau0rCxF8RvLkzuqs6w+rz1Madlpm+uaY+MIwJkR pd0icp4DovVj6Snm+x1IxsOXMrp7kwNiTIKGLsBOHyuSw4CPMOBJvmAB5vxmZunG Lci/cf6dU7e46TrygHoDyhE8CPWVuYSlZ2ISV5xBJsTsGwjcRG/YiS6BBK3xJG3Z nt1ZkntVjfGj1n2xQYqULPmais9bnySV0E7qpzHCxgTCCaytOSwVCIaugxqIUO9Z y3qipQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 424kaewk6v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:56:39 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4999ucJJ010669 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 09:56:38 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 02:56:32 -0700 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Jinlong Mao , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Song Chai , , Subject: [PATCH v5 RESEND 3/5] dt-bindings: arm: Add Coresight TMC Control Unit hardware Date: Wed, 9 Oct 2024 17:55:54 +0800 Message-ID: <20241009095556.1754876-4-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009095556.1754876-1-quic_jiegan@quicinc.com> References: <20241009095556.1754876-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0-toF4dwtZaS0gDmIw2FuAsR-JOG-e5R X-Proofpoint-GUID: 0-toF4dwtZaS0gDmIw2FuAsR-JOG-e5R X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 adultscore=1 spamscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090064 Add binding file to specify how to define a Coresight TMC Control Unit device in device tree. It is responsible for controlling the data filter function based on the source device's Trace ID for TMC ETR device. The trace data with that Trace id can get into ETR's buffer while other trace data gets ignored. Reviewed-by: Rob Herring (Arm) Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml new file mode 100644 index 000000000000..843b52eaf872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight TMC Control Unit + +maintainers: + - Yuanfang Zhang + - Mao Jinlong + - Jie Gan + +description: | + The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations. + The configuration mode (ETB, ETF, ETR) is discovered at boot time when + the device is probed. + + The Coresight TMC Control unit controls various Coresight behaviors. + It works as a helper device when connected to TMC ETR device. + It is responsible for controlling the data filter function based on + the source device's Trace ID for TMC ETR device. The trace data with + that Trace id can get into ETR's buffer while other trace data gets + ignored. + +properties: + compatible: + enum: + - qcom,sa8775p-ctcu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-1])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - in-ports + +additionalProperties: false + +examples: + - | + ctcu@1001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x1001000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ctcu_in_port0: endpoint { + remote-endpoint = <&etr0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ctcu_in_port1: endpoint { + remote-endpoint = <&etr1_out_port>; + }; + }; + }; + }; From patchwork Wed Oct 9 09:55:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 13828067 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F9EB18E357; Wed, 9 Oct 2024 09:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467823; cv=none; b=CsgmPErj4f2Nx08Dw7fG5m5IrLPm0lZao9fhmUher6c9cfTuWUDQOpzHXZ/4hza/oFIUh42qHhvmaRh1T7AZVP5hczBs/a0PVZ14BZGv3LBYZe/eYWHTPjqZBmFjYmBk+jFLOV3uRke2lpOpaBTT1Vx8Wm0oNJmkyuM20hQVrLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467823; c=relaxed/simple; bh=zGgBmQWbNpALuN0wVp75/rI/0Mj0dANl4fitHBXUj68=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Zlzshr5+mqcgc/LjxxEUpE6Rsc17V1jncU95BxXfDFVqTmy0166i63RdAWN2lKzvN8UdXvD282+GB+vBsP4AHKxNR9GXpkzRDO1b1i+jVeVeAkgIzs6Q6KNeiqq1uVtc/zI+n9wVoZJpRjRjPan3uNE51PO+KtG2XjPJdGSuvrI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ea4aV1on; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ea4aV1on" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 498LWTJL006638; Wed, 9 Oct 2024 09:56:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 8696fy4vlMwY0gAsSyFdqvhBE7SMUwofwED0Dm7hcMQ=; b=ea4aV1onj6VxT6cc eBKEDYgCKvB7BzEQaFjNvn5uhWVEcOBQ2zRaG3UbnCgwPiwi0ksfzKu3fntByl7A DVfocgaw3/pipiVjIZYPl6C5aqRPyTgJ1Aq6xvw7uC4d7tp/iOl5MM2AFhHsoa1Z u7mKf0b1CLsADzxRjv4Mz5BE/K3X94XFIGukh5mcOK9VH1OSt8KdlOjb+/H5j2fC x0rGJVJbOT6VX1/OspP6M4bg1r+YbNbMxrIH9TzEXWwOQqfxqMRilC6MHwnSlrFg EUBASuN8s/C2Do+0+WxC2PbzzX8GXaUIPyN/VwfePUgYAHD58SE7huU47Lqv/KpS 8Z6y4Q== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 424cy7evfd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:56:45 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4999uit1009243 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 09:56:44 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 02:56:38 -0700 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Jinlong Mao , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Song Chai , , Subject: [PATCH v5 RESEND 4/5] Coresight: Add Coresight TMC Control Unit driver Date: Wed, 9 Oct 2024 17:55:55 +0800 Message-ID: <20241009095556.1754876-5-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009095556.1754876-1-quic_jiegan@quicinc.com> References: <20241009095556.1754876-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: icZObrAzeOH_DPOtQ_jtOlG2ZHwD_tjp X-Proofpoint-GUID: icZObrAzeOH_DPOtQ_jtOlG2ZHwD_tjp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090064 The Coresight TMC Control Unit hosts miscellaneous configuration registers which control various features related to TMC ETR sink. Based on the trace ID, which is programmed in the related CTCU ATID register of a specific ETR, trace data with that trace ID gets into the ETR buffer, while other trace data gets dropped. Enabling source device sets one bit of the ATID register based on source device's trace ID. Disabling source device resets the bit according to the source device's trace ID. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/Kconfig | 8 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-ctcu.c | 292 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-ctcu.h | 21 ++ include/linux/coresight.h | 3 +- 5 files changed, 324 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 06f0a7594169..152eab0b9b2a 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -133,6 +133,14 @@ config CORESIGHT_STM To compile this driver as a module, choose M here: the module will be called coresight-stm. +config CORESIGHT_CTCU + tristate "CoreSight TMC Control Unit driver" + help + This driver provides support for CoreSight TMC Control Unit + that hosts miscellaneous configuration registers. This is + primarily used for controlling the behaviors of the TMC + ETR device. + config CORESIGHT_CPU_DEBUG tristate "CoreSight CPU Debug driver" depends on ARM || ARM64 diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b31..1b7869910a12 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o +obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu.c b/drivers/hwtracing/coresight/coresight-ctcu.c new file mode 100644 index 000000000000..e3a8259a2412 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-trace-id.h" + +DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); + +#define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset) +#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset) + +/* The TMC Coresight Control Unit uses four ATID registers to control the data filter function based + * on the trace ID for each TMC ETR sink. The length of each ATID register is 32 bits. Therefore, + * the ETR has a related field in CTCU that is 128 bits long. Each trace ID is represented by one + * bit in that filed. + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5 + * bit5 + * ------------------------------------------------------ + * | |28| |24| |20| |16| |12| |8| 1|4| |0| + * ------------------------------------------------------ + * + * e.g. ETR0: + * 127 0 from ATID_offset for ETR0ATID0 + * ------------------------- + * |ATID3|ATID2|ATID1|ATID0| + * + */ +#define CTCU_ATID_REG_OFFSET(traceid, atid_offset) \ + ((traceid / 32) * 4 + atid_offset) + +#define CTCU_ATID_REG_BIT(traceid) (traceid % 32) +#define CTCU_ATID_REG_SIZE 0x10 + +struct ctcu_atid_config { + const int atid_offset; + const int port_num; +}; + +struct ctcu_config { + const struct ctcu_atid_config *atid_config; + int num_atid_config; +}; + +static const struct ctcu_atid_config sa8775p_atid_cfgs[] = { + {0xf8, 0}, + {0x108, 1}, +}; + +static const struct ctcu_config sa8775p_cfgs = { + .atid_config = sa8775p_atid_cfgs, + .num_atid_config = ARRAY_SIZE(sa8775p_atid_cfgs), +}; + +/* + * __ctcu_set_etr_traceid: Set bit in the ATID register based on trace ID when enable is true. + * Reset the bit of the ATID register based on trace ID when enable is false. + * + * @csdev: coresight_device struct related to the device + * @traceid: trace ID of the source tracer. + * @enable: True for set bit and false for reset bit. + * + * Returns 0 indicates success. Non-zero result means failure. + */ +static int __ctcu_set_etr_traceid(struct coresight_device *csdev, + u8 traceid, + int port_num, + bool enable) +{ + uint32_t atid_offset; + struct ctcu_drvdata *drvdata; + unsigned long flags; + uint32_t reg_offset; + int bit; + uint32_t val; + + if (!IS_VALID_CS_TRACE_ID(traceid) || port_num < 0) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + if (IS_ERR_OR_NULL(drvdata)) + return -EINVAL; + + atid_offset = drvdata->atid_offset[port_num]; + if (atid_offset == 0) + return -EINVAL; + + spin_lock_irqsave(&drvdata->spin_lock, flags); + CS_UNLOCK(drvdata->base); + + reg_offset = CTCU_ATID_REG_OFFSET(traceid, atid_offset); + bit = CTCU_ATID_REG_BIT(traceid); + if (reg_offset - atid_offset >= CTCU_ATID_REG_SIZE || + bit >= CORESIGHT_TRACE_IDS_MAX) { + CS_LOCK(drvdata); + spin_unlock_irqrestore(&drvdata->spin_lock, flags); + return -EINVAL; + } + + val = ctcu_readl(drvdata, reg_offset); + if (enable) + val = val | BIT(bit); + else + val = val & ~BIT(bit); + ctcu_writel(drvdata, val, reg_offset); + + CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spin_lock, flags); + + return 0; +} + +static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper) +{ + int port, i; + + for (i = 0; i < sink->pdata->nr_outconns; ++i) { + if (sink->pdata->out_conns[i]->dest_dev) { + port = sink->pdata->out_conns[i]->dest_port; + return port; + } + } + + return -EINVAL; +} + +/* + * ctcu_set_etr_traceid: Retrieve the ATID offset and trace ID. + * + * Returns 0 indicates success. None-zero result means failure. + */ +static int ctcu_set_etr_traceid(struct coresight_device *csdev, + struct cs_sink_data *sink_data, + bool enable) +{ + int port_num; + + if (!IS_VALID_CS_TRACE_ID(sink_data->traceid) || + (csdev == NULL) || + (sink_data->sink == NULL)) { + dev_dbg(&csdev->dev, "Invalid parameters\n"); + return -EINVAL; + } + + port_num = ctcu_get_active_port(sink_data->sink, csdev); + if (port_num < 0) + return -EINVAL; + + dev_dbg(&csdev->dev, "traceid is %d\n", sink_data->traceid); + + return __ctcu_set_etr_traceid(csdev, sink_data->traceid, port_num, enable); +} + +static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, + void *data) +{ + int ret = 0; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + + ret = ctcu_set_etr_traceid(csdev, sink_data, true); + if (ret) + dev_dbg(&csdev->dev, "enable data filter failed\n"); + + return 0; +} + +static int ctcu_disable(struct coresight_device *csdev, void *data) +{ + int ret = 0; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + + ret = ctcu_set_etr_traceid(csdev, sink_data, false); + if (ret) + dev_dbg(&csdev->dev, "disable data filter failed\n"); + + return 0; +} + +static const struct coresight_ops_helper ctcu_helper_ops = { + .enable = ctcu_enable, + .disable = ctcu_disable, +}; + +static const struct coresight_ops ctcu_ops = { + .helper_ops = &ctcu_helper_ops, +}; + +static int ctcu_probe(struct platform_device *pdev) +{ + int i; + void __iomem *base; + struct device *dev = &pdev->dev; + struct coresight_platform_data *pdata; + struct ctcu_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + const struct ctcu_config *cfgs; + const struct ctcu_atid_config *atid_cfg; + + desc.name = coresight_alloc_device_name(&ctcu_devs, dev); + if (!desc.name) + return -ENOMEM; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + dev->platform_data = pdata; + + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (!base) + return -ENOMEM; + + drvdata->apb_clk = coresight_get_enable_apb_pclk(dev); + if (IS_ERR(drvdata->apb_clk)) + return -ENODEV; + + cfgs = of_device_get_match_data(dev); + if (cfgs) { + if (cfgs->num_atid_config <= ATID_MAX_NUM) { + for (i = 0; i < cfgs->num_atid_config; i++) { + atid_cfg = &cfgs->atid_config[i]; + drvdata->atid_offset[i] = atid_cfg->atid_offset; + } + } + } + + drvdata->base = base; + drvdata->dev = dev; + platform_set_drvdata(pdev, drvdata); + + desc.type = CORESIGHT_DEV_TYPE_HELPER; + desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; + desc.pdata = pdata; + desc.dev = dev; + desc.ops = &ctcu_ops; + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) { + if (!IS_ERR_OR_NULL(drvdata->apb_clk)) + clk_put(drvdata->apb_clk); + + return PTR_ERR(drvdata->csdev); + } + + return 0; +} + +static void ctcu_remove(struct platform_device *pdev) +{ + struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev); + + coresight_unregister(drvdata->csdev); + if (!IS_ERR_OR_NULL(drvdata->apb_clk)) + clk_put(drvdata->apb_clk); +} + +static const struct of_device_id ctcu_match[] = { + {.compatible = "qcom,sa8775p-ctcu", .data = &sa8775p_cfgs}, + {} +}; + +static struct platform_driver ctcu_driver = { + .probe = ctcu_probe, + .remove = ctcu_remove, + .driver = { + .name = "coresight-ctcu", + .of_match_table = ctcu_match, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(ctcu_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CoreSight TMC Control Unit driver"); diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h new file mode 100644 index 000000000000..ce5c9661623a --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CTCU_H +#define _CORESIGHT_CTCU_H + +#define ATID_MAX_NUM 5 + +struct ctcu_drvdata { + void __iomem *base; + struct clk *apb_clk; + phys_addr_t pbase; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spin_lock; + uint32_t atid_offset[ATID_MAX_NUM]; +}; + +#endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 22b977908f4f..d92530b3fa57 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -71,7 +71,8 @@ enum coresight_dev_subtype_source { enum coresight_dev_subtype_helper { CORESIGHT_DEV_SUBTYPE_HELPER_CATU, - CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI + CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU }; /** From patchwork Wed Oct 9 09:55:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 13828068 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35208191F8E; Wed, 9 Oct 2024 09:57:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467828; cv=none; b=UMMJe+Ya4YrdxR6yfYrYFXarUNbZNW+oXJMtVhzEdony93avAZuK2eavG9yMTb2W6nXaJfeVLfbTn1a6Z/qLzFFfahROYL3vYd6cSdyMm0c/do3UOsEyYMashHZvqluVBhVFHIhCCeQVMQhfsXSXYBPk6EgPvNtoMO8gkuwz+R0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467828; c=relaxed/simple; bh=+4lnVmz1HkbC5gG9G3ZPV4NnrsBsSmQNOr/IMQ2D4sY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TJ4RqtcV8Koa11UHPOunHvADUnDJoKrIYe2DJpd9pFoi6VJ1pDESSdDFcu4Tgxye2v4f3sfuPug1JSADixRoKkijMGAIbnlm0DlhC9ln+4kvIv5hJlpUI6BXoQpi5pa4biG3Q2KJuBzTegVuGahMlEy8MxEEpxC0jiZ6OpHPivQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ckTmee2b; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ckTmee2b" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 498NLZLl000960; Wed, 9 Oct 2024 09:56:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= osMgB0mb3XqW8YTk8xRMOzQT5xdZ8ZkzCS7pK5HdoYo=; b=ckTmee2bbuZQm+Z0 n0UZwP3xDqGzFlStVz6mjKsgZX8r2su2MsjnA9zi7B5efI+/ghEwDpFSfz7dik51 67F+XAZFkwwus4XZzT78FI8aJjYj5aMvL0X6ajRt+S1KFmsCloYlzXgWD7xp7Rel 6PTzvlM0ooU5onseEQgA8Oz3T1jw/+8hnnBkBQw1bv1ORPAX/za0y9LGdxBXnunc /ru8VslWtpf7EBV+xCOIkj9IepOXuJO1g1sp8xrtfiCADhn+ptfkPAo0VUhzCkNs sBGSO/ucFvi7ZqAV9HoxGJ4BfcvCy7+TcqEtD7T/A/aU027hWaOeGh00Zbf1p/L7 PwbbNQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4252wsudec-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:56:51 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4999uoeU009291 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 09:56:50 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 02:56:44 -0700 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Jinlong Mao , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Song Chai , , Subject: [PATCH v5 RESEND 5/5] arm64: dts: qcom: Add CTCU and ETR nodes for SA8775p Date: Wed, 9 Oct 2024 17:55:56 +0800 Message-ID: <20241009095556.1754876-6-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009095556.1754876-1-quic_jiegan@quicinc.com> References: <20241009095556.1754876-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: C7TOMid0qv6D2edSgbWJSU15T2LeueCa X-Proofpoint-GUID: C7TOMid0qv6D2edSgbWJSU15T2LeueCa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 spamscore=0 mlxscore=0 suspectscore=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090064 Add CTCU and ETR nodes in DT to enable related functions. Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 160 ++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..a8b509495440 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1664,6 +1664,35 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + ctcu@4001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x0 0x4001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ctcu_in0: endpoint { + remote-endpoint = + <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + ctcu_in1: endpoint { + remote-endpoint = + <&etr1_out>; + }; + }; + }; + }; + stm: stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x4002000 0x0 0x1000>, @@ -1867,6 +1896,129 @@ qdss_funnel_in1: endpoint { }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x4046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = + <&etr_rep_in>; + }; + }; + }; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = + <&swao_rep_out0>; + }; + }; + }; + }; + + tmc_etr: tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x4048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = + <&ctcu_in0>; + }; + }; + }; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = + <&etr_rep_out0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etr_rep_out0: endpoint { + remote-endpoint = + <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + etr_rep_out1: endpoint { + remote-endpoint = + <&etr1_in>; + }; + }; + }; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = + <&qdss_rep_out0>; + }; + }; + }; + }; + + tmc_etr1: tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = + <&ctcu_in1>; + }; + }; + }; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = + <&etr_rep_out1>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -1942,6 +2094,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + swao_rep_out0: endpoint { + remote-endpoint = + <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; swao_rep_out1: endpoint {