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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 1/6] xen/arm: Skip initializing the BSS section when it is empty Date: Thu, 10 Oct 2024 15:03:46 +0100 Message-ID: <20241010140351.309922-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010140351.309922-1-ayan.kumar.halder@amd.com> References: <20241010140351.309922-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002319:EE_|CY8PR12MB7660:EE_ X-MS-Office365-Filtering-Correlation-Id: 66456338-bf59-4d11-e413-08dce934895e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: Q0yFZtAMVMj3pS+ctfs7eUMLxNUCw3aIGuWQiO8oZ04dumzbHECvLQ03zKlneK8zqIuTf3NSU6Xn2EkmhPQoDO08KR11ULSDSepd+Q5prh7Uul4f6m/tQvPyT0h+pftYMnJsROIAEnbIghs63pkTUFMWmVghasBRpz071SCSIeuNoEmdoQY33FTVqYKkUgmEkpXUnwjZhVdC5VbxbQli0g2rdazmLyP7ka8lL6En1AkdSDhH+D/8CnSsD5W2sfDhfDt2P2r5JDCX9i5wV6Sa87EbmA94+FnSZxtBLCf30ohF5obtE750AqyuJPmxVE026rgjH+LKWUXWGgEV+b3XDxOwJrZFbvL64/HfWBXMzvw60G4qzjszETOfYnoSftWXhEPT6mMQBr8OttLmv/d7aNNL/eRh6zVKqRYzAa/InT3lpTVjkICfQL4LTbXpX5THi484BHC+jwO2eW2w4m7TRf2NXroUAZTh+irFOwWcTasCEOIj5yR2x5wAquqOjuE6hvybQECDkpiz7DhOT9Dy3IUg2QKqoyLC0Ui4QLM80MNkbgyNsEYsRNWiLzb6AjHeNTQ3gdJC6wUERGzoXKSUfRhB/8r1W5T94H7MTbPY+1C2pMHvUh7ieQE8tDguS8ANqF1wAITliKnF+MhW6/doF6HjJfOEJt6ophikUBfIZa5it9J47bztsPylkaFxkLKxXcKvgrfCRE0DFcSAV+5pi1S/aG2+BzXgpBYtnaf60LiU6kX3X+7nKMJxlFpcaaYxrYLhRNPrRThcwkxk7SAsL3S7sfDb8MrivWavruQd7ZNIWYHc1TbeAhuxtLU5ARM7SsOXqW3GnNiqwdS+wTlr/S7GQ5HpMamvieSiH/dMMAGDvc+z+2zwaKhk8ZhA6Qqa+wjUeFNo9nZjTPursi2jf8USAN9BUzBtZAKZyQCCESjUc+A+7IDZPLJHHrLYzbLxCge0oeBRYPijc6h5KjIqcnujoraDyjqQCXJHGh8uv1AiS6O2T4mWDPQwlU3GJwq9DP8PRCQYwz3WsR0Ew1OuE0Z6QT2BxkVcla+K2cxPZlrxy4t4ssvTnriGvfOnK/Rl480lEEWX7v8AqEsMrRo4ETXGMMqHYp60waPhu1Dq7cXhYbDoI9Z5gzOU97eIEo4v1XE0bSRSuj8mpgWgBOqs2YZJ4WmGM038y9W1//MUymuXKTVAvk+0r5tNTjb1UIPNJ7qP1ADA/GqfRewwVGJD1YUthvXvJY2annby6OG9Txm+ye5h24fU7WcV1CvQBwdrlZ3AtpuBRabzQ2WkgP2wiTh2LhYEXFZei8PgpJTeeJwA/jdeWneCj0OGKu/d+beIqNTcWeYhP1MN8FHwmZI561bcMInKO96EkW94MgGVinc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 14:05:03.0630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66456338-bf59-4d11-e413-08dce934895e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7660 If the BSS section is empty, then the function can just return. Signed-off-by: Ayan Kumar Halder Reviewed-by: Frediano Ziglio Reviewed-by: Luca Fancellu > --- Changes from :- v1..v2 - New patch introduced in v3. xen/arch/arm/arm64/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 14c3720d80..72c7b24498 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -346,6 +346,8 @@ FUNC_LOCAL(zero_bss) PRINT("- Zero BSS -\r\n") ldr x0, =__bss_start /* x0 := vaddr(__bss_start) */ ldr x1, =__bss_end /* x1 := vaddr(__bss_end) */ + cmp x1, x0 + beq skip_bss 1: str xzr, [x0], #8 cmp x0, x1 From patchwork Thu Oct 10 14:03:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13830171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93530CF11F5 for ; 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bh=h8Bq//NZ4qXsynzh+qjTiZ5t/d9zK4Vri+C1Mc3rvDw=; b=tBecdr2AIAyliFsoKsu4+h4/9m1XSIl8VDOy6HhL2FD4nOrQat6JVWaIluuKo97exSeNtbu4GLM0iEEhUZnhx/PsOLGziyIeT7sHcyF3lHAOmE+6SmCS3je5Thr7wLOA8mYLDsEo8KvfzNPhaareo7nZAShxYK7k+CyIiazsmr8= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 2/6] xen/arm: mpu: Introduce choice between MMU and MPU Date: Thu, 10 Oct 2024 15:03:47 +0100 Message-ID: <20241010140351.309922-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010140351.309922-1-ayan.kumar.halder@amd.com> References: <20241010140351.309922-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|SN7PR12MB7371:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ba66ff0-fd03-4bbc-85f3-08dce9348b6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: CEXySuepL7ELKM+T4XL1zP6UtnbBYFoaJwTAESN2hovTleLIm4bRZzNhAf9R6/9lL4cjjv+V+wu0uUQdk0kF2q7anSkaqEvK/JmIf40ELH2KKV8VqHqRu5dfLVtNdGq3wj2SqBLb3OzMOmDFKY0ql66Xgm5a0jyrOFGJcsl5dV1Rh8IhwXia+3S1RLVktnZs4MgqBEBpMf17g9GzMWeku1RN7ugIuqzicz9CGSWl0FdkNnlcFsMEblUD94sEgnOfNzjNOyN8XC3GYasYW04Uv39QqKEy2140Iho8hsYBUm/V6lU9dEI12Xgyi0VHkkAbMEMKTtIS2Qa/BNXWR1+4IMWvwDUTke/Y1dVHOxHvKUiNUooodJ/+MoV3J4opsOav4Rzhpn4WmhWiHYvfzU/05AwZBpdVxM4UZ7n0qDnaFRJSboqG+crfyqZDw1+L8jUMqk2MQfTASHIGqFtMnPAGCwYGvvj7BaELlGJTqMF2LSPHVSrqkh7FSB6YPGUuuQGBMtOB6fkl9G4rJmsKRfZAGn8z+c7mDFpsVkMIkQvZxXJBsf2WlkEOcnUW5qX00iOLRLMKHfLv/C5CiD54ujabBPG84TMX7O3N1+GZUUry1SoI21ei3kfpmJMBRdoRAP3atNwCaIwPG5jFF1+IW8FbnAwWJqyxeZ28wpWkt94BkxRNSuP/1KQNajsuOx6xGC4AyEMss0zcJl6D3pm3vopAmeoiNd090MCpaP5fEMHWwusVwYybL+TDyiM8Dv6s2GWEokvvlGHF1QrPZEJ0EA3pulEZO1ueGkhiCKSChZy7bc/o0S9FzAHsd4PWpPV1W1pRyjF9UQcr4EYuJPpPzqQKK/O4KkNsMRvU0e5tWo2Rdrt1IBaJ2CffdYrE2w4nd+d/blqeyQ4zZDrHdhia6mO63K2h6kpcxRVODp9YQpDYEnXSAcSBPAW260PUc2DVIQoADr75AvDEcKvl8D4/F6Nrli5qekdEKeWGu6D/DnQwzk0BDmdMAbw3aqapF9NpkusRHnd1k+l/wOIB6Gt7fw1lvVOI/4fgtDjpsgWP/nKIUVC4aRcryjnoCmkPs/HTRS0Qw0DN12MLSbv83YQXtiuaWkftkhtsufzEFTDy/kdp/7oyMwl3ZH0jOw4SiakSFGnk+asyYO16ZTjie9NrqgfbRlI0bqKPDOW+JEUZ3RFMzxZqRYaasu3UJYfpBzKPfZfDvgSh6q8BcJHmbjd/0fJTwovNTA6Hh7rfvxtm/977ZMmwH7VKh1MokOIqsc+Fwtblx00DYY+uAIpSOHrIcUTnJ0SSgW6DcpPSYu04B2ep2G44vGPM3uvM9TuernBXF07ykg4X4TBYgUTtnJEqKlsJZ2/5wxF0gEu7Pjf0ovbaNnSiGzUcCXroQqA1wI9x7Zu5 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 14:05:06.5743 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ba66ff0-fd03-4bbc-85f3-08dce9348b6f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7371 There are features in the forthcoming patches which are dependent on MPU. For eg fixed start address. Also, some of the Xen features (eg STATIC_MEMORY) will be selected by the MPU configuration. Thus, this patch introduces a choice between MMU and MPU for the type of memory management system. By default, MMU is selected. MPU is now gated by UNSUPPORTED. Update SUPPORT.md to state that the support for MPU is experimental. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. Reworded the help messages. 2. Updated Support.md. v2 - 1. Reworded the help message. SUPPORT.md | 1 + xen/arch/arm/Kconfig | 17 ++++++++++++++++- xen/arch/arm/platforms/Kconfig | 2 +- 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index 23dd7e6424..3f6d788a43 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -40,6 +40,7 @@ supported in this document. Status, Xen in AArch64 mode: Supported Status, Xen in AArch32 mode: Tech Preview + Status, Xen with MPU: Experimental Status, Cortex A57 r0p0-r1p1: Supported, not security supported Status, Cortex A77 r0p0-r1p0: Supported, not security supported diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 323c967361..ed92eb67cb 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -58,10 +58,25 @@ config PADDR_BITS default 40 if ARM_PA_BITS_40 default 48 if ARM_64 +choice + prompt "Memory management system" + default MMU + help + User can choose between the different forms of memory management system. + config MMU - def_bool y + bool "MMU" select HAS_PMAP select HAS_VMAP + help + Select it if you plan to run Xen on A-profile Armv7+ + +config MPU + bool "MPU" if UNSUPPORTED + help + Memory Protection Unit (MPU). Select if you plan to run Xen on ARMv8-R + systems supporting EL2. (UNSUPPORTED) +endchoice source "arch/Kconfig" diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig index 76f7e76b1b..02322c259c 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -1,5 +1,5 @@ choice - prompt "Platform Support" + prompt "Platform Support" if MMU default ALL_PLAT help Choose which hardware platform to enable in Xen. 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pr=C From: Ayan Kumar Halder To: CC: Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , "Jiamei . Xie" , "Ayan Kumar Halder" Subject: [PATCH v3 3/6] xen/arm: mpu: Define Xen start address for MPU systems Date: Thu, 10 Oct 2024 15:03:48 +0100 Message-ID: <20241010140351.309922-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010140351.309922-1-ayan.kumar.halder@amd.com> References: <20241010140351.309922-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|DS0PR12MB9322:EE_ X-MS-Office365-Filtering-Correlation-Id: 3da93431-0be4-45c9-48b8-08dce9348d58 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: +cHP+ZeU31cyEeSKd+IpiDx5e5P8r1ReZ5DfDWANa/Gu1Tp/wCtgkkytu+3156281hvJT3/s2LFRVl5RGbl8+wxVEy2LpkezGVNYSroiC9Nad+MPyukbvTclkHhn1Ry3B4XnesdUrzFntGiC3aIX3HM0QnOjcx+wIgBsc3FvMqsWhy0mwpYQljOv/fMlNYvxKusg17+Z8HPnD7rDSR3zDY3KdMLED7AR4AEPsd080K5vkeUMAOOCjQX3RGVD0nDXmEH12QuzG3DA7YpaSewxDVzxrSTSpgs/l5G1AJAVpClURbuVNLnNg2MIAopJ46eNthb+HIgPyju7sDanD8uKiUDyYH7pWzdGpLSl6LwUs410qqdViWJvGAXP9O0TjvdOcaxTBknDeHyMtHBsqkHEJCgXy06PgzBtNcJpWETbsj+F7p2bIQW44J2bISbyjOhdSAKMP0/JiBRE2FicGd45uTt415kWTRxmLoOrRZ/ot4LRaQKctp9fO0gYSOQK2thf79y30AJwYre7DDTPmMlzq4yXnYbxl0ztONYyPj+nHOFeb7KrGRmQzhLq7k5aF3QTyjgHMGJ5jHNuvOiwRU+WKTSXosVTtJP7qw3rvEQOCwfKgftWN8y1jOpLMgUPUuepPRXA2JLuj6Q/0hZpE2xopcBOirwEaVnoJMPwmPrHsNnCcusJgYhW5Ehzp3GsJ5PGoG5r0uE7KrOB5680toUF0BE+LGiArMFiMUd+coefOnQ5z83RQR5+HRxN68Jv/jWwx1QR46ckUQ6T0RQ0KybkpUrPJ7R3moxx+3fhdb4W9gHGJDTGpA/iX7bDXeWYTFPpaxx2m73B2ZdqmISjbiMwAFT3dNzWUsB5jT9KDKmgSRHwM8zpZ2/Ks6SMGDOXT3I1GAMiXCFxR9Deym23Q7mNAwKjrcOiWOtNTtAOZQ2RAVB8S5KE/e3AaRa03VZRqHjmY1Whmm6QDt2uYy0XGTwfDW6lAapk9MXyjr2gesP8jHpuTkttpMGOCs/ZppmhSK09O80CpW4hpfD1OBsKfN44QIQSIJL7CqVjObgkyXwnnqJHmLn5mx1WcwrZJkiiaDlTC1IFCtijkCH0qVLyilRHVTjCWGfjAbuF7yI7fNh9S4EFKqMYd63KpKhuwifIvLzawkVcgm2yPmUhpSNXYLD9Neh7DQYXKzZfypZVH9Khc0wJ281OMBonc64hLK/F6uU840UVIxh7zOmz5Cw0tj5PRsfrEs37cjBSVFcIw/msbs58iwPPbBNZVrGYWfRYgWSiDtpnkrr6M+LBxxDEdcEd3XJNvGGXVW2co7G/bEwho8gfpL37PVJQlF0zEX9JgjQ9+7eQ/p+8bdjGZX3DwTNiyfQVnQd9PlOMG4oXY6jMEjsoHliBnVOQE+HCDgHBrTjt X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 14:05:09.7774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3da93431-0be4-45c9-48b8-08dce9348d58 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9322 From: Wei Chen On Armv8-A, Xen has a fixed virtual start address (link address too) for all Armv8-A platforms. In an MMU based system, Xen can map its loaded address to this virtual start address. So, on Armv8-A platforms, the Xen start address does not need to be configurable. But on Armv8-R platforms, there is no MMU to map loaded address to a fixed virtual address and different platforms will have very different address space layout. So Xen cannot use a fixed physical address on MPU based system and need to have it configurable. So, we introduce a Kconfig option for users to set the start address. The start address needs to be aligned to 4KB. We have a check for this alignment. MPU allows us to define regions which are 64 bits aligned. This restriction comes from the bitfields of PRBAR, PRLAR (the lower 6 bits are 0 extended to provide the base and limit address of a region). This means that the start address of Xen needs to be at least 64 bits aligned (as it will correspond to the start address of memory protection region). As for now Xen on MPU tries to use the same memory alignment restrictions as it has been for MMU. Unlike MMU where the starting virtual address is 2MB, Xen on MPU needs the start address to be 4KB (ie page size) aligned. In case if the user forgets to set the start address, then 0xffffffff is used as default. This is to trigger the error (on alignment check) and thereby prompt user to set the start address. Also updated config.h so that it includes mpu/layout.h when CONFIG_MPU is defined. Signed-off-by: Wei Chen Signed-off-by: Jiamei.Xie Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. Fixed some of the coding style issues. 2. Reworded the help message. 3. Updated the commit message. v2 - Added clarification for the use of page and page size. xen/arch/arm/Kconfig | 10 ++++++++ xen/arch/arm/include/asm/config.h | 4 +++- xen/arch/arm/include/asm/mpu/layout.h | 33 +++++++++++++++++++++++++++ xen/arch/arm/setup.c | 8 +++++++ xen/arch/arm/xen.lds.S | 6 +++++ 5 files changed, 60 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/include/asm/mpu/layout.h diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index ed92eb67cb..15b2e4a227 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -23,6 +23,16 @@ config ARCH_DEFCONFIG default "arch/arm/configs/arm32_defconfig" if ARM_32 default "arch/arm/configs/arm64_defconfig" if ARM_64 +config XEN_START_ADDRESS + hex "Xen start address: keep default to use platform defined address" + default 0xFFFFFFFF + depends on MPU + help + Used to set customized address at which which Xen will be linked on MPU + systems. Must be aligned to 4KB. + 0xFFFFFFFF is used as default value to indicate that user has not + customized this address. + menu "Architecture Features" choice diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/config.h index a2e22b659d..0a51142efd 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -69,8 +69,10 @@ #include #include -#ifdef CONFIG_MMU +#if defined(CONFIG_MMU) #include +#elif defined(CONFIG_MPU) +#include #else # error "Unknown memory management layout" #endif diff --git a/xen/arch/arm/include/asm/mpu/layout.h b/xen/arch/arm/include/asm/mpu/layout.h new file mode 100644 index 0000000000..d6d397f4c2 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/layout.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_LAYOUT_H__ +#define __ARM_MPU_LAYOUT_H__ + +#define XEN_START_ADDRESS CONFIG_XEN_START_ADDRESS + +/* + * All MPU platforms need to provide a XEN_START_ADDRESS for linker. This + * address indicates where Xen image will be loaded and run from. This + * address must be aligned to a PAGE_SIZE. + */ +#if (XEN_START_ADDRESS % PAGE_SIZE) != 0 +#error "XEN_START_ADDRESS must be aligned to 4KB" +#endif + +/* + * For MPU, XEN's virtual start address is same as the physical address. + * The reason being MPU treats VA == PA. IOW, it cannot map the physical + * address to a different fixed virtual address. So, the virtual start + * address is determined by the physical address at which Xen is loaded. + */ +#define XEN_VIRT_START _AT(paddr_t, XEN_START_ADDRESS) + +#endif /* __ARM_MPU_LAYOUT_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 71ebaa77ca..0203771164 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -295,6 +295,14 @@ void asmlinkage __init start_xen(unsigned long fdt_paddr) struct domain *d; int rc, i; +#ifdef CONFIG_MPU + /* + * Unlike MMU, MPU does not use pages for translation. However, we continue + * to use PAGE_SIZE to denote 4KB. This is so that the existing memory + * management based on pages, continue to work for now. + */ + BUILD_BUG_ON(PAGE_SIZE != SZ_4K); +#endif dcache_line_bytes = read_dcache_line_bytes(); percpu_init_areas(); diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index bd884664ad..fe4b468cca 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -231,6 +231,12 @@ SECTIONS */ ASSERT(_start == XEN_VIRT_START, "_start != XEN_VIRT_START") +/* + * On MPU based platforms, the starting address is to be provided by user. + * One need to check that it is 4KB aligned. + */ +ASSERT(IS_ALIGNED(_start, 4096), "starting address is misaligned") + /* * We require that Xen is loaded at a page boundary, so this ensures that any * code running on the identity map cannot cross a section boundary. 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 4/6] xen/arm: mpu: Create boot-time MPU protection regions Date: Thu, 10 Oct 2024 15:03:49 +0100 Message-ID: <20241010140351.309922-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010140351.309922-1-ayan.kumar.halder@amd.com> References: <20241010140351.309922-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017092:EE_|CY8PR12MB8215:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c4871be-9274-48ad-2b47-08dce9348f93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: 6Rffq8JctN6kev/ygMamkIvFks+eb7wZsO9yqaafKFdYwpHvi8y6KidVXU0SXMTbRNjeA2zS9a/VhaFe3nQinZEzq4XfciWH2wGt42qHROgh8iYqUJ4wEoYDt+qMFqj49KeXIu/zzzQ2D0wOtcNbbbsKetzCNsr8RgvbQjfTz0n1Td+RMq/+Y4x2X1iADdRrGw/Qe+/n5JguS14y2cica4ApbZeCAf8Tx5HF8bNya+EbnOWNj+MJwvAtV3Ib4l0WdAD+poCu6ffONU/NKKZXDAgg0YDAAPpxdYhRsp/faV7qtZZKYmvKOKPkAyXG8fI9Q4TmzhHQGIktRuWWvrwJj9zxNEiSXuahbVc6PBBwUWAHIGaZqVGYBTHu4aXEPSudetGmu2ZS2jSPHmqRgEBHB1DRD7wXu9tA8tpx6vRPePEfGOsbKDJf09XlmhsawQtFqKIe+IovHNtJY/BNkp4tpKspanhQqI6iVsDkbfmYh3qoTNFbKNpNjhwwm2cFXaMH2zAb8kzXABrb/zOdxvjFjs86so09kd+6klhShkKYfVH7P2zJiFDuzyxB3HSLXetSghsuz2vMyOcFqs1Q1GcvPBp13/ZpGIDVz9389Po60wdQ3g3+NwOZNa/s7i2MtAwVm1Yxq2GGNyVO3JWEVN1AcmpTbRGO7TZw40xmmHa+kzEzmGJa5qucH8SRj3Y7dAplqcHOwmQNUyCWJVlpK57wyrmMIc2Jfz8oL8tsSXMh6gP5Mww9hHn5WLChSyjbwKEpN1u1NjpZ5lK/pjJtE+FIuXovvODhCLGJ8fS54IczMnU13XFeJPMh6c5B/a41OR4Xm+i2kGLM9eFHSgiK0oKpswBsWOMHA3ZiG+QLH20djbnRtaPAxIXFYMxqsCzaBX+5/jx2hEcFqy8PbwbA8Mb+OGoDxivmtFeWZTTKyV5Whmpg5pifSqVK6mwSLA6Pgohuvxmc2zU8qLI642Qh03Cj2i51Mwj+cPoz3H1dAPX2LBldFIS0O9lDGV2Qy1+F83ndFkVIY5tfwbxj0enXxK3EmxXZC2pnZJq/6KKBvrMD609eP04a6FCQJ07SOBXKY5S8RSk5f5atyMiKS0rIM9zxn8Pq4vJEdw7Xlt90u+Tt7V7PFAWStKaGE5Pbv1ZhyjztBCh0kPxzyeszMARgsuOMQc7uscDtlJspeCfGyd83rS9Z5al0ulj3np6cr4xHP9NAg+zORcvpTWBqxm5Oh2a/qvPEtgTDO8jxxwEGsI415G3foDVOuHKrkACgzdCXniX+brgSsnTvJ0uKfq2DXBc3n5kABzgbrOs4hfyoXTDfcUsSLcJJkDlcNUKIX/zR9YzrzYNCji5lfRSNDzhQpknP9OCGGn9koZ0El9ljwwcYbtZZXcH6kKG4AmdO1k87Ap1n X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 14:05:13.5032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c4871be-9274-48ad-2b47-08dce9348f93 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017092.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8215 Define enable_boot_cpu_mm() for the AArch64-V8R system. Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from normal memory. To do this, Xen maps the following sections of the binary as separate regions (with permissions) :- 1. Text (Read only at EL2, execution is permitted) 2. RO data (Read only at EL2) 3. RO after init data and RW data (Read/Write at EL2) 4. Init Text (Read only at EL2, execution is permitted) 5. Init data and BSS (Read/Write at EL2) Before creating a region, we check if the count exceeds the number defined in MPUIR_EL2. If so, then the boot fails. Also we check if the region is empty or not. IOW, if the start and end address of a section is the same, we skip mapping the region. To map a region, Xen uses the PRBAR_EL2, PRLAR_EL2 and PRSELR_EL2 registers. One can refer to ARM DDI 0600B.a ID062922 G1.3 "General System Control Registers", to get the definitions of these registers. Also, refer to G1.2 "Accessing MPU memory region registers", the following ``` The MPU provides two register interfaces to program the MPU regions: - Access to any of the MPU regions via PRSELR_ELx, PRBAR_ELx, and PRLAR_ELx. ``` We use the above mechanism for mapping sections to MPU memory regions. MPU specific registers are defined in xen/arch/arm/include/asm/arm64/mpu/sysregs.h. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Instead of mapping a (XEN_START_ADDRESS + 2MB) as a single MPU region, we have separate MPU regions for different parts of the Xen binary. The reason being different regions will nned different permissions (as mentioned in the linker script). 2. Introduced a label (__init_data_begin) to mark the beginning of the init data section. 3. Moved MPU specific register definitions to mpu/sysregs.h. 4. Fixed coding style issues. 5. Included page.h in mpu/head.S as page.h includes sysregs.h. I haven't seen sysregs.h included directly from head.S or mmu/head.S. (Outstanding comment not addressed). v2 - 1. Extracted "enable_mpu()" in a separate patch. 2. Removed alignment for limit address. 3. Merged some of the sections for preparing the early boot regions. 4. Checked for the max limit of MPU regions before creating a new region. 5. Checked for empty regions. xen/arch/arm/Makefile | 1 + xen/arch/arm/arm64/mpu/Makefile | 1 + xen/arch/arm/arm64/mpu/head.S | 130 +++++++++++++++++++ xen/arch/arm/include/asm/arm64/mpu/sysregs.h | 27 ++++ xen/arch/arm/include/asm/mm.h | 2 + xen/arch/arm/include/asm/mpu/arm64/mm.h | 22 ++++ xen/arch/arm/include/asm/mpu/mm.h | 20 +++ xen/arch/arm/xen.lds.S | 1 + 8 files changed, 204 insertions(+) create mode 100644 xen/arch/arm/arm64/mpu/Makefile create mode 100644 xen/arch/arm/arm64/mpu/head.S create mode 100644 xen/arch/arm/include/asm/arm64/mpu/sysregs.h create mode 100644 xen/arch/arm/include/asm/mpu/arm64/mm.h create mode 100644 xen/arch/arm/include/asm/mpu/mm.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 7792bff597..aebccec63a 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_ARM_32) += arm32/ obj-$(CONFIG_ARM_64) += arm64/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_ACPI) += acpi/ obj-$(CONFIG_HAS_PCI) += pci/ ifneq ($(CONFIG_NO_PLAT),y) diff --git a/xen/arch/arm/arm64/mpu/Makefile b/xen/arch/arm/arm64/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm64/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S new file mode 100644 index 0000000000..4a21bc815c --- /dev/null +++ b/xen/arch/arm/arm64/mpu/head.S @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include + +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * Inputs: + * sel: region selector + * base: reg storing base address (should be page-aligned) + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + add \sel, \sel, #1 + cmp \sel, \maxcount + bgt fail + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + msr PRSELR_EL2, \sel + isb + msr PRBAR_EL2, \prbar + msr PRLAR_EL2, \prlar + dsb sy + isb +.endm + +/* Load the physical address of a symbol into xb */ +.macro load_paddr xb, sym + ldr \xb, =\sym + add \xb, \xb, x20 /* x20 - Phys offset */ +.endm + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different MPU + * regions. + * + * Inputs: + * lr : Address to return to. + * + * Clobbers x0 - x5 + * + */ +FUNC(enable_boot_cpu_mm) + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + mrs x5, MPUIR_EL2 + + /* x0: region sel */ + mov x0, xzr + /* Xen text section. */ + load_paddr x1, _stext + load_paddr x2, _etext + cmp x1, x2 + beq 1f + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_TEXT_PRBAR + +1: /* Xen read-only data section. */ + load_paddr x1, _srodata + load_paddr x2, _erodata + cmp x1, x2 + beq 2f + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_RO_PRBAR + +2: /* Xen read-only after init and data section. (RW data) */ + load_paddr x1, __ro_after_init_start + load_paddr x2, __init_begin + cmp x1, x2 + beq 3f + prepare_xen_region x0, x1, x2, x3, x4, x5 + +3: /* Xen code section. */ + load_paddr x1, __init_begin + load_paddr x2, __init_data_begin + cmp x1, x2 + beq 4f + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_TEXT_PRBAR + +4: /* Xen data and BSS section. */ + load_paddr x1, __init_data_begin + load_paddr x2, __bss_end + cmp x1, x2 + beq 5f + prepare_xen_region x0, x1, x2, x3, x4, x5 + +5: + ret + +fail: + PRINT("- Number of MPU regions set in MPUIR_EL2 is too less -\r\n") + wfe + b 1b +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/mpu/sysregs.h b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h new file mode 100644 index 0000000000..b0c31a58ec --- /dev/null +++ b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_ARM64_MPU_SYSREGS_H +#define __ASM_ARM_ARM64_MPU_SYSREGS_H + +/* Number of EL2 MPU regions */ +#define MPUIR_EL2 S3_4_C0_C0_4 + +/* EL2 MPU Protection Region Base Address Register encode */ +#define PRBAR_EL2 S3_4_C6_C8_0 + +/* EL2 MPU Protection Region Limit Address Register encode */ +#define PRLAR_EL2 S3_4_C6_C8_1 + +/* MPU Protection Region Selection Register encode */ +#define PRSELR_EL2 S3_4_C6_C2_1 + +#endif /* __ASM_ARM_ARM64_MPU_SYSREGS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 5abd4b0d1c..7e61f37612 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -16,6 +16,8 @@ #if defined(CONFIG_MMU) # include +#elif defined(CONFIG_MPU) +# include #else # error "Unknown memory management layout" #endif diff --git a/xen/arch/arm/include/asm/mpu/arm64/mm.h b/xen/arch/arm/include/asm/mpu/arm64/mm.h new file mode 100644 index 0000000000..c2640b50df --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/arm64/mm.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * mm.h: Arm Memory Protection Unit definitions. + */ + +#ifndef __ARM64_MPU_MM_H__ +#define __ARM64_MPU_MM_H__ + +#define MPU_REGION_SHIFT 6 +#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT) +#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1)) + +#endif /* __ARM64_MPU_MM_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h new file mode 100644 index 0000000000..92599a1d75 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_MM__ +#define __ARM_MPU_MM__ + +#if defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* __ARM_MPU_MM__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index fe4b468cca..2c9b5ee238 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -157,6 +157,7 @@ SECTIONS *(.altinstr_replacement) } :text . = ALIGN(PAGE_SIZE); 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v3 5/6] xen/arm: mpu: Enable MPU Date: Thu, 10 Oct 2024 15:03:50 +0100 Message-ID: <20241010140351.309922-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010140351.309922-1-ayan.kumar.halder@amd.com> References: <20241010140351.309922-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|CH3PR12MB9028:EE_ X-MS-Office365-Filtering-Correlation-Id: cac452d3-b6cf-4be0-234f-08dce9349408 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: cYUyyQqg9on/VleGmm0+q6Q9WTg5yozdWASHwjQU86Yd/iRHLp8oYDV+posV8Af7Q6EjeVlQDK5Asv64QmM9GGlRj5FhoDZmRNT37ECTGw5+Iw9b/j5meZAZH2JMTIhD8Kfq6xZ+qJ2kn/ov3KzIKWI1KXnbeXU0kEWGYRbvNCWGVzs+bBNvNktYD0xWiO/g9zmNjMNjEJXobr+1f3WCO2IRwE190YlnAnEPXGRMGatektKA7ojnfuLBjKaCcBXJba+rVUGFNcrhBoQTRF3+qOfGoRTNZgQb1Bn/EiengQOS1vvHs6uGk1yBlPXuK047a218RaKA0eESZ4dReucFzfBFPA/QKCQwhAEQHYWnedkqjQeUd5LWG1o5GjMBjzrTtOZWZXEoTayuJOGlMybd4aFraNBFO7RvAai2oWGV2oqVUJT9lgkfcy87JJgWYsbLjADC879r/mq+xHvDmLQM7FzmmXdDhejHRihM99fYrLE+bgfefsE5Riu2ghVJVuy8kD0qby90GRsBlsMc8nx2uCv+hyUh7AdwEsBhqIr4BN6/sXxl1k3KwgKQKrYM51OLC9CGCl8UgKLeTN1uxKhkOItSW747IY5u+ANsR39C6ZT8OoaU288fU1WqOzKJ/ucb+2Veen1bgdLueAxE3q9eNTnIoCc8HIDlnZMpXpl+ThCeXYs0NB9ALYNutjbm4suFLC6ukg8ho8po2Qz6qrcOoj192/VsUfCaNgS9k8ZOBxEWTspcEYgOWaI5PbLKKXvH0nMCxc8ZeCox3Zls2jLg3RTWh1y6Fp8myb+rbl+o4+tS6Ex9DBwk5yjAAmHePf7AqMWY7qNyfFg5k3WFMRZyOM7uajFCx4qv9qi+ZjReWDxPXc5eaLz2z3p1Cmw1uIQ+4goUUelsJDbIisAJYNe9smMMG5qq6DpgSDa3ZC5yGeSlcX/7UfS7cCCSXuVAJT7yuUPs3B9Wx3USLz9QJar2bPjSnH0aBjokQ8+nQOSyjtd8JQy/7tzUz3oK/PVDJAmE+XXBlhFzNBT+BsJSI8lANw37o+VaUMOV7NxuzNc6aPOfqHpOsw+W6yh6ZbsDNTmwNIQdKxdVffWBN/BtpFOZfzlYD6dwa5G2BdUAQuUImosjPIW56UIXxC5IY8sdk6ncdyFy/dDOCuXXsn7i7xNQP5cETJyXrfri8MwxxqGPqi8GKRdT1FWuBUw4Mm2S6PmFrDvgu2uvN70CTsx/hlJAmSJaCsmY6aFFm4xP2INb9rgRA/NJfdduM0gifKV1S5XU/pqttYg5vd5QBBgUvkX7ckN8e5YvBGvJ33ZAr5Q6i+G9wEXieTMhGz1rv7UFefNppNquz1/YF3OmEa7Qcmc+azf+5N8L455TyYLIlWuY/hs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 14:05:21.0119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cac452d3-b6cf-4be0-234f-08dce9349408 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9028 After the regions have been created, now we enable the MPU. For this we disable the background region so that the new memory map created for the regions take effect. Also, we treat all RW regions as non executable and the data cache is enabled. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v2 - 1. Extracted from the previous patch into a new one. 2. Disabled background region. xen/arch/arm/arm64/mpu/head.S | 29 ++++++++++++++++++-- xen/arch/arm/include/asm/arm64/mpu/sysregs.h | 3 ++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 4a21bc815c..e354f4552b 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -61,6 +61,30 @@ add \xb, \xb, x20 /* x20 - Phys offset */ .endm +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch64 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + mrs x0, SCTLR_EL2 + bic x0, x0, #SCTLR_ELx_BR /* Disable Background region */ + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + orr x0, x0, #SCTLR_Axx_ELx_WXN /* Enable WXN */ + dsb sy + msr SCTLR_EL2, x0 + isb + + ret +END(enable_mpu) + /* * Maps the various sections of Xen (described in xen.lds.S) as different MPU * regions. @@ -68,10 +92,11 @@ * Inputs: * lr : Address to return to. * - * Clobbers x0 - x5 + * Clobbers x0 - x6 * */ FUNC(enable_boot_cpu_mm) + mov x6, lr /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ mrs x5, MPUIR_EL2 @@ -113,7 +138,7 @@ FUNC(enable_boot_cpu_mm) beq 5f prepare_xen_region x0, x1, x2, x3, x4, x5 -5: +5: mov lr, x6 ret fail: diff --git a/xen/arch/arm/include/asm/arm64/mpu/sysregs.h b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h index b0c31a58ec..3769d23c80 100644 --- a/xen/arch/arm/include/asm/arm64/mpu/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h @@ -15,6 +15,9 @@ /* MPU Protection Region Selection Register encode */ #define PRSELR_EL2 S3_4_C6_C2_1 +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + #endif /* __ASM_ARM_ARM64_MPU_SYSREGS_H */ /* From patchwork Thu Oct 10 14:03:51 2024 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 6/6] xen/arm: mpu: Implement a dummy enable_secondary_cpu_mm Date: Thu, 10 Oct 2024 15:03:51 +0100 Message-ID: <20241010140351.309922-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010140351.309922-1-ayan.kumar.halder@amd.com> References: <20241010140351.309922-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231B:EE_|SN7PR12MB8604:EE_ X-MS-Office365-Filtering-Correlation-Id: 1de2197c-76f0-45c4-af62-08dce934922c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: zKmaI+0PbdyecuZ5f3AIC0+rnU0Y/yVPFmN7KjOaEdJ5wX/qRhCPPHauVhCtoUe4T6goc+9nnqxmRbT8lcx8k9NztJ2gnofaima+oOj8y9YKVOdnNtRMKTFgjZcjE7usBGqqz9WS+8NbuKa1A6/9is1ZDTqUcyAQ6UjLZuF8k7v+IuwHssDA7AlfsH+fbRXqbaE6kmy0htVzMtnn/FM9QnZjGhNstZVKJqDzfDBFkducvN9pYxmQ2wjkJfoBmO73O8FRPLJs3/7pdhWHl+DdSOpPpvAsphZAt1qY+pCQUD48JO4EmjVBQXJ3cB87snROkKN6MSAQJasB5NNtEIvMU50sZw+d/XgsK0FIy81xHzlhWqOZVluXZw+FcoWQqWOC9AaEP9omR56E/0/M0Z6wq1+jdL5uJMteVy48GyguEFHCOGFTq8VIpxhIAD8KUBmxgUCq0HHRpPSkPn+mcNrEFYMhsVFvMJ6u8c3ovakqHL04zfEQMeoAEczpX8dU33DA8KOI/DTBuOeFlFV08M5kEt4ln5cXkwPAankJOcF2kCGVc44RPg/FQLkS0KfnZJdlzNFULal44y7KswgH0mq1rUTpd5abGmU0btcHDBIkL9nj7ClTMb7elG5dEIVKRTgq/gT/EP5Z9d6dQt/akztCMFTEVLsyz4DakjHgY85eg7/w3Yqh907r9MX+kmMoSi5us38JwRz54N72/9/u+nAu9g9qa2ptIFgjZsc/yth2nUkDW9ns5po8BN94kybZiTcAhNQNGtWgI+snCJA0LjxhLJ9fabfwuRdicpyuZVOa0cY+d8VtAgpShmPSCvi99dpYSwANu/x1Q1HBEvZyeYgzRC0SoCmB0SsH15SAPiVQ+p1vCasGtmqBhRPN8tqG2HqNtgmhG/h7rZ1EGnEWYlyeW/+RDsTZevvIzwZ/pq8Sgr2iuTkuHwUoInviWxOwQJccEkqRVTEpI+w2K1BVMnogw2eBtIhTGAyQ4a5gGCsQM7bI5z4L/h8MJfYVv45athMoYkgKZ8X5p3i65VlZSxppglUo8k8mDXW9YWfqiQlVqUMn+t4eZ7JM7Bwr+UTRXRFlOSFo/LDTnch+tBqoRMujCqsoFSeBeq5vW9uXvrPvAyj3WhgaWsSW+EHJnY1llOcCoVZsmV3GyzvhmRLL2O1jSLfMnuiCcwX7dDiRsy8Lyf8CQZck9XlOXt9L8cxwQiSRso0uENBpHnhNZFfSh/V6DtmwlGVvejfTmD+IpLKw07cF2/4l03P2phdM2N+k7a//Kcq9J3YexWK/PY+CrQ8nOn6tN9ZzSXq/cdrZaNI92Xj4MMFPgeWuQgauJr5+rW2pvxzfqnTxSNXWBnKvR+wkaOiR5Fl5I2jLZry5QdmlDo0RwYNQ49MbY47h5rmA++ds X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 14:05:17.8334 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1de2197c-76f0-45c4-af62-08dce934922c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8604 Secondary cpus initialization is not yet supported. Thus, we print an appropriate message and put the secondary cpus in WFE state. And we introduce to BUILD_BUG_ON to prevent users using from building Xen on multiprocessor based MPU systems. In Arm, there is no clean way to disable SMP. As of now, we wish to support MPU on UNP only. So, we have defined the default range of NR_CPUs to be 1 for MPU. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. NR_CPUS is defined as 1 for MPU 2. Added a message in enable_secondary_cpu_mm() v2 - 1. Added the range 2. Clarified in the commit message why/how we have disabled SMP. xen/arch/Kconfig | 2 ++ xen/arch/arm/arm64/mpu/head.S | 10 ++++++++++ xen/arch/arm/setup.c | 5 +++++ 3 files changed, 17 insertions(+) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 308ce129a8..6053e048fa 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -6,11 +6,13 @@ config PHYS_ADDR_T_32 config NR_CPUS int "Maximum number of CPUs" + range 1 1 if MPU range 1 16383 default "256" if X86 default "8" if ARM && RCAR3 default "4" if ARM && QEMU default "4" if ARM && MPSOC + default "1" if ARM && MPU default "128" if ARM help Controls the build-time size of various arrays and bitmaps diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index e354f4552b..4d36a8c9bc 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -147,6 +147,16 @@ fail: b 1b END(enable_boot_cpu_mm) +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 0203771164..5a0d343f5b 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -296,6 +296,11 @@ void asmlinkage __init start_xen(unsigned long fdt_paddr) int rc, i; #ifdef CONFIG_MPU + /* + * Currently, SMP is not enabled on MPU based systems. + */ + BUILD_BUG_ON(NR_CPUS > 1); + /* * Unlike MMU, MPU does not use pages for translation. However, we continue * to use PAGE_SIZE to denote 4KB. This is so that the existing memory