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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Thu, 10 Oct 2024 14:36:53 -0500 Message-ID: <20241010193705.10362-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|MW4PR12MB7432:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fb3a611-7dd1-4b7b-3f06-08dce9630115 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: WpuNFDpOawt8jRBgGNAyw7LMiERFRn5OAEyDUUF3NtPbLN/YAqIsFCEYamezSIbHzJhwEIAsf5vHv0VU7gBUrMhfKu9wuP7vRV9FFNWBhXgLFjMktAnQewVyWV0js+yWbwboX9Hnxv1PDPO+7UL0TRJV69iLiUz2aGjDgcoTWM50kWlfgaUlQXVfF3MkqTxifdAyS8RBjbtAXf83kGldmzZkKFiBTqQNfler9j2vpSCRi4Pq7ykW/mBzTvAVguPdhTceqowmFRmDPFv5CMHtBPLgWQ/iU5ysYo1dGgevbtNy9dE8zENtoC4qIH/1jRggECSqtNxoIMG1RIxtw8gsJsXF5pUdMG9nutpkHWEHz5fSE/27upxGR2CPCq5l4SrmgBxRyjcx+x549ol9cZx8cOs9M5G/0rrtEekloDiazaVkMC5JqDPJyrJgdJGh8V8JjgK+pgmKFB8A4lMdJFfAYqnVKnnFAqqHInqIylzMC4Nw8QYTRYKDvyXGn/KTr8pVeDmSGlWXbAiHSaVN6ndoBC82Oa7zwBBIjdVFJsfsrsH1xZ1YyBCZIgjSOuozSRhgL/9aaSZ+IntIrIGqGCmdsCSsDmNg+g4e7Y1ZB3+YVX3yeEOBZ5ea8BNLy9MeHDCSMMB9R7fNOFKGsRVCJGLJllBvG9adi3iute8QrPDmCNSgW/4rB24/h9icT60drxk7kySPacUI/Vn4WK38Iol0mZygIWoMB30eioDXCOR2ZUoxS6pyvwicDdqKlxwkqL13ZMzgxFDZUEdkaSBaEVRFgGCo2HxpEq1MabsazijRgixFA7BrmvQdnBG4ucDV9kxNybHoWODoPRgPtUE8acILY1dtXV0JBGamN2CEYkiGOdKNh9fq4e0noKB8bwaVSC6Gj1NVWIRXoEP7/kgFmQUx/ELL7zLYpXUaa6TMP/9GtqZQic9YyVKl4L7VKfEXxTiHaqb8gttVvij6ZvAd+xV2olfao8LRxJZYf8ple4A/TRPneFRvE6tUIAhB1xXCq/SGZ4dJsZYfjyDKblLfaIwe34ipjgI52rJgZ+Sn3M6+KaphOEkkvR+mYq04hmWcQ5ykPprL6tcB8wXCyEH+JxWFfdLivCLnjWHzf/BiAT12Ksg4UDk2JJP6a8V0oW5g7BYJyO//jWNKrBcShyF8aXQiEAOhsL1vdC3h9dsKzEdZVYpgmonRViO+uo5hcpgUf6AcUHE2pnotZSfqh6NudQk9HsxR86Lx48Z6poIPpLLo8J80Xn2mEMJa8Elicb9EkAngCkT4FLnTqhpvFCdgDtOhu5/EX3oWnUSlRHVBWTl53pOc62YOgU0XuwXKcOL8PkH5W6gGFjEWFG5EKqZOGFUJh4Vl8hgxw35A1bf43KjFMy8MyfwN3Bn1Vyf5VTk3vt4x X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:40.8190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fb3a611-7dd1-4b7b-3f06-08dce9630115 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7432 From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- Documentation/arch/x86/amd-hfi.rst | 116 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 117 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/amd-hfi.rst new file mode 100644 index 000000000000..351641ce2821 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,116 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================================== +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +====================================================================== + +:Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency +and power capabilities. Power management strategies must be designed to accommodate +the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural classes as well. +The purpose of the scheduling feedback mechanism is to provide information to +the operating system scheduler in real time such that the scheduler can direct +threads to the optimal core. + +``Classic cores`` are generally more performant and ``Dense cores`` are generally more +efficient. +The goal of AMD's heterogeneous architecture is to attain power benefit by sending +background thread to the dense cores while sending high priority threads to the classic +cores. From a performance perspective, sending background threads to dense cores can free +up power headroom and allow the classic cores to optimally service demanding threads. +Furthermore, the area optimized nature of the dense cores allows for an increasing +number of physical cores. This improved core density will have positive multithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and energy efficiency +capability data for each CPU in the system. The scheduler can use the ranking data +from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that describes +an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes represent +thread performance/power characteristics that may benefit from special scheduling behaviors. +The below table depicts an example of thread classification and a preference where a given thread +should be scheduled based on its thread class. The real time thread classification is consumed +by the operating system and is used to inform the scheduler of where the thread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+---------------------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter | ++----------+----------------+-------------------------------+---------------------+---------+ +| 0 | Default | Performant | Highest | | ++----------+----------------+-------------------------------+---------------------+---------+ +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 | ++----------+----------------+-------------------------------+---------------------+---------+ +| 2 | I/O bound | Efficient | Lowest | PMCx044 | ++----------+----------------+-------------------------------+---------------------+---------+ + + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system information +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performance +are reported in separate capabilities in the shared memory based ranking table. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or more. + +The mechanism used to trigger a table update like below events: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modify +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indication that +the hardware recommends to the operating system to not schedule any tasks on +that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated classification ID. + This classification is communicated to the OS via logical processor scope MSR. +3. During the thread context switch out the operating system consumes the workload(WL) + classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new thread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider scheduling + the thread on its ideal processor (if available). + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating the ranking +table and is ready for the operating system to consume it. CPUs receive such interrupt +and read new ranking table from shared memory which PCCT table has provided, then +``amd_hfi`` driver parse the new table to provide new consume data for scheduling decisions. + + diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 8ac64d7de4dc..7f47229f3104 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -43,3 +43,4 @@ x86-specific Documentation features elf_auxvec xstate + amd_hfi From patchwork Thu Oct 10 19:36:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830938 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2063.outbound.protection.outlook.com [40.107.101.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 711531CF2B9; Thu, 10 Oct 2024 19:37:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 10 Oct 2024 14:37:40 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 02/13] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Date: Thu, 10 Oct 2024 14:36:54 -0500 Message-ID: <20241010193705.10362-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|DS0PR12MB7605:EE_ X-MS-Office365-Filtering-Correlation-Id: 79fb3897-0cdc-4734-bbcd-08dce9630235 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: PyqoU+T+3ci+uuWXQVdL9V42YavydJ7APSqi+CFbLcDCV3wdHWl9VNx7VlIEsEFlSBNrEXp6KJQSfHwvsLI+GEYCVZV8p3hLZstInc2/8Ptjjhvtt9xJY+fP59w+LTiIp9iJFC2gFUbH/CQl7Kzfz/od2JYWX6cP/5lHvWN/K5WNhOmYvTVpsqtMuXXB40/6ieo7VIlxk9CCzSbugdKRr/Fjx7I0jrFW3tWRcfBHsh9MHeJSE2p+hIuYj3TaWaCzOU/YZO+BXrZ5Lr/kVXs5YzbL5lVo1MvvM88xkuoTT4iN9TJMZST2y3OwUkt0ZQFHRn36GOS1VnUQ0AONi96+nekwBkWrYoIfxDloyrOhkm1ABn+k94+LvydvVg/Jkj+TRsaHV3A9jKuWNOIWvOluhoIO1Ad88nIF9KWzTYLhuVynHZIcLltJgbqiO6Zg8mjzqwl5+KBYuUxnJ0H2rLj9LFqGvzts5RY1O8aQZMiqlQj6SBAvOP2atPmC+42rMOY2Q5K+oz0BZDctr/8k9Q1/wd8cr+sg0pmAsRN6qNzgOa5HSccOjiy9wfhVbpKhT35oBa8vpW5ot7VrPRyD+XaPN2R0y/vzb3+A1UyqW6z0xlWmIJBSCX/97juHqgAVf1iUjPibEsXSWQ0T72DPYb1uz8B6z4GQEEcevxvFL5pRfqLYH7sDuStEgqR+Zr6eebRUhvcF9uNhHgxr5zaYgmy6U3upTwm3rnKGb5HKKSLmGROML5yUmMdqWHVafY4FDyK0MnaF1HcmbjKs67cHZs7MOiwLplTX2rku6b2PJU0qETMuk6wt4GTxu3CDct70Mc3Q/sLRuN3igh5oE+JpJ6yXk4D9205gOCs9OcpprhwJ+B14pCELJEosRt6njWQh69AztH/koFrdjHTkluRCUZ26YrnjlNZQhSm6Ug8Ct6Hyfo47V4TKC4i4ryHcyQ0abQqUeoikv5DgVYSrVM31KDjslp9E2yyEPtCq+ENlt8LF6A0t9iwFyv2+mwKYku9R41pQKLY+9p/JFOje+JA0MWNAy3k1SZvcFTXVJPSFdYurrWlDI7UEw2g+GjvkvmrDiw/DcpBp5mjg7ZmyzwO5b2LrbTBemUD6v70jk4urK0g5MElOvlLTCh7vEzkBAO00UFtKcy7pCiL0RkNunRTGJchOXAoSh5LRkeosR9wegT8M1Rsa2BMHgxbOXN9fW6Owb5wqKa9+8wW4yzlUyMo581DiJJnfivisBzTBo1QpvZ0Dc9qUpV6oqoYLkxtDgoWTIhdCEsJ9MuNqrpAYsXjFdNDLbocbJWgDrGjN0EiV+DLhjrX+qd9pOJXC/we8HdCT2jW8 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:42.6940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79fb3897-0cdc-4734-bbcd-08dce9630235 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7605 Introduce the `amd_hfi` driver into the MAINTAINERS file. The driver will support AMD Heterogeneous Core design which provides hardware feedback to the OS scheduler. Moving forward, Mario will be responsible for the maintenance and Perry will assist on review of patches related to this driver. Signed-off-by: Mario Limonciello --- v2: * Make Perry Reviewer instead of Maintainer, he asked me to take over this series. --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a097afd76ded..90094e064d94 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1083,6 +1083,15 @@ F: arch/x86/include/asm/amd_hsmp.h F: arch/x86/include/uapi/asm/amd_hsmp.h F: drivers/platform/x86/amd/hsmp.c +AMD HETERO CORE HARDWARE FEEDBACK DRIVER +M: Mario Limonciello +R: Perry Yuan +L: platform-driver-x86@vger.kernel.org +S: Supported +B: https://gitlab.freedesktop.org/drm/amd/-/issues +F: Documentation/arch/x86/amd-hfi.rst +F: drivers/platform/x86/amd/hfi/ + AMD IOMMU (AMD-VI) M: Joerg Roedel R: Suravee Suthikulpanit From patchwork Thu Oct 10 19:36:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830942 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2077.outbound.protection.outlook.com [40.107.93.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56CB41E1330; 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Thu, 10 Oct 2024 14:37:41 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 03/13] x86/cpufeatures: add X86_FEATURE_WORKLOAD_CLASS feature bit Date: Thu, 10 Oct 2024 14:36:55 -0500 Message-ID: <20241010193705.10362-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|SN7PR12MB7855:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b330fe6-0e08-4f34-c7db-08dce96302e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: 9Jup9iaUe/+PRvznZ5mUpPO0+CxH8WTbEPvRYq+eltDhmxvm3fpTX7+Unea1ZGyVq8B+n79cgb4AJZLPWJH5DyovI8vLEKNm0Zqyp/NU+IF3qNOaRg8TK8wp2lkBlCAo3LoRYPMG1s/fZM2gdW/iM0Qcjs4MV5tzKC4+OCCevPYCGPx7cEEdg/4bQ8cEXksk0ZuEDCEmZZM/yXp6IULzAcZPLuqmG15BMs4efJpjFS4zcjhmoqSa0EG8OCo1KL4EfZBG7Miu2D44yO8Ep8aCkeTgRipeTemCkvi0xGatH423gHNWy7cxdHF0ghlFeAz+4UZkLCYmw3PQryDJNF3cSIH2Y+WC/NKd0ZJgmybsy34kv8+/w0RxM4YlqnxNo4/YfS+ncf+bA3Jz6T5h64nUb2cwugyiQlOZEnSMvp2dnOya2e51x6uiLm9VrP/9KUXNYdDDuqYfGbddVChVqBXz57hNYYC6NrWFxHx+VmbAOlw8MT3ihyv67JS307ZnidVqXyA4afVUFQY2P4P6b8kpkgXse3GDRX9S2rpQy2pTP+lp4y5fsRTC2uMaPimoc1GjYAtqtQlW+SyC3oY5sUmwiY7wSb9ixK9IMZrP/SkHdjgybON680f8qKR1F2EsfoqF0tWnXdhnM6aMvngUF3RYLhDpTBLUv84P2BH24xs0GzZLxV8I4pN4fLq7LbG4innLJOsY3K7u1YeCVhCoFoKjHVBo+0SO4z8FqbQ4Ci4z+J++QlPpDQeY/c2kT/m9pk1nlKn/VOAX/ekTsKHxI0e+M3XhFQLkDr7F6prMHypKz9yuyuQixzHoR2daFLp7Vxu8WWYA7jRKGmffcHFTPX2i9LRHfG8PYkliOtuFf0T1GoIixtpvQ4hfgEviTwnWNooXXydFkrWFwznzBBOPR6OYZPYyLZhJyCHfVlstlINhMSf84yDLrxOJ81sato2uCia+KAv44RIG1/5PXaZmKIHO5LlYBDjgm7PskytevltRJ7Sp8Ut+Gq0Klzmj20F2tt5xq6PKXR49VZ3zalmNLqmljUwgggl8drJGK0/BTpE8PsSyMku3ywUM3yruVXRcMlaqiryYcZudatwaQBkNS3Uy06fVym+fsaBU54ah+n0OhK2wpAjp0lvbPQJe2lO+7rdC0TGiNTGTOQ+1LUmS3nFWU69rd1ryfo3tUEVaItY+dWI/4wnHEnkw0dWkBgwSOVtesqmxYEesuXgwszgltVmQXU+lLAZP4mTufN/t8Ow9pVr64+LYzhjlxezO6PdJWdARBNg3hT+K1e9XVlAorYG9YqbYY4zJ73QSiDTeAS9AlKw1aHnEu5nJeIa8m7mS0n8H3OkTGjKd2xADDmDO6ZbjKlY3ONH5WD9+bwEdzX0lX0bD5Ttjom+7w1TSA/rDozDs X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:43.8502 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b330fe6-0e08-4f34-c7db-08dce96302e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7855 From: Perry Yuan Add new feature bit that indicates support for workload based heuristic feedback to OS for scheduling decisions. When the bit set, threads are classified during runtime into enumerated classes. The classes represent thread performance/power characteristics that may benefit from special scheduling behaviors. Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cea1ed82aeb4..3e8e67b8ec7a 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -474,6 +474,7 @@ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ #define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ #define X86_FEATURE_HETERO_CORE_TOPOLOGY (21*32 + 6) /* Heterogeneous Core Topology */ +#define X86_FEATURE_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 3bba55323163..b6547bab9e23 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, From patchwork Thu Oct 10 19:36:56 2024 Content-Type: text/plain; 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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 04/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Thu, 10 Oct 2024 14:36:56 -0500 Message-ID: <20241010193705.10362-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|DS0PR12MB8575:EE_ X-MS-Office365-Filtering-Correlation-Id: bf383d90-b864-4072-0019-08dce963031d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: Wtk8Ky5QJjT4UxI1/tlsOx/nKy5qgAU4v3EL4BG0+dDYiF3XQkSnPlM19vEyj4SxEGJXbqA4FpYYUXGo7FPM1V2gnggeyAvu+yHQfy6L1skmi1G0PvjAyKn5ArCc5rr9oLS1fkC9bT5MKZBwsrokuCpatjnSi7VqLyAbK2R/uDPO3v9NSUl8rNSgcUY9z7Orb8yLEQvMkGlCZUCGrVHHiXtX4yXBTeDq1t8NYYDm6pqGBWufb4obEUHLwiR62jHZo9MvBfLpP09FptPTq263tE4trpSvEbwtEzEowDONh2EW13F3anSnzFbbw0tc+0hK22nstIltL/NSKPsuug5lT3kDcGY2wGhmV+wCQfZnLBeFg2kMDgso2YGD4AfEuZX7LqHwmjAUNDUS+pgeOZXPQ0jxhYMvxBMq+fjOqO4vVGiKuz0sCn8BpfdtrOXqTB1/nb/AXCsuohsqWBEGLBhxbcrX3Mz9md0MnOn/pE1JcOcLkHYry5zK1D7X+rSdX9JE3UOB8jS6xAQ8DV3ARvj0YdfDIvWZNNEflI6fK+krTPASjFv1D+TS8A3GBMUVs3jvOP0hOA9laM6doFtsC7zf1L6L8+GnyUHXW+Zs+3LdEYZjwxan9CJzpxdBZRXjUBoQTEkCC1wr4hmr2EIZG90SG+1wl/vMfCc5kTxg3Gr/ghSSnKU3NLTb/VqcEiLR9EcTxen+nvmj2evFXUsdwObQj8rvFjRwy9I2CF0uPdv+T9pzv+yf6xYTDNhFE7YuAzorvFXsJwAiRicf9UtE/YwKwUMnZWMd1pW6gNM4xIfgEXa3uLR/4kKAybB6KyQ/XeJDqvQ0oCJ03rHCvoH90Gg2de5gkYYrSrQ/iSl9+Yot0iw69WxogSNO6CGTmH1mk/vzmvSg/nmnyxocFzbKkdIbzXw0SdoXWoIK9gK25hrBf5jiHiNDfV1blw3jziAglKDUE8pQcqGq3XNjTh3G4wlwEeoVcqnuFPXH4GLW96qdBdS1vNWJfZ7E5PaQrMqaO9yfjL1g0/xb8MlpE0NM7WfmNnpaNjLWq4lW0+JdhK1F8h0+SYSaAh59e0wkBVxAOuh8Sce+DUcfRTGlUqeYD2h0ZlPrHp+JLY5PMpEfd2ArSxtmctEVr2xOFgI2rKmYMRU+W1wJ/QQobKRkZW30oisZ0EBB7Lpqkr5u6VQFsPXzl5WSP7OX9tsFA2duTV3pPUwKVHNyxfO3myQl136nUVNbowWFPbhDh6JLv6KaoP+pBG+cpBnA8HOLKiG+qqWA20aB9g2UIqIWGTW4rdmgmVMd8GnZSvzSM5XEqZkjMQ2yKifaCE21M+fDBpJfsBfMnLR6Dw5dy6cho0XQU7IF/Ahjegs1WTllNG2yysxUZOQy9CqHUaG1773B64nn6NBOn0t4 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:44.2252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf383d90-b864-4072-0019-08dce963031d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8575 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..0cd5ffe50f4a 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -712,6 +712,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e From patchwork Thu Oct 10 19:36:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830940 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2068.outbound.protection.outlook.com [40.107.243.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D1221CF5C5; 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Thu, 10 Oct 2024 14:37:43 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 05/13] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Date: Thu, 10 Oct 2024 14:36:57 -0500 Message-ID: <20241010193705.10362-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|MN2PR12MB4359:EE_ X-MS-Office365-Filtering-Correlation-Id: 20e8579c-eec8-45ef-6e48-08dce96303cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: IqVBRPWC+6p75ZRovi3I7gpbbF6B6TWVmGTay70dB40lHP99usghIYxD1yu4wqB/V8Ejuw6sD5jFqykwHAnToHQF1FwGKTnn4c+jQFe/RyxVVRYp2WXOb5H13gKzKuS8PgpjlfMRPq8qC6GDLJz7imPw91QTHlbEVdhEhdAUQFjHhZu5Aclk/4V+GA54v6yICO9dYoKyLAWRrc0baKZbuHkVTHmI3zjbF8ouooQrfYAESYfh5+uHjvhFQDeOe9p9YHb2bQ45ohQtLit56fkUSY75sK45csE/Xnt+m6F4wO12uq4Csa65CP1WXOj5XhaWhWllWQY7VItZ8B4b2i0CqEXbH9Uq89FBIm0ct7bPF0yfkWB2JMvCMaFj9AAphc6K57dcgwia96D3Ei6Kg9Qukwc+EPguryh+vFuKnNBqObFWtODAVF8VuH+MlVCFW1TzgIgSz0IueAY+eWmjWFdBoAZvVg1c4eJ2y+0pSm6rxm1MW6XM4pmWon/36QN4oKL+eQRW0zGGL6XwdK31tXoFoZw11ERpwK8nocR6y0n2xJEWnSw/vsNF8m63XgfoSJw2IvYOor0oNiBXTtsPv/BgZzNhNDRu4kS4fk+pM7yrcFp2dsVojCFoVcLpmBvSS63L2QkIxTRvQYBBmKDCFunbT2jPGZ0DBP5vz+Eho/53Tez/I0c89EaHFbQQyn3Qwog0HDLdzuEk5sLN4HNv6udU/gOjhix6XZvwGBZR4wducxCVIpKAjKhRf6Lyp47e5FTptdT+0sj6cqxoIKj9PUNjG2QgWPwtm4zd0g55C9lRbHeLGQdidD2qr72PWzZBqtzyGDYXrbtT8tziURSpL7Nofa8f31pniUYh68gtjUxPLcH7fJO8hX6L6Ugfq76f+pfXab8z0R0SmVLO35V0wLDOWOEn/8M6mrqz+Nf1i2E3rYSVPnJIJVKdSvMZou1UmdRocKe4IpSgna3ojc6VdOth0ynFv1ijcFEPkFRQrojsK+/wlkW7YnjL12zXJ773ebkF2I6MsYjhCOMznpt4lkR2vC2nOiKUjN1HlSnCNbTSRA3GQ2yXLEsDdV3t8eo55KZ7dAWfxNTxC4wHnB3s62kQWN/hFkrLnPPVlrGIpTSK0kSp3Lp2VSlpWfrJUrnW+n7SmTnYVYwzsywz1trL85SZ/OnJBcUJOg99ppjZ0+cnu1CdCCs21Rc0+nhvKwysrUf7SvbwPH8mr1y5KDGQTtFCyLwiJW1axQlQhk/prAlrH0+MPW0hjsyT9V1EPNhZtrUJEiFBcbNGmyP1wjYGCmrxPIO+5A/byYEdFgZ3OSP7XtY3v8OvfRNPN5UC/jOwqKoZ9ag1JNG8mTmzqHzmeCDp3o/U4LT8dCFu4pLCmHj0rREbLB3VzCd9XcfBZUgl4g6U X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:45.3815 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20e8579c-eec8-45ef-6e48-08dce96303cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4359 From: Perry Yuan The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks. There are two CPU core types defined: `Classic Core` and `Dense Core`. "Classic" cores are the standard performance cores, while "Dense" cores are optimized for area and efficiency. Heterogeneous compute refers to CPU implementations that are comprised of more than one architectural class, each with two capabilities. This means each CPU reports two separate capabilities: "perf" and "eff". Each capability lists all core ranking numbers between 0 and 255, where a higher number represents a higher capability. Heterogeneous systems can also extend to more than two architectural classes. The purpose of the scheduling feedback mechanism is to provide information to the operating system scheduler in real time, allowing the scheduler to direct threads to the optimal core during task scheduling. All core ranking data are provided by the BIOS via a shared memory ranking table, which the driver reads and uses to update core capabilities to the scheduler. When the hardware updates the table, it generates a platform interrupt to notify the OS to read the new ranking table. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Drop unnecessary select * Make tristate instead of bool * Drop error messages * Drop unnecessary function declarations for init * Fix cleanup for amd_hfi_exit() * Drop unnecessary variables for upcoming features --- drivers/platform/x86/amd/Kconfig | 1 + drivers/platform/x86/amd/Makefile | 1 + drivers/platform/x86/amd/hfi/Kconfig | 20 +++ drivers/platform/x86/amd/hfi/Makefile | 7 ++ drivers/platform/x86/amd/hfi/hfi.c | 169 ++++++++++++++++++++++++++ 5 files changed, 198 insertions(+) create mode 100644 drivers/platform/x86/amd/hfi/Kconfig create mode 100644 drivers/platform/x86/amd/hfi/Makefile create mode 100644 drivers/platform/x86/amd/hfi/hfi.c diff --git a/drivers/platform/x86/amd/Kconfig b/drivers/platform/x86/amd/Kconfig index f88682d36447..c3f69dbe3037 100644 --- a/drivers/platform/x86/amd/Kconfig +++ b/drivers/platform/x86/amd/Kconfig @@ -5,6 +5,7 @@ source "drivers/platform/x86/amd/pmf/Kconfig" source "drivers/platform/x86/amd/pmc/Kconfig" +source "drivers/platform/x86/amd/hfi/Kconfig" config AMD_HSMP tristate "AMD HSMP Driver" diff --git a/drivers/platform/x86/amd/Makefile b/drivers/platform/x86/amd/Makefile index dcec0a46f8af..2676fc81fee5 100644 --- a/drivers/platform/x86/amd/Makefile +++ b/drivers/platform/x86/amd/Makefile @@ -9,3 +9,4 @@ amd_hsmp-y := hsmp.o obj-$(CONFIG_AMD_HSMP) += amd_hsmp.o obj-$(CONFIG_AMD_PMF) += pmf/ obj-$(CONFIG_AMD_WBRF) += wbrf.o +obj-$(CONFIG_AMD_HFI) += hfi/ diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig new file mode 100644 index 000000000000..08051cd4f74d --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# AMD Hardware Feedback Interface Driver +# + +config AMD_HFI + bool "AMD Hetero Core Hardware Feedback Driver" + depends on ACPI + depends on CPU_SUP_AMD + help + Select this option to enable the AMD Heterogeneous Core Hardware Feedback Interface. If + selected, hardware provides runtime thread classification guidance to the operating system + on the performance and energy efficiency capabilities of each heterogeneous CPU core. + These capabilities may vary due to the inherent differences in the core types and can + also change as a result of variations in the operating conditions of the system such + as power and thermal limits. If selected, the kernel relays updates in heterogeneous + CPUs' capabilities to userspace, allowing for more optimal task scheduling and + resource allocation, leveraging the diverse set of cores available. + + diff --git a/drivers/platform/x86/amd/hfi/Makefile b/drivers/platform/x86/amd/hfi/Makefile new file mode 100644 index 000000000000..672c6ac106e9 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# AMD Hardware Feedback Interface Driver +# + +obj-$(CONFIG_AMD_HFI) += amd_hfi.o +amd_hfi-objs := hfi.o diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c new file mode 100644 index 000000000000..da2e667107e8 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Hardware Feedback Interface Driver + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Author: Perry Yuan + * + */ + +#define pr_fmt(fmt) "amd-hfi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_HFI_DRIVER "amd_hfi" +#define AMD_HETERO_CPUID_27 0x80000027 +static struct platform_device *device; + +struct amd_hfi_data { + const char *name; + struct device *dev; + struct mutex lock; +}; + +struct amd_hfi_classes { + u32 perf; + u32 eff; +} __packed; + +/** + * struct amd_hfi_cpuinfo - HFI workload class info per CPU + * @cpu: cpu index + * @cpus: mask of cpus associated with amd_hfi_cpuinfo + * @class_index: workload class ID index + * @nr_class: max number of workload class supported + * @amd_hfi_classes: current cpu workload class ranking data + * + * Parameters of a logical processor linked with hardware feedback class + */ +struct amd_hfi_cpuinfo { + int cpu; + cpumask_var_t cpus; + s16 class_index; + u8 nr_class; + struct amd_hfi_classes *amd_hfi_classes; +}; + +static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; + +static int amd_hfi_alloc_class_data(struct platform_device *pdev) +{ + struct amd_hfi_cpuinfo *hfi_cpuinfo; + struct device *dev = &pdev->dev; + int idx; + int nr_class_id; + + nr_class_id = cpuid_eax(AMD_HETERO_CPUID_27); + if (nr_class_id < 0 || nr_class_id > 255) { + dev_warn(dev, "failed to get supported class number from CPUID %d\n", + AMD_HETERO_CPUID_27); + return -EINVAL; + } + + for_each_possible_cpu(idx) { + hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); + hfi_cpuinfo->amd_hfi_classes = devm_kmalloc(dev, nr_class_id * + sizeof(struct amd_hfi_classes), GFP_KERNEL); + if (!hfi_cpuinfo->amd_hfi_classes) + return -ENOMEM; + + hfi_cpuinfo->nr_class = nr_class_id; + } + + return 0; +} + +static void amd_hfi_remove(struct platform_device *pdev) +{ + struct amd_hfi_data *dev = platform_get_drvdata(pdev); + + mutex_destroy(&dev->lock); +} + +static const struct acpi_device_id amd_hfi_platform_match[] = { + { "AMDI0104", 0}, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_hfi_platform_match); + +static int amd_hfi_probe(struct platform_device *pdev) +{ + struct amd_hfi_data *amd_hfi_data; + int ret; + + if (!acpi_match_device(amd_hfi_platform_match, &pdev->dev)) + return -ENODEV; + + amd_hfi_data = devm_kzalloc(&pdev->dev, sizeof(*amd_hfi_data), GFP_KERNEL); + if (!amd_hfi_data) + return -ENOMEM; + + amd_hfi_data->dev = &pdev->dev; + + mutex_init(&amd_hfi_data->lock); + platform_set_drvdata(pdev, amd_hfi_data); + + /* alloc data array for hardware feedback class data */ + ret = amd_hfi_alloc_class_data(pdev); + if (ret) + goto out; + +out: + return ret; +} + +static struct platform_driver amd_hfi_driver = { + .driver = { + .name = AMD_HFI_DRIVER, + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), + }, + .probe = amd_hfi_probe, + .remove_new = amd_hfi_remove, +}; + +static int __init amd_hfi_init(void) +{ + int ret; + + if (acpi_disabled || + !boot_cpu_has(X86_FEATURE_HETERO_CORE_TOPOLOGY) || + !boot_cpu_has(X86_FEATURE_WORKLOAD_CLASS)) + return -ENODEV; + + device = platform_device_register_simple(AMD_HFI_DRIVER, -1, NULL, 0); + if (IS_ERR(device)) { + pr_err("unable to register hfi platform device\n"); + return PTR_ERR(device); + } + + ret = platform_driver_register(&amd_hfi_driver); + if (ret) + pr_err("Failed to register hfi driver\n"); + + return ret; +} + +static __exit void amd_hfi_exit(void) +{ + platform_device_unregister(device); + platform_driver_unregister(&amd_hfi_driver); +} +module_init(amd_hfi_init); +module_exit(amd_hfi_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Hardware Feedback Interface Driver"); From patchwork Thu Oct 10 19:36:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830943 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2042.outbound.protection.outlook.com [40.107.243.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02CF41E0099; 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Thu, 10 Oct 2024 14:37:44 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 06/13] platform/x86: hfi: parse CPU core ranking data from shared memory Date: Thu, 10 Oct 2024 14:36:58 -0500 Message-ID: <20241010193705.10362-7-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|SN7PR12MB6981:EE_ X-MS-Office365-Filtering-Correlation-Id: 9403b82c-42ac-440d-b9cc-08dce9630419 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: 6AgQl95KQsV45adRzqW1SjCuxiCqtWqbXjcMss668O3ZXoUchiFhZr+gIrTTh0s9OdFUuhmEgo1pFB1vWymWruLdHdbt3WjupPBTz3D1lq6LAamxbzwjseblKiRi7+Us2KiC5fm6UlX7K1mQg/OoyZzLp0zCm7ANXWxDzh9pCab4xo2LI20e/rrwkO1jYDmF8gfKDCG0+bv/4amjm7yK03PwRbQvXh/21rDk+uqUiUYkvnGxNG/+5iAKIfLdTOrhyV9HgjeVvWY6CdoYEK2TnZbLh3WWAMvUDeLkOpJfiVZ1FVjOxfqm6FkdfqLA+aUbfV5SDZrXsgdnToN/Y2lvqnfAJP88cEuePEnrEOXDz1TS35xsGMluQhvhUFQnPKUP2OmJS4Mi6klKKMFGjNb9UC4te99mPe3uR2T37KPVDXi+da96ijZ8iGtqtnmISV1ZhP3ptHE1/vdcRHl7yhUECVzXd7L3y/l3rh+cZTOZMpAa3Iwp99ytrKDYPIy+kGzSAq6XYZ9Kjhwrl+2G2bqWiXgcHZbw6VZoa1G0Tp+7w561uXsMjnvly3zJ7p7D0/a3eHUENjUqUIyQOxQ8jj88wxYep4kNKYbBjxn1YZkHTSLluym+cflnTVAZ/WVXoLD8F29mZzjY6rSsE59AjIBPyCMdmTfSIaJOLcCSofdhX9qNfhLhZQj6Jlza0hm7puhNi17PKh5ueoOdPY9yz8A3qFR933pg1roW4b4qptCxQ2Ip+1y9S9gyq7Y6SZ2MWImLlFCj55u3B6gE0XTOjdBuPp9YXAmknMGWf8t9S2He5DnEHJpbFJvp8lQqO80Aw/z0B+dy3zm8AFOTEjuQvB6GAZHpO3rZ0W1f2fg0dllITCG5gHDPxsj1ZqFYtZFw9wtDqqkjntATTj8OU7OuOQCAbIfirl7sPCohmHf7IrqCZG22xAWylklIJkTgEw1t6D0PmmyWSEmieCCzhpgBhfIqQckuNwAEvo+NxAVIb0DaZn8ezTMTDF1hHpnHMVwawOgKnXcCjF3GdCEDrU5J8hyPmflJntQQXAUSQvzbF3p9NFHC4avkNMEqHyVbmPxy8mlNw7dikqupsyyyyJiChy7Xm8e41DCFAWfxh0OfswwdsO+jt0YzfUdFsuEswK8uvkSjMXX6EK2MPpMtOhF3eG/mAPKutAVGBQoPvSQjPq5JuDFQ89YFitcBFrGQvJtzbOktFrobRkjEeN4dPzi3FjXDIUxGLzU9g6JKmWBBCul2LQ7u5alktvLQEtcQ/ONgQg5V5wAjEgdXigzKTflClhOYXo5SnoGFqCOLU7VF8xXNXn9AqAE0OEYbjfXW4o6sEBLHvRDbyQDThdNKzIEDfCcnXOIWgtUdBaYQ3z7iWMcz9gq7ZRyeBX/dqYm/bbhMyoH3 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:45.8659 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9403b82c-42ac-440d-b9cc-08dce9630419 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6981 From: Perry Yuan When `amd_hfi` driver is loaded, it will use PCCT subspace type 4 table to retrieve the shared memory address which contains the CPU core ranking table. This table includes a header that specifies the number of ranking data entries to be parsed and rank each CPU core with the Performance and Energy Efficiency capability as implemented by the CPU power management firmware. Once the table has been parsed, each CPU is assigned a ranking score within its class. Subsequently, when the scheduler selects cores, it chooses from the ranking list based on the assigned scores in each class, thereby ensuring the optimal selection of CPU cores according to their predefined classifications and priorities. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Rework amd_hfi_fill_metatadata to directly use structure instead of pointer math. --- drivers/platform/x86/amd/hfi/hfi.c | 215 ++++++++++++++++++++++++++++- 1 file changed, 212 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index da2e667107e8..10651399cf75 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -18,22 +18,78 @@ #include #include #include +#include #include +#include #include #include #include #include +#include +#include + +#include + +#include +#include #define AMD_HFI_DRIVER "amd_hfi" +#define AMD_HFI_MAILBOX_COUNT 1 +#define AMD_HETERO_RANKING_TABLE_VER 2 + #define AMD_HETERO_CPUID_27 0x80000027 + static struct platform_device *device; +/** + * struct amd_shmem_info - Shared memory table for AMD HFI + * + * @signature: The PCC signature. The signature of a subspace is computed by + * a bitwise of the value 0x50434300 with the subspace ID. + * @flags: Notify on completion + * @length: Length of payload being transmitted including command field + * @command: Command being sent over the subspace + * @version_number: Version number of the table + * @n_logical_processors: Number of logical processors + * @n_capabilities: Number of ranking dimensions (performance, efficiency, etc) + * @table_update_context: Command being sent over the subspace + * @n_bitmaps: Number of 32-bit bitmaps to enumerate all the APIC IDs + * This is based on the maximum APIC ID enumerated in the system + * @reserved: 24 bit spare + * @table_data: Bit Map(s) of enabled logical processors + * Followed by the ranking data for each logical processor + */ +struct amd_shmem_info { + struct acpi_pcct_ext_pcc_shared_memory header; + u32 version_number :8, + n_logical_processors :8, + n_capabilities :8, + table_update_context :8; + u32 n_bitmaps :8, + reserved :24; + u32 table_data[]; +} __packed; + struct amd_hfi_data { const char *name; struct device *dev; struct mutex lock; + + /* PCCT table related*/ + struct pcc_mbox_chan *pcc_chan; + void __iomem *pcc_comm_addr; + struct acpi_subtable_header *pcct_entry; + struct amd_shmem_info *shmem; }; +/** + * struct amd_hfi_classes - HFI class capabilities per CPU + * @perf: Performance capability + * @eff: Power efficiency capability + * + * Capabilities of a logical processor in the ranking table. These capabilities + * are unitless and specific to each HFI class. + */ struct amd_hfi_classes { u32 perf; u32 eff; @@ -42,23 +98,105 @@ struct amd_hfi_classes { /** * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index + * @apic_id: apic id of the current cpu * @cpus: mask of cpus associated with amd_hfi_cpuinfo * @class_index: workload class ID index * @nr_class: max number of workload class supported + * @ipcc_scores: ipcc scores for each class * @amd_hfi_classes: current cpu workload class ranking data * * Parameters of a logical processor linked with hardware feedback class */ struct amd_hfi_cpuinfo { int cpu; + u32 apic_id; cpumask_var_t cpus; s16 class_index; u8 nr_class; + int *ipcc_scores; struct amd_hfi_classes *amd_hfi_classes; }; static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static int find_cpu_index_by_apicid(unsigned int target_apicid) +{ + int cpu_index; + + for_each_possible_cpu(cpu_index) { + struct cpuinfo_x86 *info = &cpu_data(cpu_index); + + if (info->topo.apicid == target_apicid) { + pr_debug("match APIC id %d for CPU index: %d", + info->topo.apicid, cpu_index); + return cpu_index; + } + } + + return -ENODEV; +} + +static int amd_hfi_fill_metadata(struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext = + (struct acpi_pcct_ext_pcc_slave *)amd_hfi_data->pcct_entry; + void __iomem *pcc_comm_addr; + + pcc_comm_addr = acpi_os_ioremap(amd_hfi_data->pcc_chan->shmem_base_addr, + amd_hfi_data->pcc_chan->shmem_size); + if (!pcc_comm_addr) { + pr_err("failed to ioremap PCC common region mem\n"); + return -ENOMEM; + } + + memcpy_fromio(amd_hfi_data->shmem, pcc_comm_addr, pcct_ext->length); + iounmap(pcc_comm_addr); + + if (amd_hfi_data->shmem->header.signature != PCC_SIGNATURE) { + pr_err("Invalid signature in shared memory\n"); + return -EINVAL; + } + if (amd_hfi_data->shmem->version_number != AMD_HETERO_RANKING_TABLE_VER) { + pr_err("Invalid veresion %d\n", amd_hfi_data->shmem->version_number); + return -EINVAL; + } + + for (u32 i = 0; i < amd_hfi_data->shmem->n_bitmaps; i++) { + u32 bitmap = amd_hfi_data->shmem->table_data[i]; + + for (u32 j = 0; j < BITS_PER_TYPE(u32); j++) { + struct amd_hfi_cpuinfo *info; + int apic_id = i * BITS_PER_TYPE(u32) + j; + int cpu_index; + + if (!(bitmap & BIT(j))) + continue; + + cpu_index = find_cpu_index_by_apicid(apic_id); + if (cpu_index < 0) { + pr_warn("APIC ID %d not found\n", apic_id); + continue; + } + + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + info->apic_id = apic_id; + + /* Fill the ranking data for each logical processor */ + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + for (int k = 0; k < info->nr_class; k++) { + u32 *table = amd_hfi_data->shmem->table_data + + amd_hfi_data->shmem->n_bitmaps + + i * info->nr_class; + + info->amd_hfi_classes[k].eff = table[apic_id + 2 * k]; + info->amd_hfi_classes[k].perf = table[apic_id + 2 * k + 1]; + } + } + } + + return 0; +} + static int amd_hfi_alloc_class_data(struct platform_device *pdev) { struct amd_hfi_cpuinfo *hfi_cpuinfo; @@ -68,8 +206,7 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) nr_class_id = cpuid_eax(AMD_HETERO_CPUID_27); if (nr_class_id < 0 || nr_class_id > 255) { - dev_warn(dev, "failed to get supported class number from CPUID %d\n", - AMD_HETERO_CPUID_27); + dev_warn(dev, "failed to get number of supported classes\n"); return -EINVAL; } @@ -79,7 +216,10 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) sizeof(struct amd_hfi_classes), GFP_KERNEL); if (!hfi_cpuinfo->amd_hfi_classes) return -ENOMEM; - + hfi_cpuinfo->ipcc_scores = devm_kcalloc(dev, nr_class_id, + sizeof(int), GFP_KERNEL); + if (!hfi_cpuinfo->ipcc_scores) + return -ENOMEM; hfi_cpuinfo->nr_class = nr_class_id; } @@ -93,6 +233,70 @@ static void amd_hfi_remove(struct platform_device *pdev) mutex_destroy(&dev->lock); } +static int amd_hfi_metadata_parser(struct platform_device *pdev, + struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext; + struct acpi_subtable_header *pcct_entry; + struct mbox_chan *pcc_mbox_channels; + struct acpi_table_header *pcct_tbl; + struct pcc_mbox_chan *pcc_chan; + acpi_status status; + int ret; + + pcc_mbox_channels = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_mbox_channels), GFP_KERNEL); + if (!pcc_mbox_channels) { + ret = -ENOMEM; + goto out; + } + + pcc_chan = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_chan), GFP_KERNEL); + if (!pcc_chan) { + ret = -ENOMEM; + goto out; + } + + status = acpi_get_table(ACPI_SIG_PCCT, 0, &pcct_tbl); + if (ACPI_FAILURE(status) || !pcct_tbl) { + ret = -ENODEV; + goto out; + } + + /* get pointer to the first PCC subspace entry */ + pcct_entry = (struct acpi_subtable_header *) ( + (unsigned long)pcct_tbl + sizeof(struct acpi_table_pcct)); + + pcc_chan->mchan = &pcc_mbox_channels[0]; + + amd_hfi_data->pcc_chan = pcc_chan; + amd_hfi_data->pcct_entry = pcct_entry; + pcct_ext = (struct acpi_pcct_ext_pcc_slave *)pcct_entry; + + if (pcct_ext->length <= 0) { + ret = -EINVAL; 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Thu, 10 Oct 2024 14:37:45 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 07/13] platform/x86: hfi: init per-cpu scores for each class Date: Thu, 10 Oct 2024 14:36:59 -0500 Message-ID: <20241010193705.10362-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CB:EE_|MW6PR12MB8950:EE_ X-MS-Office365-Filtering-Correlation-Id: dd2b95ba-8501-4405-825b-08dce96304dd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: VuHKUbOqUXK/SY1GAN47n3CoyxEyIDQGYnjIeGlqfI2DAllETF1Sm/JQ9RkXkyeFZLBo5wiG8kA5h8Ks27aohp6ppe/wzfirCy2XQ9Dpm2sxp+VH50+sSULowSpylKcnXEa3zFyVoAuZ16QsFwWAHJADGV8I51avUbO+aWGeqet92C2r6Zh44uTlPomrMUz6uZT1ubeZXPxU9Q3xt11KGdN7rcmOyKuvNkZkGSb81m1lIIAVDeD7YF5ZmD+mejg3LlS0IPPW9x45Js1AFmoVUAxGfHF0mHYh2Jpu1xwxUEzh6TbLtN1FfWfoiTM/SXM/KbSBspOsJvD41v6XYfKt3DgTHtSbCuzwQPdWmYDNVrYyCYzaVCgZMNOkylTlVSH8UPuWNrRYjF0z8glTC7bNMr+xW9CaeRNhfk33BpusWlSl03B7Hs/zn/AFtkkRNhhoDBc2IqfR0RlMmv03sPuW3xgrfnrxg4fQU5RKR2qKfa+i92h4gJh+j+f00CMLuXI7ME2gz2dY9wVQTNDsdTAWiua3wKXp7EJGDK6r0G0HN5n3rGGjtCjtnFABYWkKK1gHjgyyyaDnKyBAx2hetLsKhrP5gZlzpnMrZ/kFuz5qIbRe+WizFlyztyUy7YO58aX1KZgjHNJGrrNHSe8o1TgP3qxetaXSvxmP9NYk5oEO9w7ZtPr40sDwJELf8IqB4v4w2Mee/7iAs2/NJPnltwcsq02KU1gxZKEqIFWRogjV3Z28jC4SaIxhZUUr8eDcurHgG8eIF09HCX0qd/zpvf3nOvDOR+O5XM7+7Bzqvxd/CNTJXVDRV05kKRwn79cjvFO412MuycCutuICOMN7/30wYTBA73g/i4E17jnBucjiOELZ8PXWRC+LjkearrncrNOzq6ePCIEgKjCqD5i+ZixnnnDHfy4QOLcCgaWOAA7ca7DNjJ1YME9yaSG44LtPgzrZ60T1d3MBQ9iKWbOXV5Bo+dIVNU4qN3Tdx+LDqhCeWG7D52m0PNAoFVYXdp6HcsWZnay0c1ToosuEK7HBD3W5q1jB410wH6BB2guHJqENT/VAvr3dE7HvvuJpfj1ce0ehl02Ow7VJx7JUJg8gcbyvIEhGjFnGI/7fAL1HS9CLwnof7q6hbArufuzX98wjQNw7kNF46V3qd+YkccMxrsGV3fOPLiGhrQl7baMjZ+LFiyIs5mB+0JMAz0Ep0oRZk6y87jywnKHqvej24J7qs9q+woPGGedgDfphI4MIrs/gIYFjHtog8bMzNagn1Go1aHE/jiKs1hbgaartMbSovJ+vclO/WpFLlZsPEMv/NfaRiZOOTmjT4IOHYUuC1l/JiM4Q8Po/Y2TxZ2ozP+aYWQoWQVqqb0LovMWRdneRepS65+prI4EEmIGULV56QcMp48/5 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:47.1646 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd2b95ba-8501-4405-825b-08dce96304dd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8950 From: Perry Yuan Initialize per cpu score `amd_hfi_ipcc_scores` which store energy score and performance score data for each class. `Classic core` and `Dense core` are ranked according to those values as energy efficiency capability or performance capability. OS scheduler will pick cores from the ranking list on each class ID for the thread which provide the class id got from hardware feedback interface. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Rework --- drivers/platform/x86/amd/hfi/hfi.c | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 10651399cf75..c0065ba0ed18 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -119,6 +119,8 @@ struct amd_hfi_cpuinfo { static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static DEFINE_MUTEX(hfi_cpuinfo_lock); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -233,6 +235,31 @@ static void amd_hfi_remove(struct platform_device *pdev) mutex_destroy(&dev->lock); } +static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) +{ + for (int i = 0; i < hfi_cpuinfo->nr_class; i++) + WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], + hfi_cpuinfo->amd_hfi_classes[i].perf); + + return 0; +} + +static int update_hfi_ipcc_scores(struct amd_hfi_data *amd_hfi_data) +{ + int cpu; + int ret; + + for_each_online_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + ret = amd_set_hfi_ipcc_score(hfi_cpuinfo, cpu); + if (ret) + return ret; + } + + return 0; +} + static int amd_hfi_metadata_parser(struct platform_device *pdev, struct amd_hfi_data *amd_hfi_data) { @@ -330,6 +357,11 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) goto out; + /* set up IPCC scores */ + ret = update_hfi_ipcc_scores(amd_hfi_data); + if (ret) + goto out; + out: return ret; } From patchwork Thu Oct 10 19:37:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830941 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2051.outbound.protection.outlook.com [40.107.94.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 187C71E0495; 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Thu, 10 Oct 2024 14:37:46 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 08/13] platform/x86: hfi: add online and offline callback support Date: Thu, 10 Oct 2024 14:37:00 -0500 Message-ID: <20241010193705.10362-9-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CB:EE_|MN2PR12MB4272:EE_ X-MS-Office365-Filtering-Correlation-Id: 2dae8d60-6f36-4cc7-a37f-08dce9630560 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: 6D7fzATWtxiDcc68EosNcuKRoXBNrWwbusJQU2MXjpBxFqGSK5y5lLamzubt8wqnWlGY/9/L5WQXlKPGPOYPYCrcFTmmeC+ufD8qPpCenJFSnZiZ5H7FzN41IC5Dsc8a/R/24CuJSNAmsd7/wveujsrLnRYKMbaCJHcqcvcIh/8yox1erCQuNHo3iT3Ly7RgDnkFtdfDKtN1Fx1hVeDO74kjB9e7QYxffDPTVO84thQP475yHiORpDBZFhNi7ajxZ0ZbLKsKIyX/aB/dm8k67Abz99KPpvgo2rHywtG1Qho6Aj3jGvMUaMYJMmSulhRo4AkqQOZ3C0ZHxuDylo9gtpYtXX3TVjCDoj4EmBGySQTZOFqSjTqjpe8961QmzF8THZo3V1fGUeBBsGr3lUGmiHQhZXLRjVsURzQpRZOEOojnLauOtAyf1MsvMBMeq1dowHNV9h+FqopEtRdFr3rGcLt6AlQk6ua9LO1DkS2gP3v4+SLIzG2xUu3MHVXEUcGZLXLB4vRwO+OsRy3iUTjBh+yNg9ukQ6neKKzA9ENlbPx/q2YRGqeqHzqSFvVr5iXa28aPLkp3WC07DwCKJKVM1hQesMhLDrckeHT+KoIRUNKs6qfL+ORwXGfLhYsEF9Yxwk0X/eeg1qhaudqW07Z8VcNddx/CHsf+ZH57w8rhgoVNbFeL2ck2W7E1vnwNVxscQAWx2yNAfhzFSbsN8tgNt1xW7h++18s5cmY3sDzrf30hYUSA++xZ3ljTGKkl0fV47R8B/rmPHTztBNF3TLK4JSNv3+DUK4p8sATkAdk4UxealYRiyvgfSb3Wym97vJaM1Zd6GYP+xKQKCvznsc2GifUuTQL87oFviaFln44TgEo56sc0rzKtWsXi5DYFGJXpJgIW8UxLfy2VT8gLuIzD+/eG0fG5DSQmaVW9pEb1cVIv+c9Gn7Bu2ihjYF/mOAC8lCIWuqoMFG+F4dbcjKE9sLE9gX2u/rUl8/TDvDnxTSsObg5Nrce3GNr5UY9nZ0sMPmHUEE0paqTUuSKOOCLKrLEUbGjM9Jr1J+azivkT+7O7hhyStYBQRJMhyqPgBxabkDFG+RofCj8i4DyZ8w88UaUUdjH345pO6J9DnbdTZHGJl5N4pqB6IxYYmPjbCCpKscMjWudHcCSvtVDLxmhqKfdQnjOx9zsreoDIG0RM6oKkWx6lLa9w5bEZfVSHJKIJljm0HRP7m9CG5i+lU4te+LBQtXZpUb+vZCUdJEcRSS0zXmkDH7akzaQt+QMAJwkcm76rUWADojzLYRbAAT1pYbY7Ke69R3RHnh9fnDXKZkRUrp/obF4obSELWgon59DK+9ZaEcwU8UZdzLWGsljEBWAVm/oad2DiXCzYwFiZgybF6k47cA92FvAU3JN2UQVE X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:48.0083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2dae8d60-6f36-4cc7-a37f-08dce9630560 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4272 From: Perry Yuan There are some firmware parameters that need to be configured when a CPU core is brought online or offline. when CPU is online, it will initialize the workload classification parameters to CPU firmware which will trigger the workload class ID updating function. Once the CPU is going to offline, it will need to disable the workload classification function and clear the history. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Rebase --- drivers/platform/x86/amd/hfi/hfi.c | 90 +++++++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index c0065ba0ed18..c969ee7ea5ee 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -244,6 +244,89 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) return 0; } +static int amd_hfi_set_state(unsigned int cpu, bool state) +{ + int ret; + + ret = wrmsrl_on_cpu(cpu, AMD_WORKLOAD_CLASS_CONFIG, state); + if (ret) + return ret; + + return wrmsrl_on_cpu(cpu, AMD_WORKLOAD_HRST, 0x1); +} + +/** + * amd_hfi_online() - Enable workload classification on @cpu + * @cpu: CPU in which the workload classification will be enabled + * + * Return: 0 on success, negative error code on failure + */ +static int amd_hfi_online(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + struct amd_hfi_classes *hfi_classes; + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + if (!zalloc_cpumask_var(&hfi_info->cpus, GFP_KERNEL)) + return -ENOMEM; + + mutex_lock(&hfi_cpuinfo_lock); + cpumask_set_cpu(cpu, hfi_info->cpus); + + /* + * Check if @cpu as an associated, initialized and ranking data must be filled + */ + hfi_classes = hfi_info->amd_hfi_classes; + if (!hfi_classes) + goto unlock; + + /* Enable the workload classification interface */ + ret = amd_hfi_set_state(cpu, true); + if (ret) + pr_err("wct enable failed for cpu %d\n", cpu); + + mutex_unlock(&hfi_cpuinfo_lock); + return 0; + +unlock: + free_cpumask_var(hfi_info->cpus); + mutex_unlock(&hfi_cpuinfo_lock); + return ret; +} + +/** + * amd_hfi_offline() - Disable workload classification on @cpu + * @cpu: CPU in which the workload classification will be disabled + * + * Remove @cpu from those covered by its HFI instance. + * + * Return: 0 on success, negative error code on failure + */ +static int amd_hfi_offline(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = &per_cpu(amd_hfi_cpuinfo, cpu); + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + mutex_lock(&hfi_cpuinfo_lock); + + /* Disable the workload classification interface */ + ret = amd_hfi_set_state(cpu, false); + if (ret) + pr_err("wct disable failed for cpu %d\n", cpu); + + mutex_unlock(&hfi_cpuinfo_lock); + + free_cpumask_var(hfi_info->cpus); + + return 0; +} + static int update_hfi_ipcc_scores(struct amd_hfi_data *amd_hfi_data) { int cpu; @@ -362,8 +445,13 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) goto out; + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/amd_hfi:online", + amd_hfi_online, amd_hfi_offline); + if (ret < 0) + goto out; + out: - return ret; + return ret < 0 ? ret : 0; } static struct platform_driver amd_hfi_driver = { From patchwork Thu Oct 10 19:37:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830945 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2088.outbound.protection.outlook.com [40.107.100.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E6E41990C1; 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Thu, 10 Oct 2024 14:37:47 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 09/13] platform/x86: hfi: add power management callback Date: Thu, 10 Oct 2024 14:37:01 -0500 Message-ID: <20241010193705.10362-10-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C6:EE_|LV3PR12MB9141:EE_ X-MS-Office365-Filtering-Correlation-Id: 621fdf6e-811c-48f5-d6bd-08dce963062a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: 0REJE2tNXjy3F6ECR0kXrICT+kjJ3XFQT3mpdRrVCFpOaAGUreM3gWkxNJ+zb9CGSmSKs9nt7jjrQXN+bmGlMZMMlumHLb+LNXqDdv8olGoygGamozjb7MtXslhmd1DNdPNsLQlDSGlL2VyVDdN/d+nL2SYU5riIFzTx2j4h+pPf8wB1dprreycykdfiuiHB/qObdu2J2YAVHRYVjccKyLImRMxmztVKeL3LHWVxsp8aGfLN1hjGJbRADfH+VL0Yfq14Yvk9APYln3ewzMMW7oGxD2rEOEXFiCytqErDclNOY3Tr6GMeNnFUind89LynBQtq+/5CyGXlPEhQd5P7eW73DC6xOh8HIa83BbDYLt4nmPCGad97P1i/EsAMJrat4Y5ICN0PXz+Io0+9/y6JGyEch5wubrYxeFTQJy7rVwtY3QKxeKnsF32dR9uXni/f88gv6ZNuQsm4bwTk1u7g1OcFkfsx3+gD2dOzKyA+h2lzuXDWZNu8W4unDxQ/iVUL7R8JcLr4srR3QKTsdxHoTmQIAwydW2ol4gaXNmG1bcyQXISnUcXTH1QDqmZGnNNnElguCpKplyW7btRm7I3Bm9TUzkO1MR/MjFx1DQm5Pt1us1R0RgSHrQNwtWoqqdO81IWBGBlgl1hlR3ncnj6IlHNvJVk6YBdUm63sdr1nShKTClneFWFwvVUnd9fc1VvQ7jF5Ic3oeReCf4YrmA9pKab3sd7xsyhDj4M+AaS8dKrPtQu57LSYh3fignntb/myC58UEAwoskssIu5bIx9w3zdcONfpVdfps4Lnsv/mMgl3G7UUHKMu7/s5fsgAAUtrxG9f/JOPmyPRWS6yFMspSF/cFqQ9Pr/tsSnysMUFO0QWKzE+Fwd77IvHPWeMh0QDRfOkthVwHy0rq/+1QlyqO+2xyCfPFeyLGDtrhg2IR01Sr1xWKl8L3lETaXk737bIQPE+t8FnViMnU8FzjHpAbNkwtuk5+xdE4AT/W3ICKCd4BLX0h4UhSIwZPBaoSXZHULs/hkzqHvdkOGrdER0F28EwwsA07uXxuxKZw8NbyfMCLsUvD4zHGw73g98NbRiYhqs2hnDXdv8cNZsGk3ofMgBP9SrsKh0dp/F7EXFk/yFsLyw+9U+CFSoB/ry9RrSbpYTbGwxqt2WtDJBUHinE0KB+Q3L22ps3S3xgeu8Il9OSzKy6uMKLrp4U8jOw6e2+FRO1XeX7d0sZ7yNpBYsGwdRk9ZW3rUQkSV5OtZjvUysxetTE53bAV6KchtnpS3h+YasVrTjVTi8q3LHGUh5Oq1jxrWDa3blSjPBvuqw7JjOv3D3Zsou/pCq/lRw/+4MNelD12yFOCwwnr1R1cmA2wgx+G8Nv8ARCCKq/CWjF+UQZcjNsJc6/kFzcRq1FiXIJ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:49.3335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 621fdf6e-811c-48f5-d6bd-08dce963062a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9141 From: Perry Yuan Introduces power management callbacks for the `amd_hfi` driver. Specifically, the `suspend` and `resume` callbacks have been added to handle the necessary operations during system low power states and wake-up. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Whitespace changes * Use on online CPUs not present ones --- drivers/platform/x86/amd/hfi/hfi.c | 33 ++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index c969ee7ea5ee..0263993b0a94 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -407,6 +407,38 @@ static int amd_hfi_metadata_parser(struct platform_device *pdev, return ret; } +static int amd_hfi_pm_resume(struct device *dev) +{ + int ret, cpu; + + for_each_present_cpu(cpu) { + ret = amd_hfi_set_state(cpu, true); + if (ret < 0) { + dev_err(dev, "failed to enable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int amd_hfi_pm_suspend(struct device *dev) +{ + int ret, cpu; + + for_each_online_cpu(cpu) { + ret = amd_hfi_set_state(cpu, false); + if (ret < 0) { + dev_err(dev, "failed to disable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(amd_hfi_pm_ops, amd_hfi_pm_suspend, amd_hfi_pm_resume); + static const struct acpi_device_id amd_hfi_platform_match[] = { { "AMDI0104", 0}, { } @@ -458,6 +490,7 @@ static struct platform_driver amd_hfi_driver = { .driver = { .name = AMD_HFI_DRIVER, .owner = THIS_MODULE, + .pm = &amd_hfi_pm_ops, .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), }, .probe = amd_hfi_probe, From patchwork Thu Oct 10 19:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830948 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2068.outbound.protection.outlook.com [40.107.94.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D90C1EABA6; Thu, 10 Oct 2024 19:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 10 Oct 2024 14:37:48 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 10/13] x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors Date: Thu, 10 Oct 2024 14:37:02 -0500 Message-ID: <20241010193705.10362-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|CY8PR12MB7413:EE_ X-MS-Office365-Filtering-Correlation-Id: 3aff80c1-5765-407f-a541-08dce96306c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: y6Q3fReQxGnsgimihTNYp/nH+hMgGz4wVVIOamIxwK1sDF8pwuzXCtdujcrlIfeBkPrwlQTtkGIwyQ8fyos0pOJMB4Gp/TlPrg8wCOCR0eoIGGIKCj+YJlbOpmD8YKquP8f/6eW8PDS//zLiG67N2oZ5w2037vHkKUaZdmlEoN9ePCZuPIRc5ANW60iRw0r8xqhAjhgUQDrOqUm0zqttadPCVkDLHliRyA+TrBgbmT8Hi4JnSYHcTU5vtDWrAStcKlCjfL1N6vfo4KjMDgcHy7nBjmcgGRAhq4+MZY9Fb1jkp8/7NSTye0G+sg1kgzaXWfIBFOBnb1O+ZSSMaCCiLaVrvsQe7Y8Na8qUeqihBRui2QehdyiAT8tZUsOJktJw1Vw775rnUN3+3UXh4tpQPLruF95GSX3RplFVg9fguE+0tsekidzt7ruYyCFG5PtrZZhUBO100nj8+R31Qze9QqwbXpDsJT+Lx+dUkWODhI5LQHZHKmMzHMSSyIBQplz5lHB2GYp0Lv8Gqryf6iV85KObhq0m0ht6TkZ0A45NWuhrFHGiqABvDNC2j8qMgFnh80jsbRX3+GuiFPhoGwV4T2Gd88c2k6ngVexgoxO2bboDzPVoo/sbPEG3sCN+McHGDOx0PCDOeZe51gqsVR/jttbtyZ67qz6op+Xw+R2RihXelIuqd92PvHNJfFhweGGv/VaIbRmHKGdINqRLc9XHrh5/QqdCz3lY9EIQm+FHmkvEOyOYBmJrimGGFXJxVSmapiCOvly3WuZpInveaSqyXL/d4BEri8j9VVNS/J2mZ8giMZLvOotugFxE7KrxQEQOflFFYlTrUlG0FTt0T++qWQwpnksr74HjqGaQLfb1uOSOjjEYkV5KNxt7rUsH8adcmlaFpmBAZnI/EJa1+ORW4SYqVPVvYtloajfCBIEFRoCdbl8+7W1wPkaq3RDcwBOEQdggg8KkschV0NpSZmlm1BaFbjiwdncLS7Tqp+wQcdu6NoIGKSTo4sfBdXjS5+Vz0TdpjYDw48lnxeJY1bxbfct73ZFe0jjpj8XauNfuBkZHr+EGllFZjvRFo8ym3WzMjBOA1qNGHkQps3Qfv4r2xxpeXPxIt+tW41F78GRbaLCyBhYFq0foZek7tMVQy6fJ8LeK2UmdsOnZGznrqW7qFC+4PYFoAD3oa5clvhNL0qszzzkVHncasCjk0ZabeQfk8H13t8KLzAMz/tQxezvQtdu/AsUYe05PbsY2WiJ/BKIw45M/uYlbM8wgGhITi/bbej/bSne8nXobd31l+hHnInG/T3XvzwmImDATVxseSCjSrQMIoixiAkSQjqZ2U8pXNT2WDyL8UeRjycbRHt6FTE5sUCsNmC1/wUKbNk2bCWjgOXFB2AOeiS4QsZCfbW2M X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:50.3571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3aff80c1-5765-407f-a541-08dce96306c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7413 From: Perry Yuan Enable the SD_ASYM_PACKING domain flag for the DIE domain on AMD heterogeneous processors. This flag is beneficial for processors with one or more CCDs and relies on x86_sched_itmt_flags(). Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- v2: * Whitespace --- arch/x86/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 766f092dab80..c01bb75d0375 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -497,8 +497,9 @@ static int x86_cluster_flags(void) static int x86_die_flags(void) { - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return x86_sched_itmt_flags(); + if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) || + cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return x86_sched_itmt_flags(); return 0; } From patchwork Thu Oct 10 19:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830946 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2082.outbound.protection.outlook.com [40.107.94.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 209971E8837; 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Thu, 10 Oct 2024 14:37:49 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 11/13] x86/process: Clear hardware feedback history for AMD processors Date: Thu, 10 Oct 2024 14:37:03 -0500 Message-ID: <20241010193705.10362-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|SA1PR12MB7175:EE_ X-MS-Office365-Filtering-Correlation-Id: a1071107-5749-43ec-3008-08dce9630874 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: 5vUuDEVW5M+9u4+LIAaZNJQB1TBRQH8bSKmjTWpL9gxBUtW3z/1ng4+8ur9gcZWLlNAq3v96KJOaZ+DIuZRIf2gSwrK1i5cq/pYy9xMcxOc+ekdwOJXt8jdyrCMtTXgVrbnPtLylPbloyjIzqPR/6nmksOGAWaGNBDqZ1P08TkHVRV66VWvgnLJGxvj2IVbTFlmA2fGWafodGV7MDBzv6W+BDx/zC5Fikcalx2+oeMTXf611YrBzAqQkIkVpWAtCiEO7jaZczgIEsO9NkpEO7t406yaUN2MUC2TH3ObQ1/UF2Fvzrz3m/GvwNRfG/vqujUZRyDFdstGsz8QhFjq6ihxlfsXAA1Els9jJ01dlo2y236DdBmx3Zepuc/Bp2mZHpqS/BtCPFIGxJH6SehoDtcL43c/3+T7tVfxTDww29vgS2/w8AAyebXm7eknS72/hfDj2oKS6XDFV5GBHOGCf+bOZaYsBtXHWOtV8yTPwgcOibfI8GK3dtfwfmCQc+o3pU4CRf28+jMnnWnHqzbSE6BD7kjjmjOgH3zQaumyx86SyP+sB09yhDjqGfRXSP1AxBuMbKoAw4d50v6bc2NTemaPrTHFoWxMUTkAEgKA/KCrlWauBY1nVbUUu1u+WFG39z7/jQAB+EfD5tFtk8BH3u2L/tIKXXrzKcTZq1NjPuN+hdmb8C4/tofEDpBxWqeg41NaApuDzC3/T17y0ZceCLJ4/5fAlMLRzMRyOuj9InZqB6wrlkGpRwSMbwfFEE9T1xIoNMDM5+L2WSy5taFnUA1uAu5rMLNq1LK/jDHuznoF9DGCYVEomyZmKMzh/DH2PZEA0lIhide90Vf0xlhHI2tP08K/8n4TbtZ3Ntwlk/xgU/L+r/ipJ+ELGT9EIBx9AZ17miAgmoh2d6nFcwj1JgUUMW8T7dFud7Ll0TktaEexqtRjz5NeLXMpbpIFQx5LwZ/QJonrzzjm2EDn4DJqxycjpOZZYMSGYP6xNgX3zi8EZp/DGL7BIqRLpyG/k8qh2mZ4LywBh6Yk3R3rcA2ZBajZRNWcPdHXleHRrf8EHN3mJIW9nwH6PM4dZUZhLozfsdUkqcwX3DuymZxt3skuBbZ3SaciT1uA02AXJBhFDfRl4WHe8H/S8ah+aD8OhSMX4RAV5iTTrT2ZUxZpb5R5rVVbBLr2IAfHNFu2uJjtero6eUlA8j/GWBxE1twvdTUZAUP0gw03nDyzh5v1vZzd/icxfjq6lIUFguNRx/3qMAw6oFAT73DzUKRtr7OO2u5s/z4jrB736C+2ZBGXE5JXv1ZMuF0j4JDv0DEjH2W7DyoN1VSH1ye8JzepsFuYiICNUvQVDYwBT8IExaKf9MX9nIoZvCbRkppCJeiFCoi7J8xtFsVtgCMhHejFtO5QRJiFa X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:53.0602 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1071107-5749-43ec-3008-08dce9630874 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7175 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Fix function name * Use static keys --- arch/x86/include/asm/hreset.h | 6 ++++++ arch/x86/kernel/cpu/common.c | 15 +++++++++++++++ arch/x86/kernel/process_32.c | 3 +++ arch/x86/kernel/process_64.c | 3 +++ 4 files changed, 27 insertions(+) create mode 100644 arch/x86/include/asm/hreset.h diff --git a/arch/x86/include/asm/hreset.h b/arch/x86/include/asm/hreset.h new file mode 100644 index 000000000000..ae1f72602bbd --- /dev/null +++ b/arch/x86/include/asm/hreset.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_HRESET_H + +void reset_hardware_history_hetero(void); + +#endif /* _ASM_X86_HRESET_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 07a34d723505..887821e97e54 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -403,6 +404,7 @@ static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_C X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; +static DEFINE_STATIC_KEY_FALSE_RO(hardware_history_features); void native_write_cr0(unsigned long val) { @@ -481,6 +483,12 @@ void cr4_init(void) this_cpu_write(cpu_tlbstate.cr4, cr4); } +static void __init setup_hreset(struct cpuinfo_x86 *c) +{ + if (cpu_feature_enabled(X86_FEATURE_WORKLOAD_CLASS)) + static_key_enable_cpuslocked(&hardware_history_features.key); +} + /* * Once CPU feature detection is finished (and boot params have been * parsed), record any of the sensitive CR bits that are set, and @@ -1844,6 +1852,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) setup_smep(c); setup_smap(c); setup_umip(c); + setup_hreset(c); /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { @@ -2410,3 +2419,9 @@ void __init arch_cpu_finalize_init(void) */ mem_encrypt_init(); } + +__always_inline void reset_hardware_history_hetero(void) +{ + if (static_branch_unlikely(&hardware_history_features)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); +} diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 0917c7f25720..6a3a1339f7a7 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include "process.h" @@ -213,6 +214,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + reset_hardware_history_hetero(); + return prev_p; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 226472332a70..ea7f765c6262 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include #include @@ -709,6 +710,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + reset_hardware_history_hetero(); + return prev_p; } From patchwork Thu Oct 10 19:37:04 2024 Content-Type: text/plain; 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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 12/13] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Date: Thu, 10 Oct 2024 14:37:04 -0500 Message-ID: <20241010193705.10362-13-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|BL1PR12MB5873:EE_ X-MS-Office365-Filtering-Correlation-Id: f35635fe-6677-4975-7931-08dce96308df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: oHUZj2RZHOurvBQJKQsOp9GH4QCI8Eleis3evidIq1i0mN4hjK6ekf6/J+ayI/SKSDOT+3VPreKPdg/OsLuuTmcbAWkdt0upzGGNfuz1G6xShUO85fGmCi+nCVcKGu8jYDk4HkldiBlQIWMCsQpKEok9b5b9BpGHzrGbrYiZJVsM5/iX3r1hlojwkNZ+YuhjNuhCcKzBWd7XNvlKq19zK1zg7MHcXUvVIfd8GB60eEYJFoJ2kepnK70lIb92ZV1XlCKKk3gBXkGAMMKB5Xpqw6/55Udtjk5x/ZYLJGx/rQJvoBtKAGxBo57Yyt3mPjXeNJKlbKzRGWrumwBMgkm1h7Oa/ZteRiEmTTrtKAaAoqY0tk2Jp5gP3oP7CeMdSNhKjZciykLtx3vBYwR+326zODu3k1btSZa493PrHDo4Ah3+3o7Ni5+Kgufu+XJfallExPOTge1E+I7dMBJPKMfhTsESNJtgUKMjj5CI1l1Zg+PY4XpuRmrYOKCIegZEnNmUunb4UAXzoEuZOttOcCjtP/nTp98jaxGe2UKJOVOzKlJNplymASyVGsidTdmME0Huf65khPbFghp5R7SsRs7sqrHeP2hF10rLMR/sq7SqMhr4n/C1sAiIMy5KrNWrcHBOB6Pq56acGkyO+dk5V2Y6OUffClC9rjo2D2mKUu1qcBLMJVLvLzQDGDEErD4qnh8eTHFk3cOMJEg7oT+K6ClgCwMo8ZlDnQ78SkQAT1c1sFAcp7xB7GE5FRaQ8OuypW2JJTzYZwZIA63jIZHmWhJ4hlnNGsAdbdpmr3erkQkNZAsZCHs8E6kcEhN0x0kcIY4uUIh+trHRsr1+pqBiJyboCYvM5BJR54jcZ5C5A7KrqJXBTH/2s2wVdEHZrjIYYJVTETaX+KGG5KaamJUqz9VmZnl4Lhe/u7Kl1CsaVomCzFQqjptHsCo8m1YywbRrn82Uj90+w3eZyyXfbg7WJiz/RxasbuwQOJYeCZ5gSCZeA4fuNUB9bvNuoXn9Tm36LWWdh1taKjwlfutSaF9XNHb/2vwApaor+ic/Fa+1QVlRz8rBNVKQhwJnfcitb45c66FnKeAdTv6Cw0RTZA1luQ/yqq5awK91yf7CkTBcRfnRgVwzugLgE7ZLsJq72MVY2yoMCqhlaOEAdT0bf1jI4LufJRcSkAmY6gz4DnPSlEdj3VwxkdEAk/ULV6QcLkAmj/2GvgFZ1u0yqsGFam1wNYI/V5ulktgMPBal36VG6ikDfU8RImdNeWa+wCW4oNZ3zToJolzhcOK4pcosXjIsOFhI/zV0qUa+K5Ev9sWFdlnw1VBYMgmN4+VC2p6ASDg39RLkPw7pNLxuyTKIpGP7633llyhCcQucr/hAMVPugmpdh7QAR6hKPIocV7zi5JICv9/9 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:53.8727 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f35635fe-6677-4975-7931-08dce96308df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5873 On designs that have workload classification, it's preferred that the amd-hfi driver is used to provide hints to the scheduler of which cores to use instead of the amd-pstate driver. Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 30415c30d8b4..0751579ef06c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -780,6 +780,10 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) /* user disabled or not detected */ if (!amd_pstate_prefcore) return; + /* should use amd-hfi instead */ + if (boot_cpu_has(X86_FEATURE_WORKLOAD_CLASS) && + IS_ENABLED(CONFIG_AMD_HFI)) + return; cpudata->hw_prefcore = true; From patchwork Thu Oct 10 19:37:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13830947 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2062.outbound.protection.outlook.com [40.107.95.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A456C1CF2B4; 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Thu, 10 Oct 2024 14:37:52 -0500 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 13/13] platform/x86/amd: hfi: Set ITMT priority from ranking data Date: Thu, 10 Oct 2024 14:37:05 -0500 Message-ID: <20241010193705.10362-14-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|MW5PR12MB5682:EE_ X-MS-Office365-Filtering-Correlation-Id: a3738b1b-d99c-4f6e-894d-08dce9630930 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: I+5C4qrkIdTNcPemA4x4qRscndtj+8Tjbl31FSswMkKViwy96Um9qPoQU/z7EhWPpdqoJluYpvRXnCW4bBNP9ie9Nmdu8apI85bvBUT5ieW1Wu4REbdxdoLD4/cPpVuP8Xr4Ddqqvq8GnWYFWE6FLl/L4wghA/SP9LI9X4VJwsXzwEhLmqYei1TbFGwXVLJ1ltniHPItOyXUAAu46GX3QbQJsKcfgFrLAbFgQg+AaCHrbH6twl2jl5XnTShB3c5xmoT+4Sl58lWkuuD2//FiTDeRxA81qIzR+yMMvpigDRpvd+ih3GdlApW3Um7bOeP9xFfX5wkb9kopq1Swq0Xb34Ohlz6IGJjviGQTy6pgCNoroBuTezLIyVAb4vudCO2gMm07M4aVVGiryGBNYpZBS9vSYtADE8S6q7ZiT5CfsjMxqsmOqlRqSrLsWn1DGEFmovLEJxF1wgjPPwq9FUxBPQc0E4Rmdfqdsyt/k87QjdHzx7TiD0AJAZOdMtN647TSQAxi7jhZXLO7tilbQNIDSFI9Ldpv8derBw8P581CW25uyzCx1txUFoshJmwbi63J8OHs33Vv74wsFlGeuFjuCDVz7Gy9csanQVybQjC/0f2qTPqF55aPYQoxsNmSPmaZS6Ek3Xv9mfZ48zIURwPZM/h9hGmkDln5Ok3GlMMV45uZdjsA09zNRWVMvOjn4jWKyeOWahlsaEm9DhaQOFf1kINxPiSn1epeORhftYvnWH/NqRWwDf90syDloPKIuECs9bnQopf0zMTG7c2wCCztmml/F83HNYg8GtewOB3TEr+a+wsOZXmuhsUNdZ6LDfIWT7HYdW7YDM2WfbcUo3wUlylz1nEZGrGIJCAvlvnUQw9TPHEM1bceRFK4h1A3zbL/7+evlWYQJmfM7IIC+DVPcgZd8yUW6cu2N6D1A6rpbejh1tCEp3ICxEBpnwBDDQ/aBdoAiJHFOl3/wX460JjI+OVu1gOjyNhtlEpRP83xENz38RDKZyymX97qhk8/6KfKNavl1qWosfAbwjDaXTHGt0XxnYPpbPrkeu+3WlesUGYRI06dIGypwBnfSupxqvRzwaSs/Xk9iyhgKpfZEO2pQxnw8CadH/tGEQ6M8JEiTPiN7ZqeOhHI1vq8mVM5nTNmSJY/asJvk7IHg2aPEvSLW3Vkcgow6WvLow3J1M7ppZ0+8lqD9nSynDkQqgMKf+k3EaN4IjJz4EJXhLQAz0hia6Wy196py+vNAu0WkKG7qiRzQ9c8v3T8ZN4cP0gctMy5Vy8zviWtEVg4VOvMHUs+L/D5zIuWEdj/FDpgxT9IzKSP0YtP/k+DidKvMo89S7uV6v20uy7iY+VzsUojEx3nL6EPkUGiEX1uC8vErCmW0Ow= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:54.4040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3738b1b-d99c-4f6e-894d-08dce9630930 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5682 The static ranking data that is read at module load should be used to set up the priorities for the cores relative to the performance values. Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/Kconfig | 1 + drivers/platform/x86/amd/hfi/hfi.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig index 08051cd4f74d..4dfa7641b35b 100644 --- a/drivers/platform/x86/amd/hfi/Kconfig +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -7,6 +7,7 @@ config AMD_HFI bool "AMD Hetero Core Hardware Feedback Driver" depends on ACPI depends on CPU_SUP_AMD + depends on SCHED_MC_PRIO help Select this option to enable the AMD Heterogeneous Core Hardware Feedback Interface. If selected, hardware provides runtime thread classification guidance to the operating system diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 0263993b0a94..f212820a0e4a 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -121,6 +121,12 @@ static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = static DEFINE_MUTEX(hfi_cpuinfo_lock); +static void amd_hfi_sched_itmt_work(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_amd_hfi_itmt_work, amd_hfi_sched_itmt_work); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -241,6 +247,8 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], hfi_cpuinfo->amd_hfi_classes[i].perf); + sched_set_itmt_core_prio(hfi_cpuinfo->ipcc_scores[0], cpu); + return 0; } @@ -482,6 +490,7 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret < 0) goto out; + schedule_work(&sched_amd_hfi_itmt_work); out: return ret < 0 ? ret : 0; }