From patchwork Fri Oct 11 21:43:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 13833189 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D666C1D1721 for ; Fri, 11 Oct 2024 21:44:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728683057; cv=none; b=XSNFOOs0xMt/49s9PK6+yQWTYt/D+vAEcuYvJT9puYKdNGpz3M/lRxQL4CSmzqD6C1n1GdfPZscz0Qyma9RSDU2u7lAfPX/xl2yVFLFTR0a1/6H7fbsTSZGKDY1p1Er7jnd9zxGhp51olnhXcyHwrTPJezdGPm7iQRRdBEf4Bpw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728683057; c=relaxed/simple; bh=Alfb43ggy1morVAhVCl9j9Qs+u6QkOqSpSocYaViI8Y=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=R/DTtoPUk9+tYkmO7mC+AKXBnFbof+h+eKMiDNHRVCXvr3MrBTCZ9ICA6wL3lcBc0mlq3fLLynLBHekfjIC9q0+TSRzy1zVROLnWfeLhT6T212HTuRuvdqNH01pO7xse7VNsVRWZf+863f4rWV15D0nLb4IbG4Phw5T4b1QEgJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=kxsPETSC; arc=none smtp.client-ip=209.85.210.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="kxsPETSC" Received: by mail-pf1-f201.google.com with SMTP id d2e1a72fcca58-71e368933adso2134392b3a.2 for ; Fri, 11 Oct 2024 14:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1728683054; x=1729287854; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=W8FDOlqwvEsdAJAf8IdqafehVhAI8JwdIbxbRDiLpiY=; b=kxsPETSCMazyrqlUZ+G7O95fuiPcGSkrzp9eB56qC2iRtLKxU7CrNCYH1K0PT5uWWE rIu/HqgfJuP81HV4nMwvt3Lk9dPpZNAQ1O+a65GuMgt7V5R+PeJs4oW3jTN53xFkakkL 54le5HOUTrFuFwj8l0MCRM2V2C24tOVm6LaXKRIFYeugRL2twulrMl/NpiOYJLRROUUD PuFjDfnAonfYij0r9N3+j75DhTafkLfSEXMaC/7p2gtG2Za8vOV9YebrrgQDimTAllrY L68RJGiNEpkW4KfFVCOqTNSGcZeuj6iTDNGVyOkpCQJvcQ2uYp3fVXtE4ac6NDx6cSqk HsvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728683054; x=1729287854; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=W8FDOlqwvEsdAJAf8IdqafehVhAI8JwdIbxbRDiLpiY=; b=SeXXdkl0HQDJMMSBnahN6v/Lex1Svfebm+p3tFe2lGx3/8cz0d4q8hA9/T0TNNmewO DKU14Duu9c6/uUaC5sctLCiyO45MpH2viHrWP+Kes6pvKkp6VsfhXpuznd4EO0ZBsqYD GQYWsvs8K9JjeIc33DsLzjbO6V0GvU978wZrbyF87y/joJ53NVVpFG/mnK0+R5wixpIk M/7JvUfMRnusozvaXvAvvqNNC+WmKl1topuEcTt/mGXPqOUMemi6qRUNMSGwUBDLCF3F CdJBArbxm80/s5l16pFSNg4jciE1OVCTH/1C+8OOlNha4kSoBV94Nr6p11nEvVpS7IAY UdZA== X-Gm-Message-State: AOJu0Yyci1E+gAC+j45E3tqE7GQkjI0bohpwRxvLbasTYe4GX+SP7wDp D6Ccw+fYyJ21O8HHHT6noEa0kvp2/zda2SN+e4qzH7cKJ7sFVxfnOxn7VVYLhgUjTE0zfdD07Lk Q1D0h2OFtHYHP32PlmfOkagrNHbZpz6siTS0lIyLVdsEF+xFPj0z6C9x9GuSUEiwS+As3vmHlay oC+ecQs8ax1WRbF4590Ek8UPYCH/OSofGH4mt6Veo= X-Google-Smtp-Source: AGHT+IG+CTYjXiI2WYVmaCbmdgx8aJmNp5eEhEtp42YdvInIMKciu2bPG9BFE/JQsrplK7JkLlS0PX/QLI0I4A== X-Received: from loggerhead.c.googlers.com ([fda3:e722:ac3:cc00:f3:525d:ac13:60e1]) (user=jmattson job=sendgmr) by 2002:a05:6a00:6f66:b0:71e:268d:19a6 with SMTP id d2e1a72fcca58-71e37e28a35mr18995b3a.1.1728683053750; Fri, 11 Oct 2024 14:44:13 -0700 (PDT) Date: Fri, 11 Oct 2024 14:43:50 -0700 In-Reply-To: <20241011214353.1625057-1-jmattson@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241011214353.1625057-1-jmattson@google.com> X-Mailer: git-send-email 2.47.0.rc1.288.g06298d1525-goog Message-ID: <20241011214353.1625057-2-jmattson@google.com> Subject: [PATCH v5 1/4] x86/cpufeatures: Clarify semantics of X86_FEATURE_IBPB From: Jim Mattson To: kvm@vger.kernel.org Cc: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jpoimboe@kernel.org, kai.huang@intel.com, linux-kernel@vger.kernel.org, mingo@redhat.com, pawan.kumar.gupta@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, seanjc@google.com, tglx@linutronix.de, x86@kernel.org, Jim Mattson Since this synthetic feature bit is set on AMD CPUs that don't flush the RSB on an IBPB, indicate as much in the comment, to avoid potential confusion with the Intel IBPB semantics. Signed-off-by: Jim Mattson --- arch/x86/include/asm/cpufeatures.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index dd4682857c12..644b3e1e1ab6 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -215,7 +215,7 @@ #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Speculative Store Bypass. */ #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation via LS_CFG MSR */ #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */ -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */ +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */ #define X86_FEATURE_STIBP ( 7*32+27) /* "stibp" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_ZEN ( 7*32+28) /* Generic flag for all Zen and newer */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* L1TF workaround PTE inversion */ From patchwork Fri Oct 11 21:43:51 2024 Content-Type: text/plain; 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Fri, 11 Oct 2024 14:44:19 -0700 (PDT) Date: Fri, 11 Oct 2024 14:43:51 -0700 In-Reply-To: <20241011214353.1625057-1-jmattson@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241011214353.1625057-1-jmattson@google.com> X-Mailer: git-send-email 2.47.0.rc1.288.g06298d1525-goog Message-ID: <20241011214353.1625057-3-jmattson@google.com> Subject: [PATCH v5 2/4] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET From: Jim Mattson To: kvm@vger.kernel.org Cc: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jpoimboe@kernel.org, kai.huang@intel.com, linux-kernel@vger.kernel.org, mingo@redhat.com, pawan.kumar.gupta@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, seanjc@google.com, tglx@linutronix.de, x86@kernel.org, Jim Mattson , Venkatesh Srinivas , Tom Lendacky AMD's initial implementation of IBPB did not clear the return address predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[bit 30]. Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, when determining cross-vendor capabilities. Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson Reviewed-by: Tom Lendacky Reviewed-by: Thomas Gleixner --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 644b3e1e1ab6..a222a24677d7 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -348,6 +348,7 @@ #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */ #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */ +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ From patchwork Fri Oct 11 21:43:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 13833191 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7DE1D1E6D for ; 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Fri, 11 Oct 2024 14:44:23 -0700 (PDT) Date: Fri, 11 Oct 2024 14:43:52 -0700 In-Reply-To: <20241011214353.1625057-1-jmattson@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241011214353.1625057-1-jmattson@google.com> X-Mailer: git-send-email 2.47.0.rc1.288.g06298d1525-goog Message-ID: <20241011214353.1625057-4-jmattson@google.com> Subject: [PATCH v5 3/4] KVM: x86: Advertise AMD_IBPB_RET to userspace From: Jim Mattson To: kvm@vger.kernel.org Cc: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jpoimboe@kernel.org, kai.huang@intel.com, linux-kernel@vger.kernel.org, mingo@redhat.com, pawan.kumar.gupta@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, seanjc@google.com, tglx@linutronix.de, x86@kernel.org, Jim Mattson , Tom Lendacky This is an inherent feature of IA32_PRED_CMD[0], so it is trivially virtualizable (as long as IA32_PRED_CMD[0] is virtualized). Suggested-by: Tom Lendacky Signed-off-by: Jim Mattson Reviewed-by: Tom Lendacky Reviewed-by: Thomas Gleixner --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 41786b834b16..53112669be00 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -755,7 +755,7 @@ void kvm_set_cpu_caps(void) F(CLZERO) | F(XSAVEERPTR) | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | - F(AMD_PSFD) + F(AMD_PSFD) | F(AMD_IBPB_RET) ); /* From patchwork Fri Oct 11 21:43:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 13833192 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CC6A1E2000 for ; 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Fri, 11 Oct 2024 14:44:26 -0700 (PDT) Date: Fri, 11 Oct 2024 14:43:53 -0700 In-Reply-To: <20241011214353.1625057-1-jmattson@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241011214353.1625057-1-jmattson@google.com> X-Mailer: git-send-email 2.47.0.rc1.288.g06298d1525-goog Message-ID: <20241011214353.1625057-5-jmattson@google.com> Subject: [PATCH v5 4/4] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB From: Jim Mattson To: kvm@vger.kernel.org Cc: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jpoimboe@kernel.org, kai.huang@intel.com, linux-kernel@vger.kernel.org, mingo@redhat.com, pawan.kumar.gupta@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, seanjc@google.com, tglx@linutronix.de, x86@kernel.org, Jim Mattson , Venkatesh Srinivas From Intel's documention [1], "CPUID.(EAX=07H,ECX=0):EDX[26] enumerates support for indirect branch restricted speculation (IBRS) and the indirect branch predictor barrier (IBPB)." Further, from [2], "Software that executed before the IBPB command cannot control the predicted targets of indirect branches (4) executed after the command on the same logical processor," where footnote 4 reads, "Note that indirect branches include near call indirect, near jump indirect and near return instructions. Because it includes near returns, it follows that **RSB entries created before an IBPB command cannot control the predicted targets of returns executed after the command on the same logical processor.**" [emphasis mine] On the other hand, AMD's IBPB "may not prevent return branch predictions from being specified by pre-IBPB branch targets" [3]. However, some AMD processors have an "enhanced IBPB" [terminology mine] which does clear the return address predictor. This feature is enumerated by CPUID.80000008:EDX.IBPB_RET[bit 30] [4]. Adjust the cross-vendor features enumerated by KVM_GET_SUPPORTED_CPUID accordingly. [1] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html [2] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/speculative-execution-side-channel-mitigations.html#Footnotes [3] https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1040.html [4] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf Fixes: 0c54914d0c52 ("KVM: x86: use Intel speculation bugs and features as derived in generic x86 code") Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson Reviewed-by: Tom Lendacky --- arch/x86/kvm/cpuid.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 53112669be00..d695e7bc41ed 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -690,7 +690,9 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); - if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) + if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) && + boot_cpu_has(X86_FEATURE_AMD_IBPB) && + boot_cpu_has(X86_FEATURE_AMD_IBRS)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); if (boot_cpu_has(X86_FEATURE_STIBP)) kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); @@ -763,8 +765,12 @@ void kvm_set_cpu_caps(void) * arch/x86/kernel/cpu/bugs.c is kind enough to * record that in cpufeatures so use them. */ - if (boot_cpu_has(X86_FEATURE_IBPB)) + if (boot_cpu_has(X86_FEATURE_IBPB)) { kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) && + !boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) + kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET); + } if (boot_cpu_has(X86_FEATURE_IBRS)) kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); if (boot_cpu_has(X86_FEATURE_STIBP))