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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:32 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 1/8] target/riscv: Add Ssdbltrp CSRs handling Date: Mon, 14 Oct 2024 13:22:11 +0200 Message-ID: <20241014112225.90297-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_helper.c | 20 +++++++++++++++++ target/riscv/csr.c | 45 ++++++++++++++++++++++++++++++--------- 5 files changed, 63 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a84e719d3f..ee984bf270 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -553,6 +553,7 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index da1723496c..3a5588d4df 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -558,6 +558,7 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ +#define MSTATUS_SDT 0x01000000 #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL @@ -588,6 +589,7 @@ typedef enum { #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 +#define SSTATUS_SDT 0x01000000 #define SSTATUS64_UXL 0x0000000300000000ULL @@ -777,11 +779,13 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_DTE (1ULL << 59) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) /* For RV32 */ +#define MENVCFGH_DTE BIT(27) #define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) @@ -795,11 +799,13 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_DTE MENVCFG_DTE #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE /* For RV32 */ +#define HENVCFGH_DTE MENVCFGH_DTE #define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index ae2a945b5f..dd804f95d4 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -77,6 +77,7 @@ struct RISCVCPUConfig { bool ext_smstateen; bool ext_sstc; bool ext_smcntrpmf; + bool ext_ssdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9d0400035f..77e7736d8a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -63,6 +63,22 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) #endif } +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + if (!riscv_cpu_cfg(env)->ext_ssdbltrp) { + return false; + } + if (virt) { + return (env->henvcfg & HENVCFG_DTE) != 0; + } else { + return (env->menvcfg & MENVCFG_DTE) != 0; + } +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { @@ -562,6 +578,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) g_assert(riscv_has_ext(env, RVH)); + if (riscv_env_smode_dbltrp_enabled(env, current_virt)) { + mstatus_mask |= MSTATUS_SDT; + } + if (current_virt) { /* Current V=1 and we are about to change to V=0 */ env->vsstatus = env->mstatus & mstatus_mask; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e5de72453c..d8280ec956 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -540,6 +540,15 @@ static RISCVException aia_hmode32(CPURISCVState *env, int csrno) return hmode32(env, csrno); } +static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + return RISCV_EXCP_NONE; + } + + return hmode(env, csrno); +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->pmp) { @@ -1402,7 +1411,7 @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | SSTATUS_SDT; /* * Spec allows for bits 13:63 to be either read-only or writable. @@ -1600,6 +1609,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mask |= MSTATUS_VS; } + if (riscv_env_smode_dbltrp_enabled(env, env->virt_enabled)) { + mask |= MSTATUS_SDT; + if ((val & MSTATUS_SDT) != 0) { + mstatus &= ~MSTATUS_SIE; + val &= ~MSTATUS_SIE; + } + } + if (xl != MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |= MSTATUS_MPV | MSTATUS_GVA; @@ -2354,7 +2371,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); @@ -2374,7 +2392,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); uint64_t valh = (uint64_t)val << 32; env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); @@ -2425,9 +2444,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 * henvcfg.stce is read_only 0 when menvcfg.stce = 0 * henvcfg.adue is read_only 0 when menvcfg.adue = 0 + * henvcfg.dte is read_only 0 when menvcfg.dte = 0 */ - *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | - env->menvcfg); + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | + HENVCFG_DTE) | env->menvcfg); return RISCV_EXCP_NONE; } @@ -2435,6 +2455,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + uint64_t menvcfg_mask; RISCVException ret; ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); @@ -2443,7 +2464,11 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, } if (riscv_cpu_mxl(env) == MXL_RV64) { - mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); + menvcfg_mask = HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE; + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + menvcfg_mask |= HENVCFG_DTE; + } + mask |= env->menvcfg & menvcfg_mask; } env->henvcfg = (env->henvcfg & ~mask) | (val & mask); @@ -2461,8 +2486,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, return ret; } - *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | - env->menvcfg)) >> 32; + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | + HENVCFG_DTE) | env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } @@ -2470,7 +2495,7 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_ADUE); + HENVCFG_ADUE | HENVCFG_DTE); uint64_t valh = (uint64_t)val << 32; RISCVException ret; @@ -5246,7 +5271,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, + [CSR_MTVAL2] = { "mtval2", dbltrp_hmode, read_mtval2, write_mtval2, .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, .min_priv_ver = PRIV_VERSION_1_12_0 }, From patchwork Mon Oct 14 11:22:12 2024 Content-Type: text/plain; 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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:33 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior Date: Mon, 14 Oct 2024 13:22:12 +0200 Message-ID: <20241014112225.90297-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning to VU from HS. Signed-off-by: Clément Léger --- target/riscv/op_helper.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 6895c7596b..00b6f75102 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -287,6 +287,18 @@ target_ulong helper_sret(CPURISCVState *env) get_field(mstatus, MSTATUS_SPIE)); mstatus = set_field(mstatus, MSTATUS_SPIE, 1); mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); + + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + if (riscv_has_ext(env, RVH)) { + target_ulong prev_vu = get_field(env->hstatus, HSTATUS_SPV) && + prev_priv == PRV_U; + /* Returning to VU from HS, vsstatus.sdt = 0 */ + if (!env->virt_enabled && prev_vu) { + env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + mstatus = set_field(mstatus, MSTATUS_SDT, 0); + } if (env->priv_ver >= PRIV_VERSION_1_12_0) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } @@ -297,7 +309,6 @@ target_ulong helper_sret(CPURISCVState *env) target_ulong hstatus = env->hstatus; prev_virt = get_field(hstatus, HSTATUS_SPV); - hstatus = set_field(hstatus, HSTATUS_SPV, 0); env->hstatus = hstatus; @@ -328,6 +339,22 @@ static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } } +static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatus, + target_ulong prev_priv, + target_ulong prev_virt) +{ + /* If returning to U, VS or VU, sstatus.sdt = 0 */ + if (prev_priv == PRV_U || (prev_virt && + (prev_priv == PRV_S || prev_priv == PRV_U))) { + mstatus = set_field(mstatus, MSTATUS_SDT, 0); + /* If returning to VU, vsstatus.sdt = 0 */ + if (prev_virt && prev_priv == PRV_U) { + env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + + return mstatus; +} target_ulong helper_mret(CPURISCVState *env) { @@ -345,6 +372,9 @@ target_ulong helper_mret(CPURISCVState *env) mstatus = set_field(mstatus, MSTATUS_MPP, riscv_has_ext(env, RVU) ? PRV_U : PRV_M); mstatus = set_field(mstatus, MSTATUS_MPV, 0); + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); + } if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } @@ -382,6 +412,9 @@ target_ulong helper_mnret(CPURISCVState *env) if (prev_priv < PRV_M) { env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false); } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt); + } if (riscv_has_ext(env, RVH) && prev_virt) { riscv_cpu_swap_hypervisor_regs(env); From patchwork Mon Oct 14 11:22:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13834792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CD57D16245 for ; Mon, 14 Oct 2024 11:23:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0J9v-0006Xs-0C; Mon, 14 Oct 2024 07:22:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0J9r-0006VT-MV for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:39 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0J9p-0002cV-PA for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:39 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-37d4a5ecc44so2953341f8f.2 for ; Mon, 14 Oct 2024 04:22:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728904956; x=1729509756; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Xvl0BCdfuSbxLN2r2iyzpL1Dr4H5UKtM3MitHEn5Ro=; b=vN+gZ/Ze+Jpr9YUr7RTD0bsowZTVgPb/7PDg4nsxvuGv0knpFZgOd8ZQuiX6g6Guzr HUnYjGh3D4a+wbhmRGEppNwrwGjup2Vj4Ie1izB3SMb/LhmVJhiteasZfO9lURXYjj2I EEzp7Vg0fVu/aeDieGJAmTN/lkyuMt6C5u975ZWEz/gSWqS3ciUAME0jp2xx4pAtf4i6 5dN+jRMFZfM08pKjD5+4yzclrEx8RBKFxFhxBoNKYIuC7jMMKi+uhX1sr4iB/aPZvidW aCwoanPfcxs6EMk7xufVG1ZBpeV5nWtkrwlv0OLvmnDdUQum+HoxkRhGE0IMSlTt//Zv cnCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728904956; x=1729509756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Xvl0BCdfuSbxLN2r2iyzpL1Dr4H5UKtM3MitHEn5Ro=; b=S65zlL1AMkLKd88kYWRZQHq10KIdfFitL5R3W93Bx/kD/X89bUZUorCzPudKBL0xV4 iaP9DjWIJXbuvcQU3hoZsXMpCx2Ql1MSeoShV5DjciHIYLuMoXzhVh2gPPEm1MS1PT2o acC/9ELe0+IiXgj5CFi+76o6vM4k5SLkEJ7aJhR0rxTAZHOHCwUpuOXSo19XjHJxr7WE Y4tWScWedYKdHJVQ94uI6sSSiSwSwn0v0DoDMgOwtcFWXWB+5VP8TlrCHQXASVVmkICw eC7k+F2pnIRG1s+OgqWVMRH/nVfXLsLUf3AQAwnm+0bAxzvf7x+Vk1x4ImSDZzKDMso1 inUg== X-Forwarded-Encrypted: i=1; AJvYcCVC6yw/EnGGH+Hpor+/Wf4rGu16UiUTtu9zleC/kBwkCgjoJPgL+/Aug0Ib9Ob4qGcD7s89fd7Ajcxm@nongnu.org X-Gm-Message-State: AOJu0YyP6gjXyPgT+bH0Sm3wMQoI88Omx+9OQR1uP0YPwELb53Rzf0QP KuNzsKpxBlHFLZutxWk05F25zoYJJi3eQPaA4bk+niE1Py8wf+x5+sF0ODoAChM= X-Google-Smtp-Source: AGHT+IFTB/L7tF0axs2brZvg17fG9mIyc4+5Q2dmhE3fpbB1PWz/09HLp4+yLKbAmiQis3S/zP/xSA== X-Received: by 2002:a05:6000:1d0:b0:374:cd3e:7d98 with SMTP id ffacd0b85a97d-37d551e3caamr8208016f8f.19.1728904955744; Mon, 14 Oct 2024 04:22:35 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:35 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 3/8] target/riscv: Implement Ssdbltrp exception handling Date: Mon, 14 Oct 2024 13:22:13 +0200 Message-ID: <20241014112225.90297-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cf06cd741a..65347ccd5a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -284,7 +284,7 @@ static const char * const riscv_excp_names[] = { "load_page_fault", "reserved", "store_page_fault", - "reserved", + "double_trap", "reserved", "reserved", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3a5588d4df..5557a86348 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -699,6 +699,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_DOUBLE_TRAP = 0x10, RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 77e7736d8a..5173155070 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1711,6 +1711,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) CPURISCVState *env = &cpu->env; bool virt = env->virt_enabled; bool write_gva = false; + bool vsmode_exc; uint64_t s; int mode; @@ -1725,6 +1726,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1 << cause)); bool vs_injected = env->hvip & (1 << cause) & env->hvien && !(env->mip & (1 << cause)); + bool smode_double_trap = false; + uint64_t hdeleg = async ? env->hideleg : env->hedeleg; target_ulong tval = 0; target_ulong tinst = 0; target_ulong htval = 0; @@ -1841,13 +1844,34 @@ void riscv_cpu_do_interrupt(CPUState *cs) !async && mode == PRV_M; + vsmode_exc = env->virt_enabled && (((hdeleg >> cause) & 1) || vs_injected); + /* + * Check double trap condition only if already in S-mode and targeting + * S-mode + */ + if (cpu->cfg.ext_ssdbltrp && env->priv == PRV_S && mode == PRV_S) { + bool dte = (env->menvcfg & MENVCFG_DTE) != 0; + bool sdt = (env->mstatus & MSTATUS_SDT) != 0; + /* In VS or HS */ + if (riscv_has_ext(env, RVH)) { + if (vsmode_exc) { + /* VS -> VS, use henvcfg instead of menvcfg*/ + dte = (env->henvcfg & HENVCFG_DTE) != 0; + } else if (env->virt_enabled) { + /* VS -> HS, mret/sret always reset dte to false */ + dte = false; + } + } + smode_double_trap = dte && sdt; + if (smode_double_trap) { + mode = PRV_M; + } + } + if (mode == PRV_S) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg = async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && - (((hdeleg >> cause) & 1) || vs_injected)) { + if (vsmode_exc) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt @@ -1880,6 +1904,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s = set_field(s, MSTATUS_SPP, env->priv); s = set_field(s, MSTATUS_SIE, 0); + if (riscv_env_smode_dbltrp_enabled(env, virt)) { + s = set_field(s, MSTATUS_SDT, 1); + } env->mstatus = s; env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); env->sepc = env->pc; @@ -1913,9 +1940,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_MIE, 0); env->mstatus = s; env->mcause = cause | ~(((target_ulong)-1) >> async); + if (smode_double_trap) { + env->mtval2 = env->mcause; + env->mcause = RISCV_EXCP_DOUBLE_TRAP; + } else { + env->mtval2 = mtval2; + } env->mepc = env->pc; env->mtval = tval; - env->mtval2 = mtval2; env->mtinst = tinst; if (cpu->cfg.ext_smrnmi && nmi_execp) { From patchwork Mon Oct 14 11:22:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13834799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47888D16243 for ; Mon, 14 Oct 2024 11:25:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0J9x-0006Z9-Mi; Mon, 14 Oct 2024 07:22:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0J9s-0006Vt-D9 for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:41 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0J9q-0002cg-KJ for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:40 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-37d533b5412so1864712f8f.2 for ; Mon, 14 Oct 2024 04:22:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728904957; x=1729509757; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hfu45ZedV2oYYdcJlwtmsTcYcSwVZM5Rhrrvekmn4k8=; b=UH6JDFFrND2LAVhA0VJ9uuwc/mpP4GrxkZ3eK/YZGrFuYJGare87/cNrdwYi2PnmEZ 8nlYbiqFwCopv8yic0/soHN088bAJ1K1whbsw6iJGpBCaO9cf7ZkofLOeAWObx0daGwf HxlL+PivNgzVpcUBlzGeYyV0IqJfBXIq1jzak+XXlfGGhCXCp4u4Z4LINywvHK6E37Z9 x0rDmD2NKXyKnz4VXqs3t0oraLoEUzFIZ4M/rig1IPPKXeNDQ4GxiEm6vOS6rXoEOR/3 CzAcFERR7zVGX4vFQ7O/SfcJiZ+Okqcl2UzPYZb/H+XE01R23mk/IrRWI10xT5ThPd3u Gkyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728904957; x=1729509757; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hfu45ZedV2oYYdcJlwtmsTcYcSwVZM5Rhrrvekmn4k8=; b=jMCWyerQZnGI0EkNwJKjSTtdeN6gyCgSrLIbVTbfV5ToTSpC/XUQjAjQLKbsirhJAI Mc23FVXUyFGNlRwcLYw7OvQ8z/QxcIxKemVeusk4XWaZ2rBdc+drhGrCnFXhi4RYR+cF 63PypjVfvfja+MYHXtv+/V8n677MKruVY0HEv4xEGSvO0bz71pLZO/PFn0MI1/zv0cbv YfcAPGiwGzC5qH58MhrhQJDhqETy4Dbz7fTrjJgow3ZL0Tr2AawZiH5HY1HKS8Npuf/T p16pKDhOYadH0hqirhNm7I7M2p6Dw8KfQhNmftgFieAoi1FkkmJOFe3JJuCcqRVZnAbS DypQ== X-Forwarded-Encrypted: i=1; AJvYcCUxDuvhyMk2UKAedKQtwPAcXI4jT3BV81ozl26yVVqZKfrMVJO3Bzt8d4k1jLctuuBLhoi9Wx2WzTR6@nongnu.org X-Gm-Message-State: AOJu0YzEANVt8LNebWPRCz7b9eXGhZMZzhYBrd7HVFdn+TU6Y0WYAeIj SqVC/1WWwR3VTvDMDsQLxgmvPh8R/yFkbok2CrPfXzgfBbs+0mjaW7Lpl6W+WTE= X-Google-Smtp-Source: AGHT+IGEz87dAj2XpG48PJ4i3nQmZtvyODMgISsVz2OeZad48TXvTMv1MX19c7lw0kyBmqky4QXirA== X-Received: by 2002:a5d:68c5:0:b0:37d:46a8:ad4e with SMTP id ffacd0b85a97d-37d551b9740mr7558620f8f.15.1728904956802; Mon, 14 Oct 2024 04:22:36 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:36 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch Date: Mon, 14 Oct 2024 13:22:14 +0200 Message-ID: <20241014112225.90297-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the switch to enable the Ssdbltrp ISA extension. Signed-off-by: Clément Léger --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 65347ccd5a..4a146bb637 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -190,6 +190,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1492,6 +1493,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), + MULTI_EXT_CFG_BOOL("ssdbltrp", ext_ssdbltrp, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), From patchwork Mon Oct 14 11:22:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13834796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6B69D16245 for ; Mon, 14 Oct 2024 11:24:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0J9w-0006YI-6V; Mon, 14 Oct 2024 07:22:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0J9t-0006WX-CM for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:41 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0J9r-0002d9-Kv for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:41 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43117ed8adbso45611915e9.2 for ; Mon, 14 Oct 2024 04:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728904958; x=1729509758; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fQQO2T5uiR+FYgD4cQeDW1X+EPKbvqM649D/aATLO28=; b=Rsdz0dKLUyq4qvZLGDmpXelSsVwgsoCPmyjgxL7fVFSGycmF8jIh+M/iuFbLD/gpc+ 05y4bZZiuUIzhFvIXg0z0TwESvvbmvlpDyOEvAyBkKAmzmvdCOQV4lLsHYiBi6O/xhil Z7mIxHVcNkwbXzEalMqWcOIgwRVujZ2SgqUf/hfe5Y+1NRKpqQyzh9cK6DAPJOznnCdl 9sKZXgUeoFOtCfYIX84MniyHVMuU1O3YEmIfwRXFBEQ+Ps07guxa3ulN6tFJCZDsQ/vF aWR6uqbDGfEjdbnkWno1B87lyNgyb2JCfn+pKDspDZpvu1RJ6bm3OsqYd7wa0zm8siAo /32A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728904958; x=1729509758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fQQO2T5uiR+FYgD4cQeDW1X+EPKbvqM649D/aATLO28=; b=iOQRbVdxy66VvlOpGRrDXYwvczA7br1FFk054Dp6n5IRC0j50p6zpBdYNgUe1iBmJa F7bqRBWaaNYqJkknrl5z433bDlkQOai6stPEX5XUPMvr42MeyEChJkPqCDMaA/mJvJRU 6Hx27mVzp7EwMM7oR8FuEZBNtOVwOSKgWSty8/Oab2u1fTE6mcsiHbOs6w9/2Q2RepM/ mCIYcP74xwnJg+iOzpSHmMn+EAytiaAR0+3QwtFPCyS7zOHFebYMgtfK4YLDJAnneaRV j2n8916X34pLQIRWEv1oW4xXgqxBwyhJDwsI9oY+i7YifhrrgdmwWXVAFskNaAmF2xVC yfVg== X-Forwarded-Encrypted: i=1; AJvYcCWQaPRWFt94LYxrqZsJnWrw/i9gNrkeXs+OVDzmt/hhs0N9DKwzYhRgLeOh5PgYHOO5Fd8N4JjUhcDy@nongnu.org X-Gm-Message-State: AOJu0Yz3Cazfd2EKoqlFv9tDDoTc9jdEczY4CmY0C9wKhg0KTFvMmnHT WrHEx4uzb1PPyVeXZjYTwhUsWFwqB1h1MM6gF/nC/n/pV7K6KUSp9x2n8CjFBdA= X-Google-Smtp-Source: AGHT+IEjYxqgLJ2n8zlhNXgKVsYmlQ03KfR0qpjFGlsWbLm/7uQv5GlqIwVpRXnShmdSKGUsKvnKTw== X-Received: by 2002:adf:ffc5:0:b0:374:c1c5:43ca with SMTP id ffacd0b85a97d-37d5ffa3561mr6197519f8f.32.1728904957840; Mon, 14 Oct 2024 04:22:37 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:37 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 5/8] target/riscv: Add Smdbltrp CSRs handling Date: Mon, 14 Oct 2024 13:22:15 +0200 Message-ID: <20241014112225.90297-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Clément Léger --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 15 +++++++++++++++ 4 files changed, 20 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4a146bb637..53e3bb6b37 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -946,6 +946,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) env->mstatus_hs = set_field(env->mstatus_hs, MSTATUS64_UXL, env->misa_mxl); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1); + } } env->mcause = 0; env->miclaim = MIP_SGEIP; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5557a86348..62bab1bf55 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -561,6 +561,7 @@ #define MSTATUS_SDT 0x01000000 #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */ #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index dd804f95d4..4c4caa2b39 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -78,6 +78,7 @@ struct RISCVCPUConfig { bool ext_sstc; bool ext_smcntrpmf; bool ext_ssdbltrp; + bool ext_smdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d8280ec956..cc1940447a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1617,6 +1617,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, } } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |= MSTATUS_MDT; + if ((val & MSTATUS_MDT) != 0) { + mstatus &= ~MSTATUS_MIE; + val &= ~MSTATUS_MIE; + } + } + if (xl != MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |= MSTATUS_MPV | MSTATUS_GVA; @@ -1655,6 +1663,13 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, uint64_t valh = (uint64_t)val << 32; uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |= MSTATUS_MDT; + if ((val & MSTATUS_MDT) != 0) { + env->mstatus &= ~MSTATUS_MIE; + val &= ~MSTATUS_MIE; + } + } env->mstatus = (env->mstatus & ~mask) | (valh & mask); return RISCV_EXCP_NONE; From patchwork Mon Oct 14 11:22:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13834798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44907D16245 for ; Mon, 14 Oct 2024 11:24:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0JA3-0006bw-8K; Mon, 14 Oct 2024 07:22:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0J9x-0006ZD-Qr for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:45 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0J9v-0002dp-1H for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:45 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-37d4c482844so2351814f8f.0 for ; Mon, 14 Oct 2024 04:22:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728904959; x=1729509759; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iLp4r6f6llKlFkIQR3exhrK8GnjMUvUuiR9NnPTHniw=; b=WLVCQyOzLmCtAkGRxPuHpOhZujOWR4PvHm0zK3Gd0etwBtnxllwLWn61IRpl1//GVj TIQyMGUXOINzHJJ6SFvB9RzO4eP44qmJYiQjIAuSGb+Lx5w7IC0Evcv3hnqiKdVPoDRg N7gPM69hLl/SNzz+tiNYozFUBhmqROGglhPIe6Sagp4FaJOdR0n3QuDDe5U4/ATo8ejM XKXv0zDNH0T2zufpxzYztia0CugOySGJPoMJ5NGn3fvOuycCQlkFAU5+TBnlB0duS2tD aFyl5Z9RKzakDeD4Pv7vNwz5JsecQrQE79jGqU8OBlWWXjTpAtSUj6/K6qfK2P+W+IJ6 HekA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728904959; x=1729509759; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iLp4r6f6llKlFkIQR3exhrK8GnjMUvUuiR9NnPTHniw=; b=EFwfwpeUXnXJOz3tyOTa2HX5TmFaeKrq6PRuJZwruFPR1/2aH70oLxQcMA9EWtSV4U +CD5VhWm+E9m6gONOWvakK+GfzjAXIXEIb/CF0rJ5TflWE0opU0TnrSSifoXHG6y0ULH 2fEXiLpzQ9D+luuyBV8HlDFrqutE6S2sVrmI58H4NYJAbZL1S8elk/YVtKPrALYofqmL QcdOXJHEGJ2TpBr2wbob6yHllmICAkuRTdZVfuJZEykWqWIP5+/f8IA/c/jb30rqKnkt ImIzW+bUjP/4F5fph9j62rGDz9qQ6DR8F7aqLlmzjfJZNO32rRTilztsHxOQuJl4+4Q4 MURg== X-Forwarded-Encrypted: i=1; AJvYcCXDYeobWD9rzebLLHERw/oGcPj4UFs9asPa9ob3L+A0LV1Vpvhogv2BugdS5+kjCOrrEaydnLTGQdt5@nongnu.org X-Gm-Message-State: AOJu0YxgqkTC5QLU5FTZgJ3G1IWdip6vEpelK1r01arFBVRqhbCe/o90 m+Hu3vQxFgGX0Ll9TvzX9b/le/CD7uHI1jLAp4dhlGCIH2KMiPj18CjdRavMlsM= X-Google-Smtp-Source: AGHT+IGcm4wAoeiVRTAh/v/bSmxcwTVDPXMFZEHIdbI9BOBLCSP4QpJehj9WHmu22Ars0836ai+vkw== X-Received: by 2002:a5d:4f91:0:b0:37d:45f0:dd08 with SMTP id ffacd0b85a97d-37d551aac31mr7285938f8f.11.1728904959344; Mon, 14 Oct 2024 04:22:39 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:38 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret behavior Date: Mon, 14 Oct 2024 13:22:16 +0200 Message-ID: <20241014112225.90297-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Clément Léger --- target/riscv/op_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 00b6f75102..9d0911f697 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -299,6 +299,9 @@ target_ulong helper_sret(CPURISCVState *env) } mstatus = set_field(mstatus, MSTATUS_SDT, 0); } + if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >= PRV_M) { + mstatus = set_field(mstatus, MSTATUS_MDT, 0); + } if (env->priv_ver >= PRIV_VERSION_1_12_0) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } @@ -375,6 +378,9 @@ target_ulong helper_mret(CPURISCVState *env) if (riscv_cpu_cfg(env)->ext_ssdbltrp) { mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mstatus = set_field(mstatus, MSTATUS_MDT, 0); + } if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) { mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } @@ -416,6 +422,12 @@ target_ulong helper_mnret(CPURISCVState *env) env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + if (prev_priv < PRV_M) { + env->mstatus = set_field(env->mstatus, MSTATUS_MDT, false); + } + } + if (riscv_has_ext(env, RVH) && prev_virt) { riscv_cpu_swap_hypervisor_regs(env); } From patchwork Mon Oct 14 11:22:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13834797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17B2ED16245 for ; Mon, 14 Oct 2024 11:24:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0J9z-0006aq-4e; Mon, 14 Oct 2024 07:22:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0J9w-0006YK-AE for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:44 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0J9u-0002eK-HO for qemu-devel@nongnu.org; Mon, 14 Oct 2024 07:22:44 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-37d47eff9acso2449464f8f.3 for ; Mon, 14 Oct 2024 04:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728904961; x=1729509761; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0jjVOqHYyme7TuTf7cP0qU+WrovStk5IdwfY0O87Bfg=; b=TpleimeFxDfFZpYBGoksyP8y9xG5HRya70/ivnohPtoelFLVlquESknbytmZWWuX6p tucSea1NIx/gzXGk+x6dspa3vrRPv2AgHCBYxFRnBJU3A+Qj1UDo3nMOYSxJunbKmDgq uhqvPlYZF10rrZcCfOq4OTxvAG5hEuSxmGaSTsSu1s6lqlC9fQbiHGdANnAZWpMwQDSM SWKsZUFp9LEhBJO9r/1dk8LaG4v5rzeTP3CqeG9AO1gySIOB8/2dxFn4+XBrCoXCpWxF TgIQIRQ++ZTsWMT/vvsFMaY6wl+tzWxCL51aqT+JIenHwjL4bywftYVGJt8BiMIYu5yU UMqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728904961; x=1729509761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0jjVOqHYyme7TuTf7cP0qU+WrovStk5IdwfY0O87Bfg=; b=sE71x6MaOVOEN2vx8jIHXyPb/DtdHLgrCUCuEbD/BQQn89Fj5Bo4PuYD7K5I1pRUgy CRqaMfbz2ql37zTAwDm8ftsaMWIEVga3yBlKKRnsAeIzsUEceaI+mwQQp4AILVZ+eZYm nswFIPtlaIb9snx8afLLpm5RVBPFQUAeg9bBzoDWb73TTB8M5p7ZLmNeAUiQhmWYC6YC 2VxpH1MvIiV8SFAHE9DqU0F3CD2ueTH8yWpvWSSIGigsFqMoucn7F7tDuDHDhiR5AnII MlVfh6JNYIbpAqsKbqytoSmnpnnP2ItPfvfP1OqNMH9IrwLhQgTSN2fS6BobgRqoUG1g Nw1g== X-Forwarded-Encrypted: i=1; AJvYcCVrGMYvqPKXQ3pOiL7JYHKgStSjVZICssoSPvbZ8NlatPdn+QwTdur5Mm4sNkEVQorUs9ed7fBeIZcq@nongnu.org X-Gm-Message-State: AOJu0YzICOopz8j9WSRI4q2jrLhxlv5PBLipo0G8nPWOswZJMP3bImxq nio0B+51hQWKioiphXIIdfo4s3NrSZRsDrQa+2XBk2x9zh6DxLfhul7EuSbrJRA= X-Google-Smtp-Source: AGHT+IEhB0fsnX6b9YVK+DJ0kLB/v+DmYLq6ZjkIFYA6wjx0kLtx1QnYd3CVEK855WuOjkwTLeUPkA== X-Received: by 2002:a05:6000:b91:b0:37d:47e2:5e30 with SMTP id ffacd0b85a97d-37d5ff6ce3fmr5078588f8f.42.1728904960778; Mon, 14 Oct 2024 04:22:40 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:39 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 7/8] target/riscv: Implement Smdbltrp behavior Date: Mon, 14 Oct 2024 13:22:17 +0200 Message-ID: <20241014112225.90297-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Clément Léger --- target/riscv/cpu_helper.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5173155070..8b44986cd6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1699,6 +1699,17 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env, return xinsn; } +static void riscv_do_nmi(CPURISCVState *env, target_ulong cause, bool virt) +{ + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPV, virt); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP, env->priv); + env->mncause = cause; + env->mnepc = env->pc; + env->pc = env->rnmi_irqvec; + riscv_cpu_set_mode(env, PRV_M, virt); +} + /* * Handle Traps * @@ -1735,15 +1746,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool nmi_execp = false; if (cpu->cfg.ext_smrnmi && env->rnmip && async) { - env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); - env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPV, - env->virt_enabled); - env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP, - env->priv); - env->mncause = cause | ((target_ulong)1U << (TARGET_LONG_BITS - 1)); - env->mnepc = env->pc; - env->pc = env->rnmi_irqvec; - riscv_cpu_set_mode(env, PRV_M, virt); + riscv_do_nmi(env, cause | ((target_ulong)1U << (TARGET_LONG_BITS - 1)), + virt); return; } @@ -1938,6 +1942,19 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s = set_field(s, MSTATUS_MPP, env->priv); s = set_field(s, MSTATUS_MIE, 0); + if (cpu->cfg.ext_smdbltrp) { + if (env->mstatus & MSTATUS_MDT) { + assert(env->priv == PRV_M); + if (!cpu->cfg.ext_smrnmi || nmi_execp) { + cpu_abort(CPU(cpu), "M-mode double trap\n"); + } else { + riscv_do_nmi(env, cause, false); + return; + } + } + + s = set_field(s, MSTATUS_MDT, 1); + } env->mstatus = s; env->mcause = cause | ~(((target_ulong)-1) >> async); if (smode_double_trap) { From patchwork Mon Oct 14 11:22:18 2024 Content-Type: text/plain; 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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d4b6bd382sm11117303f8f.43.2024.10.14.04.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 04:22:41 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v3 8/8] target/riscv: Add Smdbltrp ISA extension enable switch Date: Mon, 14 Oct 2024 13:22:18 +0200 Message-ID: <20241014112225.90297-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241014112225.90297-1-cleger@rivosinc.com> References: <20241014112225.90297-1-cleger@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the switch to enable the Smdbltrp ISA extension. Signed-off-by: Clément Léger --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 53e3bb6b37..6e22bfe37d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), + ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1492,6 +1493,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), + MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),