From patchwork Tue Oct 15 13:56:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 13836486 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 776AD1AF0B6 for ; Tue, 15 Oct 2024 13:56:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729000598; cv=none; b=jjy9CUutGkdLKdNKUy1ECWfQmPxHKseb3Yl5VxCatc/Maug0VGfTp+40RdbJzffPoLPQYb2xbqyQGvwuGm45o5M0+Vs2qfyyuwQOGX1kvkJo/BEBoPuBB6kpmhz6FpDB651ml8FLlCl1N2wG74glZAdDI08PJfnlfAsg7sQCAxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729000598; c=relaxed/simple; bh=i5ddTg9UYKxycz6OdhvhiiZOyT6VwY+Z1+h88aZcdf0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iCHOqV++fI21bgicyPg7RgQiRIP9mFWj1yMHAyU2jswDGmAFR4yozOCDCj7JyrWyaPMi3JMoRYpuwK77FgFO0HssiwizdXo70xzuII5q7V8HRgGS423hOiSzAj7zSnXT8p5UBbnc7m9iRWZpSKOJZTKV4m4h0Ndt1F0kz28rrr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=bkwCbjO2; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="bkwCbjO2" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4311fd48032so29518445e9.0 for ; Tue, 15 Oct 2024 06:56:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729000594; x=1729605394; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=h90tf0LvnuADZLFwaf8lb54SaNEZPrEuE8XroohvsMM=; b=bkwCbjO22u16KPEhUyXuD5Ti6+jDiCI14G213A3xPUH5RSEYU4RdBF5XO47JYPQweJ 4vxHfGP10jmGV9L4kH77d6SnXVIecg+VRRlKXX5Z4x02/N2R0xQ6kBPy8bb8H7Y8ovkP 6/WSpcV436FO4ZEfe995ypH//abPAJOIK9asyyF6h36Ju+6d2lNW8hwb717kAfeXceYL t+iDG7l0/0VS3tNImaPim7XNXh5Jw2QbiiBBPeLJw6rB05mDal72yKkM5PJ7FrfsUHGG zhK9fK/JCOvLqfBbQ5WjmqSV8AOqFMICjvkUuFl1s2J4K0KRPvFB8qmrPbrB6PcPnveI 7U9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729000594; x=1729605394; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h90tf0LvnuADZLFwaf8lb54SaNEZPrEuE8XroohvsMM=; b=YtWwzmZVCMWHs/OELswx9+/tkLH/QTbyyGr4c9YeHSbAGt0vbrPV1xYjRv/+kS+1kA Fi3dlTS8cgruvLmA9OJW3IOeP9gsZDXOf3Cm4gHlt71VvdiDO2rovFBxRAngONvjTvxA MhGh4K7PB0VEh3prE1YMPE88zN3Wq+5QO7M+dHWmAjEIf4Ak1KV5r5rKCxkULuAAFqnb 5DCoqwZJrsLUAi+cONkLgbb7f2VW9aOsljW7kdmTmbCLt9RJLxIJm8Nvhj1GXKBdJ999 a/FTWvCrLOheM5b9WtOgIGxa1y1IrcD64GQ/GxZQkoFNU+SSExa0OadnxVzFjy6RgMjn 8z+A== X-Forwarded-Encrypted: i=1; AJvYcCWUvBn/g+5jK5e9psMDJJ4+8iJC6TCXfqNFtFjZsE0vgcaeEeXyTdXi2BBE7+gZnW7qdXwFCmpnjt4rEg==@vger.kernel.org X-Gm-Message-State: AOJu0YzDB1MbwPPEpjmIrUttj4AGENDRNnl0eAL3xOojnBF13z2bfCAQ 7O7qtVrleMCy+rwZ2+n0AL4heVxRc2gGqLEcj2qhu7YUJC34qglWOOfP9YFoVeg= X-Google-Smtp-Source: AGHT+IHhf+9ITq2oLXri+liuyT6Hpb/e08PVQU+OeunYvA4yXrRxB3L9+6EuNBga9KUv0f7mcCsjBw== X-Received: by 2002:a05:600c:a55:b0:426:5e91:3920 with SMTP id 5b1f17b1804b1-4314a38454cmr5238565e9.29.1729000593672; Tue, 15 Oct 2024 06:56:33 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:33 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:14 +0000 Subject: [PATCH v5 1/8] dt-bindings: iio: adc: ad7606: Remove spi-cpha from required Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-1-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=2087; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=i5ddTg9UYKxycz6OdhvhiiZOyT6VwY+Z1+h88aZcdf0=; b=llTDacqfiNiCfSV52+gxL6/KFEr/5JuV2k/zG3dq92qjaNDLxjZdNcY8PXfrKtsnYXPOlGj9J ACXaSkeJvUyCc2TpHBuXbitb1XHdWP2ebfTQRuoxa50grZfa4nvyjqv X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The documentation is erroneously stating that spi-cpha is required, and the example is erroneously setting both spi-cpol and spi-cpha. According to the datasheet, only cpol should be set. On zedboard for instance, setting the devicetree as in the example will simply not work. Fixes: 416f882c3b40 ("dt-bindings: iio: adc: Migrate AD7606 documentation to yaml") Fixes: 6e33a125df66 ("dt-bindings: iio: adc: Add docs for AD7606 ADC") Reviewed-by: Rob Herring (Arm) Signed-off-by: Guillaume Stols --- Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index bec7cfba52a7..47081c79a1cf 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -39,6 +39,11 @@ properties: "#size-cells": const: 0 + # According to the datasheet, "Data is clocked in from SDI on the falling + # edge of SCLK, while data is clocked out on DOUTA on the rising edge of + # SCLK". Also, even if not stated textually in the datasheet, it is made + # clear on the diagrams that sclk idles at high. Subsequently, in case SPI + # interface is used, the correct way is to only set spi-cpol. spi-cpha: true spi-cpol: true @@ -168,7 +173,6 @@ patternProperties: required: - compatible - reg - - spi-cpha - avcc-supply - vdrive-supply - interrupts @@ -255,7 +259,6 @@ examples: reg = <0>; spi-max-frequency = <1000000>; spi-cpol; - spi-cpha; avcc-supply = <&adc_vref>; vdrive-supply = <&vdd_supply>; @@ -288,7 +291,6 @@ examples: spi-max-frequency = <1000000>; spi-cpol; - spi-cpha; avcc-supply = <&adc_vref>; vdrive-supply = <&vdd_supply>; From patchwork Tue Oct 15 13:56:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 13836487 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528C41AF0C2 for ; Tue, 15 Oct 2024 13:56:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729000599; cv=none; b=CovwHRGTnjQoeRLa+bvs+OwW9OftyumRL5efcPwpNVbiNsNtmRcTHFugzD+05mD41iyDmNB1yHvum0D/mXfzC8cTuOug3lUi+JZmm8hmNrpvNxTcc3GD85IpqFEwV0slXxljA4oNhZpiR9lCThg5c3CxsilAc55LHuVyvvfHClc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729000599; c=relaxed/simple; bh=cnL3eq0CvnDwIBAYvPykYoJ3Fx17pk9WK/iph6l0pIg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ALChx9FYMgSK5VZtxNXUonGiAdgMeEYvp94+KN8kSoae+Jx0RXGyMiPBqwMbhcVm7XL88yDSsu1uG75QfeegLsZm01qyHSE2boiEC9QCIgFfabas8g66r3pT431OAwnFWYsutIHWrAPMX+Q7c7YIcplabq/xPx/alPfYPonaMak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=B5rwtgea; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="B5rwtgea" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4311c285bc9so39461245e9.3 for ; Tue, 15 Oct 2024 06:56:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729000595; x=1729605395; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=55EhiFz0eoHIW1OIthep7nNdg0DTxW/ypPJriA4rZJE=; b=B5rwtgearxZ/TLOBIiBcp81qCEVZGRm2xgfHccIM6cTHH3FpyqlTiHcG34JfAeK9Rm odLsQcxJUSzOtCuNMe5lRUNRwq6rgiZl8qG1LQozPA3VGRTItO34G00wqPrF6X5OE33Q Nz9ZOPnrO6ar8Ou6Low0gXmb0Yo7AxLknkv3+WVTTc71PAq1T4ftsyW9k4aHDYYyuA/X /1QuNG8Qeb+RYbYnra06NDqBionBUSjzWx6IG/j4Xz/LqqXzgwf7Vl3HHw1K8yxGTwW5 HZGKMt9yXWDRaeSOSm3wJ/EZtqgLGkwJLhAThzJYHKnM92NxiQG/axV1I8VCkOu6YxTK PoOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729000595; x=1729605395; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=55EhiFz0eoHIW1OIthep7nNdg0DTxW/ypPJriA4rZJE=; b=S9N8F9RjlN5gqB34cmXP4SzPMuFwQvtV3bDyRHhdVbHJpstuQqT6S8UgPTpAWsBXH1 vRu7fhXzBwwRnVoWi1lIgJfU4VW7WDPEQLNP5/XNFdWP6drP4uP6ADDdHK2m4g46PURb hxbHtdvPbBCQUGFOpa4ejZ0+Jp8glf4d3GjyXqEEQ7DunmIv/V7oJ5hCzC7KL1fwW7Jt vx8xpsptpSLxQz9z2jHFymujmXdLG9RpDCWIgCnDOXo1reiIQXguI557Ed24/I3JAERt dUv+3l6BcCW37SZ6w4D2E/xvcwRhGrNA0b1w/LQsO1oDti0to5SFryKWzyPuDJJzRRfU ls9w== X-Forwarded-Encrypted: i=1; AJvYcCUK1ndiOtbzbcGkrsxgCRt50jMcbqWtC3NsNShL7HveW5w0/kRzpyN8u7KIE4H5G+l1BJlskdhUiPPnAw==@vger.kernel.org X-Gm-Message-State: AOJu0Yz/YN6J2vWEBtEH+NYOL5rYsE6JihMr7XSbzZEewZ6gKdlHECmx O85iOzVDvMAFfne9PAHsBk4C2iAve/HUlRop0pzjFQ+32kVqrPEQIGlA1eIE5mM= X-Google-Smtp-Source: AGHT+IGFMDKNEZfRxjTgqBnidg/6QFPy8mj1gXNoC+c98Fc+Fn4B8+8Oa85J417KHNm+8nmGN9G1/A== X-Received: by 2002:a05:600c:1e07:b0:42c:b7e2:3bc3 with SMTP id 5b1f17b1804b1-4311deec1c6mr140344865e9.19.1729000594442; Tue, 15 Oct 2024 06:56:34 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:34 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:15 +0000 Subject: [PATCH v5 2/8] dt-bindings: iio: adc: ad7606: Add iio backend bindings Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-2-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=3731; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=cnL3eq0CvnDwIBAYvPykYoJ3Fx17pk9WK/iph6l0pIg=; b=PJxGnQFCqsmZCxZJEICUrQtpGVcY7GNVmBguDsX09XW0o1CbFQHwQ6tO6N3Rrw4meySd4x+Kp nUo+B2XDDfSA9jOlj0PMXl1Nl6n0dFhgK/G3KWGFZL+Szc8pCSnqRLb X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Add the required properties for iio-backend support, as well as an example and the conditions to mutually exclude interruption and conversion trigger with iio-backend. The iio-backend's function is to controls the communication, and thus the interruption pin won't be available anymore. As a consequence, the conversion pin must be controlled externally since we will miss information about when every single conversion cycle (i.e conversion + data transfer) ends, hence a PWM is introduced to trigger the conversions. Reviewed-by: Rob Herring (Arm) Signed-off-by: Guillaume Stols --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 64 +++++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 47081c79a1cf..0a612844029a 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -129,6 +129,29 @@ properties: assumed that the pins are hardwired to VDD. type: boolean + pwms: + description: + In case the conversion is triggered by a PWM instead of a GPIO plugged to + the CONVST pin, the PWM must be referenced. + The first is the PWM connected to CONVST or CONVST1 for the chips with the + 2nd PWM connected to CONVST2, if CONVST2 is available and not shorted to + CONVST1. + minItems: 1 + maxItems: 2 + + pwm-names: + items: + - const: convst1 + - const: convst2 + + io-backends: + description: + A reference to the iio-backend, which is responsible handling the BUSY + pin's falling edge and communication. + An example of backend can be found at + http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html + + patternProperties: "^channel@[1-8]$": type: object @@ -175,12 +198,22 @@ required: - reg - avcc-supply - vdrive-supply - - interrupts - - adi,conversion-start-gpios allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# + - oneOf: + - required: + - adi,conversion-start-gpios + - required: + - pwms + + - oneOf: + - required: + - interrupts + - required: + - io-backends + - if: properties: compatible: @@ -222,6 +255,10 @@ allOf: adi,sw-mode: false else: properties: + pwms: + maxItems: 1 + pwm-names: + maxItems: 1 adi,conversion-start-gpios: maxItems: 1 @@ -247,6 +284,29 @@ allOf: unevaluatedProperties: false examples: + - | + #include + iio-backend { + #address-cells = <1>; + #size-cells = <0>; + adi_adc@0 { + compatible = "adi,ad7606b"; + reg = <0>; + pwms = <&axi_pwm_gen 0 0>; + + avcc-supply = <&adc_vref>; + vdrive-supply = <&vdd_supply>; + + reset-gpios = <&gpio0 91 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + adi,range-gpios = <&gpio0 89 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH + &gpio0 87 GPIO_ACTIVE_HIGH + &gpio0 86 GPIO_ACTIVE_HIGH>; + io-backends = <&iio_backend>; + }; + }; + - | #include #include From patchwork Tue Oct 15 13:56:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 13836488 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63BFC1AF0D3 for ; Tue, 15 Oct 2024 13:56:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:34 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:16 +0000 Subject: [PATCH v5 3/8] Documentation: iio: Document ad7606 driver Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-3-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=6859; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=gYRorQljls7gnt12GddZsLRjR3XCK4N21cRs97XBdSo=; b=Oup2lEs68aPov+l9kBPkGocBP+fxR3rFBu8pSGtAEJLWbIMWOT+Kpkk5kuVkBzWEMTWbaAZ0l 5f0/2Ahg83UDGW2sF9wHT3PA6FcSPErEglRPaNC5risPwwgSSN1foNF X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The Analog Devices Inc. AD7606 (and similar chips) are complex ADCs that will benefit from a detailed driver documentation. This documents the current features supported by the driver. Signed-off-by: Guillaume Stols --- Documentation/iio/ad7606.rst | 145 +++++++++++++++++++++++++++++++++++++++++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 147 insertions(+) diff --git a/Documentation/iio/ad7606.rst b/Documentation/iio/ad7606.rst new file mode 100644 index 000000000000..a1173708b489 --- /dev/null +++ b/Documentation/iio/ad7606.rst @@ -0,0 +1,145 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +============= +AD7606 driver +============= + +ADC driver for Analog Devices Inc. AD7606 and similar devices. The module name +is ``ad7606``. + +Supported devices +================= + +The following chips are supported by this driver: + +* `AD7605 `_ +* `AD7606 `_ +* `AD7606B `_ +* `AD7616 `_ + +Supported features +================== + +SPI wiring modes +---------------- + +These ADCs can output data on several SDO lines (1/2/4/8). The driver +currently supports only 1 SDO line. + +Parallel wiring mode +-------------------- + +There is also a parallel interface, with 16 lines (that can be reduced to 8 in +byte mode). The parallel interface is selected by declaring the device as +platform in the device tree (with no io-backends node defined, see below). + +IIO-backend mode +---------------- + +This mode allows to reach the best sample rates, but it requires an external +hardware (eg HDL or APU) to handle the low level communication. +The backend mode is enabled when through the definition of the "io-backends" +property in the device tree. + +The reference configuration for the current implementation of IIO-backend mode +is the HDL reference provided by ADI: +https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl + +This implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM +connected to the conversion trigger pin. + +.. code-block:: + + +---+ +---------------------------- + | | +-------+ |AD76xx + | A | controls | | | + | D |-------------->| PWM |-------------->| cnvst + | 7 | | | | + | 6 | +-------+ | + | 0 | controls +-----------+-----------+ | + | 6 |---------->| | |<--| frstdata + | | | Backend | Backend |<--| busy + | D | | Driver | | | + | R | | | |-->| clk + | I | requests |+---------+| DMA | | + | V |----------->| Buffer ||<---- |<=>| DATA + | E | |+---------+| | | + | R | +-----------+-----------+ | + | |-------------------------------------->| reset/configuration gpios + +---+ +----------------------------- + + +Software and hardware modes +--------------------------- + +While all the AD7606/AD7616 series parts can be configured using GPIOs, some of +them can be configured using register. + +The chips that support software mode have more values available for configuring +the device, as well as more settings, and allow to control the range and +calibration per channel. + +The following settings are available per channel in software mode: + - Scale + +Also, there is a broader choice of oversampling ratios in software mode. + +Conversion triggering +--------------------- + +The conversion can be triggered by two distinct ways: + + - A GPIO is connected to the conversion trigger pin, and this GPIO is controlled + by the driver directly. In this configuration, the driver sets back the + conversion trigger pin to high as soon as it has read all the conversions. + + - An external source is connected to the conversion trigger pin. In the + current implementation, it must be a PWM. In this configuration, the driver + does not control directly the conversion trigger pin. Instead, it can + control the PWM's frequency. This trigger is enabled only for iio-backend. + +Reference voltage +----------------- + +2 possible reference voltage sources are supported: + + - Internal reference (2.5V) + - External reference (2.5V) + +The source is determined by the device tree. If ``refin-supply`` is present, +then the external reference is used, otherwise the internal reference is used. + +Oversampling +------------ + +This family supports oversampling to improve SNR. +In software mode, the following ratios are available: +1 (oversampling disabled)/2/4/8/16/32/64/128/256. + +Unimplemented features +---------------------- + +- 2/4/8 SDO lines +- CRC indication +- Calibration + +Device buffers +============== + +IIO triggered buffer +-------------------- + +This driver supports IIO triggered buffers, with a "built in" trigger, i.e the +trigger is allocated and linked by the driver, and a new conversion is triggered +as soon as the samples are transferred, and a timestamp channel is added to make +up for the potential jitter induced by the delays in the interrupt handling. + +IIO backend buffer +------------------ + +When IIO backend is used, the trigger is not needed, and the sample rate is +considered as stable. There is no timestamp channel. The communication is +delegated to an external logic, called a backend, and the backend's driver +handles the buffer. When this mode is enabled, the driver cannot control the +conversion pin, because the busy pin is bound to the backend. + diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index dfcf9618568a..88bc36326b74 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -21,6 +21,7 @@ Industrial I/O Kernel Drivers ad4000 ad4695 ad7380 + ad7606 ad7944 adis16475 adis16480 diff --git a/MAINTAINERS b/MAINTAINERS index 32719c014888..2793a5765fa8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1572,6 +1572,7 @@ F: Documentation/ABI/testing/sysfs-bus-iio-frequency-adf4350 F: Documentation/devicetree/bindings/iio/*/adi,* F: Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml F: Documentation/devicetree/bindings/iio/adc/lltc,ltc2497.yaml +F: Documentation/iio/ad7606.rst F: drivers/iio/*/ad* F: drivers/iio/adc/ltc249* F: drivers/iio/amplifiers/hmc425a.c From patchwork Tue Oct 15 13:56:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 13836489 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CA141B218C for ; Tue, 15 Oct 2024 13:56:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729000601; cv=none; b=SptqEqh/oHBPgqOVX2c5sitv5Jr09S73u5osyPxlhHy87E/TgjZsBCcfFF3MSiEe/Bf/f9gEff0t4vFTTLZnvL+spZ1HjGiUGrnm6eUuJxFE1jU5FYE/X8TF/FwRyNuxfgjSYJF3ghqbC61S7trpzUprqQljWlwgCr3bIA5xygg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729000601; c=relaxed/simple; bh=bd+nWTyfJcwbii4A58CUizm8w3dMDkWk2+CdLjB+yGU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u3b/tUmtxrDcD/grPb1JtQC5tNtTUXpunn6mTkhZFeMa6YFJ+6s65XJyGZ6Er0qO9vxEUKW1Y+AMejMFBToDgNsywGxvNMPh5eKWsEfVk17f1PcEQ62XbduxFU+cC4EjClarWB+z7D5E3QUVbdJHbA0STQ4qU07gW26z/t5Ilq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Pcxor0aQ; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Pcxor0aQ" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-431160cdbd0so34866145e9.1 for ; Tue, 15 Oct 2024 06:56:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1729000596; x=1729605396; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KKS7B10FNwBsSHhexRWQdA1j1LuMEJVL7bASAbjk2ME=; b=Pcxor0aQVY5bPpHsZ1ObIx7AweYHoaeG+FpF94lg3JBo5ax6nYZNBeShkSlA1I3mCl 6O533/dimHCYRlw7jYBHHnsqwLQ4UO13vIMPPerXMDhfxJlg6FkPnLfYRGmmC15QKfox qxY9DEjhrIOy9FPevprZjvkG+Lu/upv/ne0JRwkcvkiN4NwVKdrsGi1c+Lr1uSA/2KyF IDl3k6AylZxPZtwiVXaiGHPvNyUy0SZ5NIIeKstbhdw65DCvwZXNLSALm4lgOg/0MmBe aN73+Pq4odSwtZmeYCvK4BHTC1nHVXvyEGu74HVbia0PanaX7pDD1UCbD2RAjqFdyssn AQmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729000596; x=1729605396; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KKS7B10FNwBsSHhexRWQdA1j1LuMEJVL7bASAbjk2ME=; b=XVdriwVIulDxzwb/4i64cZIec5qEpWe4qkHHcM85v/UpEZR2E4yZAS62dy4mTHR3zy OrzeQCVTiGDosR6WFpg0j3IUZHHk3wD6gAdXgYtgyPqtVfMhL/WNjRtxBNe21u76U38u PMXo6HZKwSVWSyv9vNjNlahYVxKcgclLWzVbR2AttocGlT9JcItVMRF1AZU8EC70UTel T/7ETjJIszUsPbpm8bWVMv6lcOIhI01KnsN8BhDt8txOZbzM5YWofByx4qGGVNWD3VOT sKDBps0BhUkgFh88CHYEqBdmIQUVKuaTemaUCLLGYIW445Vtwu2Gm/bFF9m7PLkHwgEp GCwA== X-Forwarded-Encrypted: i=1; AJvYcCUb8She5QQK+4EoJgW0sDiO/xQZysmNN0a5sOeCa+JKxNH6EkkSBWXeQKrVdU29F3hdHbBuCBmbj2SV6Q==@vger.kernel.org X-Gm-Message-State: AOJu0Yxe340QvDX12xQ8sUndQqaYYn4wcgmxaZuS5MFt1eh1kysfzNOD 4DBsCG+v7wVzJw/kpUhFJckKUKvKrEbw9dMaRKSF8ZvZaCyG9wD4Lxgv7pHdQjA= X-Google-Smtp-Source: AGHT+IEBRPWh4WaHUL1fzOUqJq2sNAoGnCnbVu5ytpPYpIo+QrCHM8Zr1G2TyYRjysHdnE9r7I7YNQ== X-Received: by 2002:a5d:5103:0:b0:37d:5251:e5ad with SMTP id ffacd0b85a97d-37d862663f8mr589851f8f.2.1729000596040; Tue, 15 Oct 2024 06:56:36 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:35 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:17 +0000 Subject: [PATCH v5 4/8] iio: adc: ad7606: Add PWM support for conversion trigger Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-4-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=8616; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=bd+nWTyfJcwbii4A58CUizm8w3dMDkWk2+CdLjB+yGU=; b=PvXMUBVdGsZy045vMiACl3bL1rju7K2bDU3f4FQ2Q9dsFs5BGOOOeQHqRJKxDvnWZyacO3udq WDfbrDfJoMzC/TbjvV3Z7evxYSlx+PVwOj/nRfHiAiBazkg6aZtlfM0 X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Until now, the conversion were triggered by setting high the GPIO connected to the convst pin. This commit gives the possibility to connect the convst pin to a PWM. Connecting a PWM allows to have a better control on the samplerate, but it must be handled with care, as it is completely decorrelated of the driver's busy pin handling. Hence it is not recommended to be used "as is" but must be exploited in conjunction with IIO backend, and for now only a mock functionality is enabled, i.e PWM never swings, but is used as a GPIO, i.e duty_cycle == period equals high state, duty_cycle == 0 equals low state. This mock functionality will be disabled after the IIO backend usecase is introduced. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 147 ++++++++++++++++++++++++++++++++++++++++++++--- drivers/iio/adc/ad7606.h | 2 + 2 files changed, 142 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 71362eafe838..dd4e0c6fce3e 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -299,6 +301,73 @@ static int ad7606_reg_access(struct iio_dev *indio_dev, } } +static int ad7606_pwm_set_high(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + int ret; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + + ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); + /* sleep 2 µS to let finish the current pulse */ + fsleep(2); + + return ret; +} + +static int ad7606_pwm_set_low(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + int ret; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = 0; + + ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); + /* sleep 2 µS to let finish the current pulse */ + fsleep(2); + + return ret; +} + +static bool ad7606_pwm_is_swinging(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + + return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period && + cnvst_pwm_state.duty_cycle != 0; +} + +static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) +{ + struct pwm_state cnvst_pwm_state; + bool is_swinging = ad7606_pwm_is_swinging(st); + bool is_high; + + if (freq == 0) + return -EINVAL; + + /* Retrieve the previous state. */ + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period; + + cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); + cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL; + if (is_high) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + else if (is_swinging) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; + else + cnvst_pwm_state.duty_cycle = 0; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + static int ad7606_read_samples(struct ad7606_state *st) { unsigned int num = st->chip_info->num_channels - 1; @@ -324,7 +393,13 @@ static irqreturn_t ad7606_trigger_handler(int irq, void *p) error_ret: iio_trigger_notify_done(indio_dev->trig); /* The rising edge of the CONVST signal starts a new conversion. */ - gpiod_set_value(st->gpio_convst, 1); + if (st->gpio_convst) { + gpiod_set_value(st->gpio_convst, 1); + } else { + ret = ad7606_pwm_set_high(st) + if (ret < 0) + dev_err(st->dev, "Could not set PWM to high."); + } return IRQ_HANDLED; } @@ -337,7 +412,13 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, const struct iio_chan_spec *chan; int ret; - gpiod_set_value(st->gpio_convst, 1); + if (st->gpio_convst) { + gpiod_set_value(st->gpio_convst, 1); + } else { + ret = ad7606_pwm_set_high(st); + if (ret < 0) + return ret; + } ret = wait_for_completion_timeout(&st->completion, msecs_to_jiffies(1000)); if (!ret) { @@ -363,6 +444,11 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, } error_ret: + if (!st->gpio_convst) { + ret = ad7606_pwm_set_low(st); + if (ret < 0) + return ret; + } gpiod_set_value(st->gpio_convst, 0); return ret; @@ -662,8 +748,9 @@ static int ad7606_request_gpios(struct ad7606_state *st) { struct device *dev = st->dev; - st->gpio_convst = devm_gpiod_get(dev, "adi,conversion-start", - GPIOD_OUT_LOW); + st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_convst)) return PTR_ERR(st->gpio_convst); @@ -705,14 +792,24 @@ static irqreturn_t ad7606_interrupt(int irq, void *dev_id) { struct iio_dev *indio_dev = dev_id; struct ad7606_state *st = iio_priv(indio_dev); + int ret; if (iio_buffer_enabled(indio_dev)) { - gpiod_set_value(st->gpio_convst, 0); + if (st->gpio_convst) { + gpiod_set_value(st->gpio_convst, 0); + } else { + ret = ad7606_pwm_set_low(st); + if (ret < 0) { + dev_err(st->dev, "PWM set low failed"); + goto done; + } + } iio_trigger_poll_nested(st->trig); } else { complete(&st->completion); } +done: return IRQ_HANDLED; }; @@ -731,7 +828,10 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) { struct ad7606_state *st = iio_priv(indio_dev); - gpiod_set_value(st->gpio_convst, 1); + if (st->gpio_convst) + gpiod_set_value(st->gpio_convst, 1); + else + return ad7606_pwm_set_high(st); return 0; } @@ -740,7 +840,10 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) { struct ad7606_state *st = iio_priv(indio_dev); - gpiod_set_value(st->gpio_convst, 0); + if (st->gpio_convst) + gpiod_set_value(st->gpio_convst, 0); + else + return ad7606_pwm_set_low(st); return 0; } @@ -874,6 +977,11 @@ static int ad7606_chan_scales_setup(struct iio_dev *indio_dev) return 0; } +static void ad7606_pwm_disable(void *data) +{ + pwm_disable(data); +} + int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, const char *name, unsigned int id, const struct ad7606_bus_ops *bops) @@ -950,6 +1058,31 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; + /* If convst pin is not defined, setup PWM. */ + if (!st->gpio_convst) { + st->cnvst_pwm = devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnvst_pwm)) + return PTR_ERR(st->cnvst_pwm); + + /* The PWM is initialized at 1MHz to have a fast enough GPIO emulation. */ + ret = ad7606_set_sampling_freq(st, 1 * MEGA); + if (ret) + return ret; + + ret = ad7606_pwm_set_low(st); + if (ret) + return ret; + + /* + * PWM is not disabled when sampling stops, but instead its duty cycle is set + * to 0% to be sure we have a "low" state. After we unload the driver, let's + * disable the PWM. + */ + ret = devm_add_action_or_reset(dev, ad7606_pwm_disable, + st->cnvst_pwm); + if (ret) + return ret; + } st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, iio_device_id(indio_dev)); diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index fc05a4afa3b8..760cf5e2ecb6 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -115,6 +115,7 @@ struct ad7606_chan_scale { * @bops bus operations (SPI or parallel) * @chan_scales scale configuration for channels * @oversampling oversampling selection + * @cnvst_pwm pointer to the PWM device connected to the cnvst pin * @base_address address from where to read data in parallel operation * @sw_mode_en software mode enabled * @oversampling_avail pointer to the array which stores the available @@ -142,6 +143,7 @@ struct ad7606_state { const struct ad7606_bus_ops *bops; struct ad7606_chan_scale chan_scales[AD760X_MAX_CHANNELS]; unsigned int oversampling; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:36 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:18 +0000 Subject: [PATCH v5 5/8] iio: adc: ad7606: Add compatibility to fw_nodes Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-5-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=20772; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=p5W7C9eFQDZ97zIyZZtTH6VbXAEzZrNsKQ8f3gAiwNE=; b=jEWYPIumcW14EL7S3zdjULrVgwT+Dc6SVyQkhidG17sm5Dsd6l/RZ4m2VS0CBNGPBtjdWTxct F28NtKYqmKaBN77fFNNpXu2JxPV7/B5mxiIS/9Soe3Z4hWNIGk+MsoK X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= On the parallel version, the current implementation is only compatible with id tables and won't work with fw_nodes, this commit intends to fix it. Doing so required to declare ad7606_chip_info structures in the .h file so to make them accessible to all the driver files that can set a pointer to the corresponding chip as the driver data. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 283 ++++++++++++++++++++++++------------------- drivers/iio/adc/ad7606.h | 32 +++-- drivers/iio/adc/ad7606_par.c | 30 +++-- drivers/iio/adc/ad7606_spi.c | 96 +++++++++------ 4 files changed, 254 insertions(+), 187 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index dd4e0c6fce3e..72e0864ba9e4 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -78,6 +78,155 @@ static const unsigned int ad7616_oversampling_avail[8] = { 1, 2, 4, 8, 16, 32, 64, 128, }; +static const struct iio_chan_spec ad7605_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(4), + AD7605_CHANNEL(0), + AD7605_CHANNEL(1), + AD7605_CHANNEL(2), + AD7605_CHANNEL(3), +}; + +static const struct iio_chan_spec ad7606_channels_16bit[] = { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_CHANNEL(0, 16), + AD7606_CHANNEL(1, 16), + AD7606_CHANNEL(2, 16), + AD7606_CHANNEL(3, 16), + AD7606_CHANNEL(4, 16), + AD7606_CHANNEL(5, 16), + AD7606_CHANNEL(6, 16), + AD7606_CHANNEL(7, 16), +}; + +static const struct iio_chan_spec ad7606_channels_18bit[] = { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_CHANNEL(0, 18), + AD7606_CHANNEL(1, 18), + AD7606_CHANNEL(2, 18), + AD7606_CHANNEL(3, 18), + AD7606_CHANNEL(4, 18), + AD7606_CHANNEL(5, 18), + AD7606_CHANNEL(6, 18), + AD7606_CHANNEL(7, 18), +}; + +/* + * The current assumption that this driver makes for AD7616, is that it's + * working in Hardware Mode with Serial, Burst and Sequencer modes activated. + * To activate them, following pins must be pulled high: + * -SER/PAR + * -SEQEN + * And following pins must be pulled low: + * -WR/BURST + * -DB4/SER1W + */ +static const struct iio_chan_spec ad7616_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(16), + AD7606_CHANNEL(0, 16), + AD7606_CHANNEL(1, 16), + AD7606_CHANNEL(2, 16), + AD7606_CHANNEL(3, 16), + AD7606_CHANNEL(4, 16), + AD7606_CHANNEL(5, 16), + AD7606_CHANNEL(6, 16), + AD7606_CHANNEL(7, 16), + AD7606_CHANNEL(8, 16), + AD7606_CHANNEL(9, 16), + AD7606_CHANNEL(10, 16), + AD7606_CHANNEL(11, 16), + AD7606_CHANNEL(12, 16), + AD7606_CHANNEL(13, 16), + AD7606_CHANNEL(14, 16), + AD7606_CHANNEL(15, 16), +}; + +static int ad7606c_18bit_chan_scale_setup(struct ad7606_state *st, + struct iio_chan_spec *chan, int ch); +static int ad7606c_16bit_chan_scale_setup(struct ad7606_state *st, + struct iio_chan_spec *chan, int ch); +static int ad7606_16bit_chan_scale_setup(struct ad7606_state *st, + struct iio_chan_spec *chan, int ch); + +const struct ad7606_chip_info ad7605_4_info = { + .channels = ad7605_channels, + .name = "ad7605-4", + .num_channels = 5, + .scale_setup_cb = ad7606_16bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7605_4_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606_8_info = { + .channels = ad7606_channels_16bit, + .name = "ad7606-8", + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .scale_setup_cb = ad7606_16bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7606_8_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606_6_info = { + .channels = ad7606_channels_16bit, + .name = "ad7606-6", + .num_channels = 7, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .scale_setup_cb = ad7606_16bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7606_6_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606_4_info = { + .channels = ad7606_channels_16bit, + .name = "ad7606-4", + .num_channels = 5, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .scale_setup_cb = ad7606_16bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7606_4_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606b_info = { + .channels = ad7606_channels_16bit, + .name = "ad7606b", + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .scale_setup_cb = ad7606_16bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7606b_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606c_16_info = { + .channels = ad7606_channels_16bit, + .name = "ad7606c16", + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .scale_setup_cb = ad7606c_16bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, IIO_AD7606); + +const struct ad7606_chip_info ad7606c_18_info = { + .channels = ad7606_channels_18bit, + .name = "ad7606c18", + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .scale_setup_cb = ad7606c_18bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, IIO_AD7606); + +const struct ad7606_chip_info ad7616_info = { + .channels = ad7616_channels, + .init_delay_ms = 15, + .name = "ad7616", + .num_channels = 17, + .oversampling_avail = ad7616_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), + .os_req_reset = true, + .scale_setup_cb = ad7606_16bit_chan_scale_setup, +}; +EXPORT_SYMBOL_NS_GPL(ad7616_info, IIO_AD7606); + int ad7606_reset(struct ad7606_state *st) { if (st->gpio_reset) { @@ -622,128 +771,6 @@ static const struct attribute_group ad7606_attribute_group_range = { .attrs = ad7606_attributes_range, }; -static const struct iio_chan_spec ad7605_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(4), - AD7605_CHANNEL(0), - AD7605_CHANNEL(1), - AD7605_CHANNEL(2), - AD7605_CHANNEL(3), -}; - -static const struct iio_chan_spec ad7606_channels_16bit[] = { - IIO_CHAN_SOFT_TIMESTAMP(8), - AD7606_CHANNEL(0, 16), - AD7606_CHANNEL(1, 16), - AD7606_CHANNEL(2, 16), - AD7606_CHANNEL(3, 16), - AD7606_CHANNEL(4, 16), - AD7606_CHANNEL(5, 16), - AD7606_CHANNEL(6, 16), - AD7606_CHANNEL(7, 16), -}; - -static const struct iio_chan_spec ad7606_channels_18bit[] = { - IIO_CHAN_SOFT_TIMESTAMP(8), - AD7606_CHANNEL(0, 18), - AD7606_CHANNEL(1, 18), - AD7606_CHANNEL(2, 18), - AD7606_CHANNEL(3, 18), - AD7606_CHANNEL(4, 18), - AD7606_CHANNEL(5, 18), - AD7606_CHANNEL(6, 18), - AD7606_CHANNEL(7, 18), -}; - -/* - * The current assumption that this driver makes for AD7616, is that it's - * working in Hardware Mode with Serial, Burst and Sequencer modes activated. - * To activate them, following pins must be pulled high: - * -SER/PAR - * -SEQEN - * And following pins must be pulled low: - * -WR/BURST - * -DB4/SER1W - */ -static const struct iio_chan_spec ad7616_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(16), - AD7606_CHANNEL(0, 16), - AD7606_CHANNEL(1, 16), - AD7606_CHANNEL(2, 16), - AD7606_CHANNEL(3, 16), - AD7606_CHANNEL(4, 16), - AD7606_CHANNEL(5, 16), - AD7606_CHANNEL(6, 16), - AD7606_CHANNEL(7, 16), - AD7606_CHANNEL(8, 16), - AD7606_CHANNEL(9, 16), - AD7606_CHANNEL(10, 16), - AD7606_CHANNEL(11, 16), - AD7606_CHANNEL(12, 16), - AD7606_CHANNEL(13, 16), - AD7606_CHANNEL(14, 16), - AD7606_CHANNEL(15, 16), -}; - -static const struct ad7606_chip_info ad7606_chip_info_tbl[] = { - /* More devices added in future */ - [ID_AD7605_4] = { - .channels = ad7605_channels, - .num_channels = 5, - .scale_setup_cb = ad7606_16bit_chan_scale_setup, - }, - [ID_AD7606_8] = { - .channels = ad7606_channels_16bit, - .num_channels = 9, - .scale_setup_cb = ad7606_16bit_chan_scale_setup, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606_6] = { - .channels = ad7606_channels_16bit, - .num_channels = 7, - .scale_setup_cb = ad7606_16bit_chan_scale_setup, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606_4] = { - .channels = ad7606_channels_16bit, - .num_channels = 5, - .scale_setup_cb = ad7606_16bit_chan_scale_setup, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606B] = { - .channels = ad7606_channels_16bit, - .num_channels = 9, - .scale_setup_cb = ad7606_16bit_chan_scale_setup, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606C_16] = { - .channels = ad7606_channels_16bit, - .num_channels = 9, - .scale_setup_cb = ad7606c_16bit_chan_scale_setup, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606C_18] = { - .channels = ad7606_channels_18bit, - .num_channels = 9, - .scale_setup_cb = ad7606c_18bit_chan_scale_setup, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7616] = { - .channels = ad7616_channels, - .num_channels = 17, - .scale_setup_cb = ad7606_16bit_chan_scale_setup, - .oversampling_avail = ad7616_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), - .os_req_reset = true, - .init_delay_ms = 15, - }, -}; - static int ad7606_request_gpios(struct ad7606_state *st) { struct device *dev = st->dev; @@ -922,7 +949,7 @@ static const struct iio_trigger_ops ad7606_trigger_ops = { .validate_device = iio_trigger_validate_own_device, }; -static int ad7606_sw_mode_setup(struct iio_dev *indio_dev, unsigned int id) +static int ad7606_sw_mode_setup(struct iio_dev *indio_dev) { struct ad7606_state *st = iio_priv(indio_dev); @@ -983,7 +1010,7 @@ static void ad7606_pwm_disable(void *data) } int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, - const char *name, unsigned int id, + const struct ad7606_chip_info *chip_info, const struct ad7606_bus_ops *bops) { struct ad7606_state *st; @@ -1008,7 +1035,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, return dev_err_probe(dev, ret, "Failed to enable specified AVcc supply\n"); - st->chip_info = &ad7606_chip_info_tbl[id]; + st->chip_info = chip_info; if (st->chip_info->oversampling_num) { st->oversampling_avail = st->chip_info->oversampling_avail; @@ -1031,7 +1058,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->info = &ad7606_info_no_os_or_range; } indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->name = name; + indio_dev->name = chip_info->name; indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; @@ -1050,7 +1077,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, st->write_scale = ad7606_write_scale_hw; st->write_os = ad7606_write_os_hw; - ret = ad7606_sw_mode_setup(indio_dev, id); + ret = ad7606_sw_mode_setup(indio_dev); if (ret) return ret; @@ -1101,7 +1128,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, NULL, &ad7606_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - name, indio_dev); + chip_info->name, indio_dev); if (ret) return ret; diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 760cf5e2ecb6..d401d3ab37e0 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -69,6 +69,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, /** * struct ad7606_chip_info - chip specific information * @channels: channel specification + * @name device name * @num_channels: number of channels * @scale_setup_cb: callback to setup the scales for each channel * @oversampling_avail pointer to the array which stores the available @@ -80,6 +81,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, */ struct ad7606_chip_info { const struct iio_chan_spec *channels; + const char *name; unsigned int num_channels; ad7606_scale_setup_cb_t scale_setup_cb; const unsigned int *oversampling_avail; @@ -199,22 +201,30 @@ struct ad7606_bus_ops { u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; +/** + * struct ad7606_bus_info - agregate ad7606_chip_info and ad7606_bus_ops + * @chip_info entry in the table of chips that describes this device + * @bops bus operations (SPI or parallel) + */ +struct ad7606_bus_info { + const struct ad7606_chip_info *chip_info; + const struct ad7606_bus_ops *bops; +}; + int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, - const char *name, unsigned int id, + const struct ad7606_chip_info *info, const struct ad7606_bus_ops *bops); int ad7606_reset(struct ad7606_state *st); -enum ad7606_supported_device_ids { - ID_AD7605_4, - ID_AD7606_8, - ID_AD7606_6, - ID_AD7606_4, - ID_AD7606B, - ID_AD7606C_16, - ID_AD7606C_18, - ID_AD7616, -}; +extern const struct ad7606_chip_info ad7605_4_info; +extern const struct ad7606_chip_info ad7606_8_info; +extern const struct ad7606_chip_info ad7606_6_info; +extern const struct ad7606_chip_info ad7606_4_info; +extern const struct ad7606_chip_info ad7606b_info; +extern const struct ad7606_chip_info ad7606c_16_info; +extern const struct ad7606_chip_info ad7606c_18_info; +extern const struct ad7606_chip_info ad7616_info; #ifdef CONFIG_PM_SLEEP extern const struct dev_pm_ops ad7606_pm_ops; diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index d651639c45eb..b87be2f1ca04 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -89,12 +90,20 @@ static const struct ad7606_bus_ops ad7606_par8_bops = { static int ad7606_par_probe(struct platform_device *pdev) { - const struct platform_device_id *id = platform_get_device_id(pdev); + const struct ad7606_chip_info *chip_info; + const struct platform_device_id *id; struct resource *res; void __iomem *addr; resource_size_t remap_size; int irq; + if (dev_fwnode(&pdev->dev)) { + chip_info = device_get_match_data(&pdev->dev); + } else { + id = platform_get_device_id(pdev); + chip_info = (const struct ad7606_chip_info *)id->driver_data; + } + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; @@ -105,26 +114,25 @@ static int ad7606_par_probe(struct platform_device *pdev) remap_size = resource_size(res); - return ad7606_probe(&pdev->dev, irq, addr, - id->name, id->driver_data, + return ad7606_probe(&pdev->dev, irq, addr, chip_info, remap_size > 1 ? &ad7606_par16_bops : &ad7606_par8_bops); } static const struct platform_device_id ad7606_driver_ids[] = { - { .name = "ad7605-4", .driver_data = ID_AD7605_4, }, - { .name = "ad7606-4", .driver_data = ID_AD7606_4, }, - { .name = "ad7606-6", .driver_data = ID_AD7606_6, }, - { .name = "ad7606-8", .driver_data = ID_AD7606_8, }, + { .name = "ad7605-4", .driver_data = (kernel_ulong_t)&ad7605_4_info, }, + { .name = "ad7606-4", .driver_data = (kernel_ulong_t)&ad7606_4_info, }, + { .name = "ad7606-6", .driver_data = (kernel_ulong_t)&ad7606_6_info, }, + { .name = "ad7606-8", .driver_data = (kernel_ulong_t)&ad7606_8_info, }, { } }; MODULE_DEVICE_TABLE(platform, ad7606_driver_ids); static const struct of_device_id ad7606_of_match[] = { - { .compatible = "adi,ad7605-4" }, - { .compatible = "adi,ad7606-4" }, - { .compatible = "adi,ad7606-6" }, - { .compatible = "adi,ad7606-8" }, + { .compatible = "adi,ad7605-4", .data = &ad7605_4_info }, + { .compatible = "adi,ad7606-4", .data = &ad7606_4_info }, + { .compatible = "adi,ad7606-6", .data = &ad7606_6_info }, + { .compatible = "adi,ad7606-8", .data = &ad7606_8_info }, { } }; MODULE_DEVICE_TABLE(of, ad7606_of_match); diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index d12e55123888..44c6031e9e9a 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -334,7 +334,7 @@ static const struct ad7606_bus_ops ad7616_spi_bops = { .sw_mode_config = ad7616_sw_mode_config, }; -static const struct ad7606_bus_ops ad7606B_spi_bops = { +static const struct ad7606_bus_ops ad7606b_spi_bops = { .read_block = ad7606_spi_read_block, .reg_read = ad7606_spi_reg_read, .reg_write = ad7606_spi_reg_write, @@ -352,54 +352,76 @@ static const struct ad7606_bus_ops ad7606c_18_spi_bops = { .sw_mode_config = ad7606c_18_sw_mode_config, }; +static const struct ad7606_bus_info ad7605_4_bus_info = { + .chip_info = &ad7605_4_info, + .bops = &ad7606_spi_bops, +}; + +static const struct ad7606_bus_info ad7606_8_bus_info = { + .chip_info = &ad7606_8_info, + .bops = &ad7606_spi_bops, +}; + +static const struct ad7606_bus_info ad7606_6_bus_info = { + .chip_info = &ad7606_6_info, + .bops = &ad7606_spi_bops, +}; + +static const struct ad7606_bus_info ad7606_4_bus_info = { + .chip_info = &ad7606_4_info, + .bops = &ad7606_spi_bops, +}; + +static const struct ad7606_bus_info ad7606b_bus_info = { + .chip_info = &ad7606b_info, + .bops = &ad7606b_spi_bops, +}; + +static const struct ad7606_bus_info ad7606c_16_bus_info = { + .chip_info = &ad7606c_16_info, + .bops = &ad7606b_spi_bops, +}; + +static const struct ad7606_bus_info ad7606c_18_bus_info = { + .chip_info = &ad7606c_18_info, + .bops = &ad7606c_18_spi_bops, +}; + +static const struct ad7606_bus_info ad7616_bus_info = { + .chip_info = &ad7616_info, + .bops = &ad7616_spi_bops, +}; + static int ad7606_spi_probe(struct spi_device *spi) { - const struct spi_device_id *id = spi_get_device_id(spi); - const struct ad7606_bus_ops *bops; - - switch (id->driver_data) { - case ID_AD7616: - bops = &ad7616_spi_bops; - break; - case ID_AD7606B: - case ID_AD7606C_16: - bops = &ad7606B_spi_bops; - break; - case ID_AD7606C_18: - bops = &ad7606c_18_spi_bops; - break; - default: - bops = &ad7606_spi_bops; - break; - } + const struct ad7606_bus_info *bus_info = spi_get_device_match_data(spi); return ad7606_probe(&spi->dev, spi->irq, NULL, - id->name, id->driver_data, - bops); + bus_info->chip_info, bus_info->bops); } static const struct spi_device_id ad7606_id_table[] = { - { "ad7605-4", ID_AD7605_4 }, - { "ad7606-4", ID_AD7606_4 }, - { "ad7606-6", ID_AD7606_6 }, - { "ad7606-8", ID_AD7606_8 }, - { "ad7606b", ID_AD7606B }, - { "ad7606c-16", ID_AD7606C_16 }, - { "ad7606c-18", ID_AD7606C_18 }, - { "ad7616", ID_AD7616 }, + { "ad7605-4", (kernel_ulong_t)&ad7605_4_bus_info }, + { "ad7606-4", (kernel_ulong_t)&ad7606_4_bus_info }, + { "ad7606-6", (kernel_ulong_t)&ad7606_6_bus_info }, + { "ad7606-8", (kernel_ulong_t)&ad7606_8_bus_info }, + { "ad7606b", (kernel_ulong_t)&ad7606b_bus_info }, + { "ad7606c-16", (kernel_ulong_t)&ad7606c_16_bus_info }, + { "ad7606c-18", (kernel_ulong_t)&ad7606c_18_bus_info }, + { "ad7616", (kernel_ulong_t)&ad7616_bus_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7606_id_table); static const struct of_device_id ad7606_of_match[] = { - { .compatible = "adi,ad7605-4" }, - { .compatible = "adi,ad7606-4" }, - { .compatible = "adi,ad7606-6" }, - { .compatible = "adi,ad7606-8" }, - { .compatible = "adi,ad7606b" }, - { .compatible = "adi,ad7606c-16" }, - { .compatible = "adi,ad7606c-18" }, - { .compatible = "adi,ad7616" }, + { .compatible = "adi,ad7605-4", .data = &ad7605_4_bus_info }, + { .compatible = "adi,ad7606-4", .data = &ad7606_4_bus_info }, + { .compatible = "adi,ad7606-6", .data = &ad7606_6_bus_info }, + { .compatible = "adi,ad7606-8", .data = &ad7606_8_bus_info }, + { .compatible = "adi,ad7606b", .data = &ad7606b_bus_info }, + { .compatible = "adi,ad7606c-16", .data = &ad7606c_16_bus_info }, + { .compatible = "adi,ad7606c-18", .data = &ad7606c_18_bus_info }, + { .compatible = "adi,ad7616", .data = &ad7616_bus_info }, { } }; MODULE_DEVICE_TABLE(of, ad7606_of_match); From patchwork Tue Oct 15 13:56:19 2024 Content-Type: text/plain; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:37 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:19 +0000 Subject: [PATCH v5 6/8] iio: adc: ad7606: Introduce num_adc_channels Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-6-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=4668; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=uZ2pSOh9N6nTo2PEopWYoEeymPnCeCw1H9WWOEjHy2g=; b=pEAYRdFvNOGUcjukNeAiOazcKbbUJKD1EV/IyNMmcyetlet1IX2S25VhmWxsV5eq8ocW407kN aDx558QbhtqDpu5sBbH9q0GtaZBFdXv5XxKm9TsM7Nm4BXqcTkXCfmL X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= This variable determines how many hardware channels has the chip, oppositely to the num_channels that can contain more channels, e.g a timestamp channel in our case. Introducing this variable avoids decreasing the former num_channels variable when reading the ADC's channels, and clarifies a bit the code. Reviewed-by: Nuno Sa Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 10 +++++++++- drivers/iio/adc/ad7606.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 72e0864ba9e4..34d377e9ac79 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -150,6 +150,7 @@ static int ad7606_16bit_chan_scale_setup(struct ad7606_state *st, const struct ad7606_chip_info ad7605_4_info = { .channels = ad7605_channels, .name = "ad7605-4", + .num_adc_channels = 4, .num_channels = 5, .scale_setup_cb = ad7606_16bit_chan_scale_setup, }; @@ -158,6 +159,7 @@ EXPORT_SYMBOL_NS_GPL(ad7605_4_info, IIO_AD7606); const struct ad7606_chip_info ad7606_8_info = { .channels = ad7606_channels_16bit, .name = "ad7606-8", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -168,6 +170,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606_8_info, IIO_AD7606); const struct ad7606_chip_info ad7606_6_info = { .channels = ad7606_channels_16bit, .name = "ad7606-6", + .num_adc_channels = 6, .num_channels = 7, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -178,6 +181,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606_6_info, IIO_AD7606); const struct ad7606_chip_info ad7606_4_info = { .channels = ad7606_channels_16bit, .name = "ad7606-4", + .num_adc_channels = 4, .num_channels = 5, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -188,6 +192,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606_4_info, IIO_AD7606); const struct ad7606_chip_info ad7606b_info = { .channels = ad7606_channels_16bit, .name = "ad7606b", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -198,6 +203,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606b_info, IIO_AD7606); const struct ad7606_chip_info ad7606c_16_info = { .channels = ad7606_channels_16bit, .name = "ad7606c16", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -208,6 +214,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, IIO_AD7606); const struct ad7606_chip_info ad7606c_18_info = { .channels = ad7606_channels_18bit, .name = "ad7606c18", + .num_adc_channels = 8, .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), @@ -219,6 +226,7 @@ const struct ad7606_chip_info ad7616_info = { .channels = ad7616_channels, .init_delay_ms = 15, .name = "ad7616", + .num_adc_channels = 16, .num_channels = 17, .oversampling_avail = ad7616_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), @@ -519,7 +527,7 @@ static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) static int ad7606_read_samples(struct ad7606_state *st) { - unsigned int num = st->chip_info->num_channels - 1; + unsigned int num = st->chip_info->num_adc_channels; return st->bops->read_block(st->dev, num, &st->data); } diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index d401d3ab37e0..b26a11b2eba1 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -71,6 +71,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, * @channels: channel specification * @name device name * @num_channels: number of channels + * @num_adc_channels the number of channels the ADC actually inputs. * @scale_setup_cb: callback to setup the scales for each channel * @oversampling_avail pointer to the array which stores the available * oversampling ratios. @@ -82,6 +83,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, struct ad7606_chip_info { const struct iio_chan_spec *channels; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:38 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:20 +0000 Subject: [PATCH v5 7/8] iio: adc: ad7606: Add iio-backend support Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-7-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=16895; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=knvF5aKMvqbmI6xU45rnHDO+4jl4aWSRuRnTBvrdC14=; b=IOsLO5n2Bydup55KdpPSTpzhpAjfsK8lS+gFZsD4gucoIgzxOmdRrDPTv4Alx/RGsRfxL/Jc8 +hBPimg+o80BqA8eW4I/nvNLMFDAZiuOClkEM4S65ILzEJj6txUOqsQ X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= - Basic support for iio backend. - Supports IIO_CHAN_INFO_SAMP_FREQ R/W. - Only hardware mode is available, and that IIO_CHAN_INFO_RAW is not supported if iio-backend mode is selected. Signed-off-by: Guillaume Stols --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad7606.c | 154 ++++++++++++++++++++++++++++++++++--------- drivers/iio/adc/ad7606.h | 15 +++++ drivers/iio/adc/ad7606_par.c | 92 +++++++++++++++++++++++++- 4 files changed, 231 insertions(+), 32 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 91873f60322d..a57b5f0bc070 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -224,9 +224,11 @@ config AD7606_IFACE_PARALLEL tristate "Analog Devices AD7606 ADC driver with parallel interface support" depends on HAS_IOPORT select AD7606 + select IIO_BACKEND help Say yes here to build parallel interface support for Analog Devices: ad7605-4, ad7606, ad7606-6, ad7606-4 analog to digital converters (ADC). + It also support iio_backended devices for AD7606B. To compile this driver as a module, choose M here: the module will be called ad7606_par. diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 34d377e9ac79..7871552ce5ac 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -191,6 +192,7 @@ EXPORT_SYMBOL_NS_GPL(ad7606_4_info, IIO_AD7606); const struct ad7606_chip_info ad7606b_info = { .channels = ad7606_channels_16bit, + .max_samplerate = 800 * KILO, .name = "ad7606b", .num_adc_channels = 8, .num_channels = 9, @@ -490,6 +492,17 @@ static int ad7606_pwm_set_low(struct ad7606_state *st) return ret; } +static int ad7606_pwm_set_swing(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + static bool ad7606_pwm_is_swinging(struct ad7606_state *st) { struct pwm_state cnvst_pwm_state; @@ -576,11 +589,22 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, if (ret < 0) return ret; } - ret = wait_for_completion_timeout(&st->completion, - msecs_to_jiffies(1000)); - if (!ret) { - ret = -ETIMEDOUT; - goto error_ret; + + /* + * If no backend, wait for the interruption on busy pin, otherwise just add + * a delay to leave time for the data to be available. For now, the latter + * will not happen because IIO_CHAN_INFO_RAW is not supported for the backend. + * TODO: Add support for reading a single value when the backend is used. + */ + if (!st->back) { + ret = wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(1000)); + if (!ret) { + ret = -ETIMEDOUT; + goto error_ret; + } + } else { + fsleep(1); } ret = ad7606_read_samples(st); @@ -620,6 +644,7 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, int ret, ch = 0; struct ad7606_state *st = iio_priv(indio_dev); struct ad7606_chan_scale *cs; + struct pwm_state cnvst_pwm_state; switch (m) { case IIO_CHAN_INFO_RAW: @@ -640,6 +665,14 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: *val = st->oversampling; return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + /* + * TODO: return the real frequency intead of the requested one once + * pwm_get_state_hw comes upstream. + */ + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + *val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); + return IIO_VAL_INT; } return -EINVAL; } @@ -732,6 +765,10 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, return ret; return 0; + case IIO_CHAN_INFO_SAMP_FREQ: + if (val < 0 && val2 != 0) + return -EINVAL; + return ad7606_set_sampling_freq(st, val); default: return -EINVAL; } @@ -914,14 +951,50 @@ static int ad7606_read_avail(struct iio_dev *indio_dev, return -EINVAL; } +static int ad7606_backend_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + return ad7606_pwm_set_swing(st); +} + +static int ad7606_backend_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + return ad7606_pwm_set_low(st); +} + +static int ad7606_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + /* + * The update scan mode is only for iio backend compatible drivers. + * If the specific update_scan_mode is not defined in the bus ops, + * just do nothing and return 0. + */ + if (!st->bops->update_scan_mode) + return 0; + + return st->bops->update_scan_mode(indio_dev, scan_mask); +} + static const struct iio_buffer_setup_ops ad7606_buffer_ops = { .postenable = &ad7606_buffer_postenable, .predisable = &ad7606_buffer_predisable, }; +static const struct iio_buffer_setup_ops ad7606_backend_buffer_ops = { + .postenable = &ad7606_backend_buffer_postenable, + .predisable = &ad7606_backend_buffer_predisable, +}; + static const struct iio_info ad7606_info_no_os_or_range = { .read_raw = &ad7606_read_raw, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os_and_range = { @@ -929,6 +1002,7 @@ static const struct iio_info ad7606_info_os_and_range = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_os_and_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_sw_mode = { @@ -937,6 +1011,7 @@ static const struct iio_info ad7606_info_sw_mode = { .read_avail = &ad7606_read_avail, .debugfs_reg_access = &ad7606_reg_access, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os = { @@ -944,6 +1019,7 @@ static const struct iio_info ad7606_info_os = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_os, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_range = { @@ -951,6 +1027,7 @@ static const struct iio_info ad7606_info_range = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_trigger_ops ad7606_trigger_ops = { @@ -1070,8 +1147,6 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; - init_completion(&st->completion); - ret = ad7606_reset(st); if (ret) dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n"); @@ -1118,34 +1193,51 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; } - st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", - indio_dev->name, - iio_device_id(indio_dev)); - if (!st->trig) - return -ENOMEM; - st->trig->ops = &ad7606_trigger_ops; - iio_trigger_set_drvdata(st->trig, indio_dev); - ret = devm_iio_trigger_register(dev, st->trig); - if (ret) - return ret; + if (st->bops->iio_backend_config) { + /* + * If there is a backend, the PWM should not overpass the maximum sampling + * frequency the chip supports. + */ + ret = ad7606_set_sampling_freq(st, + chip_info->max_samplerate ? : 2 * KILO); + if (ret) + return ret; + + ret = st->bops->iio_backend_config(dev, indio_dev); + if (ret) + return ret; - indio_dev->trig = iio_trigger_get(st->trig); + indio_dev->setup_ops = &ad7606_backend_buffer_ops; + } else { + init_completion(&st->completion); + st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + + st->trig->ops = &ad7606_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret = devm_iio_trigger_register(dev, st->trig); + if (ret) + return ret; - ret = devm_request_threaded_irq(dev, irq, - NULL, - &ad7606_interrupt, - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - chip_info->name, indio_dev); - if (ret) - return ret; + indio_dev->trig = iio_trigger_get(st->trig); - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, - &iio_pollfunc_store_time, - &ad7606_trigger_handler, - &ad7606_buffer_ops); - if (ret) - return ret; + ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + chip_info->name, indio_dev); + if (ret) + return ret; + + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad7606_trigger_handler, + &ad7606_buffer_ops); + if (ret) + return ret; + } return devm_iio_device_register(dev, indio_dev); } diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index b26a11b2eba1..2c629a15cc33 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -61,6 +61,12 @@ #define AD7616_CHANNEL(num) AD7606_SW_CHANNEL(num, 16) +#define AD7606_BI_CHANNEL(num) \ + AD760X_CHANNEL(num, 0, \ + BIT(IIO_CHAN_INFO_SCALE), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 16) + struct ad7606_state; typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, @@ -69,6 +75,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, /** * struct ad7606_chip_info - chip specific information * @channels: channel specification + * @max_samplerate: maximum supported samplerate * @name device name * @num_channels: number of channels * @num_adc_channels the number of channels the ADC actually inputs. @@ -82,6 +89,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct ad7606_state *st, */ struct ad7606_chip_info { const struct iio_chan_spec *channels; + unsigned int max_samplerate; const char *name; unsigned int num_adc_channels; unsigned int num_channels; @@ -152,6 +160,7 @@ struct ad7606_state { bool sw_mode_en; const unsigned int *oversampling_avail; unsigned int num_os_ratios; + struct iio_backend *back; int (*write_scale)(struct iio_dev *indio_dev, int ch, int val); int (*write_os)(struct iio_dev *indio_dev, int val); @@ -180,16 +189,21 @@ struct ad7606_state { /** * struct ad7606_bus_ops - driver bus operations + * @iio_backend_config function pointer for configuring the iio_backend for + * the compatibles that use it * @read_block function pointer for reading blocks of data * @sw_mode_config: pointer to a function which configured the device * for software mode * @reg_read function pointer for reading spi register * @reg_write function pointer for writing spi register * @write_mask function pointer for write spi register with mask + * @update_scan_mode function pointer for handling the calls to iio_info's update_scan + * mode when enabling/disabling channels. * @rd_wr_cmd pointer to the function which calculates the spi address */ struct ad7606_bus_ops { /* more methods added in future? */ + int (*iio_backend_config)(struct device *dev, struct iio_dev *indio_dev); int (*read_block)(struct device *dev, int num, void *data); int (*sw_mode_config)(struct iio_dev *indio_dev); int (*reg_read)(struct ad7606_state *st, unsigned int addr); @@ -200,6 +214,7 @@ struct ad7606_bus_ops { unsigned int addr, unsigned long mask, unsigned int val); + int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *scan_mask); u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index b87be2f1ca04..6946ff00e4cb 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -2,7 +2,8 @@ /* * AD7606 Parallel Interface ADC driver * - * Copyright 2011 Analog Devices Inc. + * Copyright 2011 - 2024 Analog Devices Inc. + * Copyright 2024 BayLibre SAS. */ #include @@ -14,9 +15,82 @@ #include #include +#include #include + #include "ad7606.h" +static const struct iio_chan_spec ad7606b_bi_channels[] = { + AD7606_BI_CHANNEL(0), + AD7606_BI_CHANNEL(1), + AD7606_BI_CHANNEL(2), + AD7606_BI_CHANNEL(3), + AD7606_BI_CHANNEL(4), + AD7606_BI_CHANNEL(5), + AD7606_BI_CHANNEL(6), + AD7606_BI_CHANNEL(7), +}; + +static int ad7606_bi_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) +{ + struct ad7606_state *st = iio_priv(indio_dev); + unsigned int c, ret; + + for (c = 0; c < indio_dev->num_channels; c++) { + if (test_bit(c, scan_mask)) + ret = iio_backend_chan_enable(st->back, c); + else + ret = iio_backend_chan_disable(st->back, c); + if (ret) + return ret; + } + + return 0; +} + +static int ad7606_bi_setup_iio_backend(struct device *dev, struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + unsigned int ret, c; + struct iio_backend_data_fmt data = { + .sign_extend = true, + .enable = true, + }; + + st->back = devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + /* If the device is iio_backend powered the PWM is mandatory */ + if (!st->cnvst_pwm) + return dev_err_probe(st->dev, -EINVAL, + "A PWM is mandatory when using backend.\n"); + + ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret = devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + for (c = 0; c < indio_dev->num_channels; c++) { + ret = iio_backend_data_format_set(st->back, c, &data); + if (ret) + return ret; + } + + indio_dev->channels = ad7606b_bi_channels; + indio_dev->num_channels = 8; + + return 0; +} + +static const struct ad7606_bus_ops ad7606_bi_bops = { + .iio_backend_config = ad7606_bi_setup_iio_backend, + .update_scan_mode = ad7606_bi_update_scan_mode, +}; + static int ad7606_par16_read_block(struct device *dev, int count, void *buf) { @@ -96,9 +170,22 @@ static int ad7606_par_probe(struct platform_device *pdev) void __iomem *addr; resource_size_t remap_size; int irq; + struct iio_backend *back; + /* + * If a firmware node is available (ACPI or DT), platform_device_id is null + * and we must use get_match_data. + */ if (dev_fwnode(&pdev->dev)) { chip_info = device_get_match_data(&pdev->dev); + if (device_property_present(&pdev->dev, "io-backends")) + /* + * If a backend is available ,call the core probe with backend + * bops, otherwise use the former bops. + */ + return ad7606_probe(&pdev->dev, 0, NULL, + chip_info, + &ad7606_bi_bops); } else { id = platform_get_device_id(pdev); chip_info = (const struct ad7606_chip_info *)id->driver_data; @@ -124,6 +211,7 @@ static const struct platform_device_id ad7606_driver_ids[] = { { .name = "ad7606-4", .driver_data = (kernel_ulong_t)&ad7606_4_info, }, { .name = "ad7606-6", .driver_data = (kernel_ulong_t)&ad7606_6_info, }, { .name = "ad7606-8", .driver_data = (kernel_ulong_t)&ad7606_8_info, }, + { .name = "ad7606b", .driver_data = (kernel_ulong_t)&ad7606b_info, }, { } }; MODULE_DEVICE_TABLE(platform, ad7606_driver_ids); @@ -133,6 +221,7 @@ static const struct of_device_id ad7606_of_match[] = { { .compatible = "adi,ad7606-4", .data = &ad7606_4_info }, { .compatible = "adi,ad7606-6", .data = &ad7606_6_info }, { .compatible = "adi,ad7606-8", .data = &ad7606_8_info }, + { .compatible = "adi,ad7606b", .data = &ad7606b_info }, { } }; MODULE_DEVICE_TABLE(of, ad7606_of_match); @@ -152,3 +241,4 @@ MODULE_AUTHOR("Michael Hennerich "); MODULE_DESCRIPTION("Analog Devices AD7606 ADC"); MODULE_LICENSE("GPL v2"); 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4313f56f241sm18848295e9.22.2024.10.15.06.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 06:56:38 -0700 (PDT) From: Guillaume Stols Date: Tue, 15 Oct 2024 13:56:21 +0000 Subject: [PATCH v5 8/8] iio: adc: ad7606: Disable PWM usage for non backend version Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241015-ad7606_add_iio_backend_support-v5-8-654faf1ae08c@baylibre.com> References: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> In-Reply-To: <20241015-ad7606_add_iio_backend_support-v5-0-654faf1ae08c@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, aardelean@baylibre.com, dlechner@baylibre.com, jstephan@baylibre.com, nuno.sa@analog.com, Jonathan Cameron , Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729000592; l=2658; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=8sj2ik6YIhgGPpUYAJWB3DqY/rpxFFg132670LOYgCg=; b=1u2rG+kjJiMqYohGDsnjVlDj3sIi34d9AcBG26SyutZ8VN80TTEQ0g/9rRT0jd/zVf+8HUkLX 24VBapyaxS3BkB8VGn298idC036IGXhLHEHFHfCi9s6y6b7XT1p5QNF X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Since the pwm was introduced before backend, there was a mock use, with a GPIO emulation. Now that iio backend is introduced, the mock use can be removed. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 28 +++++++++------------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 7871552ce5ac..0e830a17fc19 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -470,8 +470,6 @@ static int ad7606_pwm_set_high(struct ad7606_state *st) cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); - /* sleep 2 µS to let finish the current pulse */ - fsleep(2); return ret; } @@ -486,8 +484,6 @@ static int ad7606_pwm_set_low(struct ad7606_state *st) cnvst_pwm_state.duty_cycle = 0; ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); - /* sleep 2 µS to let finish the current pulse */ - fsleep(2); return ret; } @@ -563,13 +559,7 @@ static irqreturn_t ad7606_trigger_handler(int irq, void *p) error_ret: iio_trigger_notify_done(indio_dev->trig); /* The rising edge of the CONVST signal starts a new conversion. */ - if (st->gpio_convst) { - gpiod_set_value(st->gpio_convst, 1); - } else { - ret = ad7606_pwm_set_high(st) - if (ret < 0) - dev_err(st->dev, "Could not set PWM to high."); - } + gpiod_set_value(st->gpio_convst, 1); return IRQ_HANDLED; } @@ -900,10 +890,7 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) { struct ad7606_state *st = iio_priv(indio_dev); - if (st->gpio_convst) - gpiod_set_value(st->gpio_convst, 1); - else - return ad7606_pwm_set_high(st); + gpiod_set_value(st->gpio_convst, 1); return 0; } @@ -912,10 +899,7 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) { struct ad7606_state *st = iio_priv(indio_dev); - if (st->gpio_convst) - gpiod_set_value(st->gpio_convst, 0); - else - return ad7606_pwm_set_low(st); + gpiod_set_value(st->gpio_convst, 0); return 0; } @@ -1210,6 +1194,12 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->setup_ops = &ad7606_backend_buffer_ops; } else { + + /* Reserve the PWM use only for backend (force gpio_convst definition) */ + if (!st->gpio_convst) + return dev_err_probe(dev, -EINVAL, + "No backend, connect convst to a GPIO"); + init_completion(&st->completion); st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,