From patchwork Tue Oct 15 15:44:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1734BD1D879 for ; Tue, 15 Oct 2024 15:45:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jjH-0008Vz-QX; Tue, 15 Oct 2024 11:44:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jjF-0008VT-To for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:44:57 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jjD-0000Tl-AQ for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:44:57 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-20caccadbeeso41621205ad.2 for ; Tue, 15 Oct 2024 08:44:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007093; x=1729611893; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JaR1kDH2Bf+l69hgvZCXqIUYxGHmIwLgfUQ5KPkPEPs=; b=wX2lUx/ss+LkpkiPbceI85npjakfpQo1R1XqIBGReXoIB2cznkF6grostbpUe+K1kH iQeLdnffsbbSC4rCoHITAN6wCA8vV22Nx+xv+V0qBhdVvsTDgy+Pl9AXfjlluV4dHUn+ X5ZbNPDTkttKLl3UtCU2jutimSeMyvsouXwaLUlRwvGW2L2tnjvcwF9fJ1Ceth4xo5Gq oVVmDXYjiQTz6CT/sDaXCl1x+B8dUvhPhpbi2bl9NGH5lGTUkUUBdMXD9RyW4sJATRxW nXI3t9QJRdLCfhmLmigVkiOoZGeMm4vYJEQvUHy/dyPDULKWgFuctXQ/1c6GE6oohOV5 s3VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007093; x=1729611893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JaR1kDH2Bf+l69hgvZCXqIUYxGHmIwLgfUQ5KPkPEPs=; b=Hn1HzAt8NXz4oY4G0C61cd7d/U0oH+xCOhS4xQ5PwXjrVsY09ffmcysJ1Vx4NRFdpH TSdU0S0NNhU0bteLif4gSNhyLCWcqxTaT1aq47gXsuG9ntVuDLPK35IwyV70ns+hN8LD 9yOMk48CXYRJV/0b+g9Pl6HkxjeWGhkUu3VU+8wneBbxxHPq1GLBciH//NTQOgAbyFWK dQqrOqMdxqhyZi5JteZoUxeHTiNpednZTYFM5IH8Yes7FiPQgbjiJ+vOD6WKkfro8PUd 0cO7KvYjuTVyyvzkJHmRzTi/jfK4K6DNn3Hg6GO66u02kVPqLLsTTrw9fuLkhoLaKaf9 8PgA== X-Gm-Message-State: AOJu0YxNv9FWzPwEQX42ZRvdVNiXE4bFc8ACt/8/O3aSLgCyGCVzef2N hfF6TOPBlta+42BCAcdVza3p0hDPxhsXoZN1DusOWPJGUUUhiwV8FbqXM+u334Cno2RAxlEE7Te c X-Google-Smtp-Source: AGHT+IGKcLoA1fzV1i2vd0BYFIhCf5eW8oz28clBDDmuWcA5pYS+J+GtFWNAX2+LyzrmWAwMLgC0aw== X-Received: by 2002:a17:902:d552:b0:20b:7ed8:3978 with SMTP id d9443c01a7336-20ca147e967mr224903405ad.26.1729007093610; Tue, 15 Oct 2024 08:44:53 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d17f828adsm13463945ad.41.2024.10.15.08.44.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:44:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth Subject: [PULL 01/33] qemu/bswap: Undefine CPU_CONVERT() once done Date: Tue, 15 Oct 2024 12:44:10 -0300 Message-ID: <20241015154443.71763-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Better undefined macros once we are done with them, like we do few lines later with DO_STN_LDN_P(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20241003234211.53644-2-philmd@linaro.org> --- include/qemu/bswap.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index ad22910a5d1..b915835bead 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -140,6 +140,8 @@ CPU_CONVERT(le, 16, uint16_t) CPU_CONVERT(le, 32, uint32_t) CPU_CONVERT(le, 64, uint64_t) +#undef CPU_CONVERT + /* * Same as cpu_to_le{16,32,64}, except that gcc will figure the result is * a compile-time constant if you pass in a constant. So this can be From patchwork Tue Oct 15 15:44:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64DDBCFC27C for ; Tue, 15 Oct 2024 15:46:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jjP-00005i-M0; Tue, 15 Oct 2024 11:45:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jjM-00005C-RW for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:05 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jjL-0000VD-9d for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:04 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-20c70abba48so37332185ad.0 for ; Tue, 15 Oct 2024 08:45:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007101; x=1729611901; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rYfx3nszSCCIo154zwSkhn548PKsWfltylmZM2l6IU8=; b=z43i/pXn60a2tXQIizLFQ6uKCtMvWhw3hWFTFKRC9V7hdVB+3IJw9TL0p5k7Hy8+Iz QmzQxE+aDIKCXcS5tp1xwx8VQkmmfxXMULoSZ6vwHGm1Lq5erZUNt3k0JPq02+EGN/9U rY12pT62rVRlrGY0uKehyQvA0vmhKRlCAMAyV4H9TyBMvUlSrZTAr2cX7ZVLCE2XEw/S yc0gOzWxS80GpMP3SBZmoVfvh/KkTt8I2xu5FJ8dRR2TKVmVX5f+1dtfV/2Mn9Q5v/j+ w93uDu5Inf6oYRpnI4xePVHDLVYxk4zjYe44uAs5cpBMWUHEdhmqtBmJUO7RoogQoZbD jeEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007101; x=1729611901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rYfx3nszSCCIo154zwSkhn548PKsWfltylmZM2l6IU8=; b=LknlnCSkevgboPUAg3uTzgmNNBf9FqqyMA3uGRVYpvsbfiSM3bDS79e18BLpsmoXnu nFyvlkak2taitf34ZEkj46jXjUlvf3JX6f6JQWM5I25fAIPQBprJA+Bg2EXywJYSmlNu jNup9U4oKCPqQcORbXOJ6xzqY8yS+oCrwOT0XwHFvZ6/5vL/w6KQBVlHDojbjpfItjc4 oC5DEvPxMy3Bqee6yJ8VoR6Un9eBNwc+I/+SPUeEzg2pMhnTWTv4wzoL1ZHGAE1k6Ma7 jRYebGReSquzTJT3WSxgjBL1SE8yQGs2jNjrMI0cO98l1OmtMLPt1IhITc3qC2Zk2qVp ZVEQ== X-Gm-Message-State: AOJu0Yx40zFIN1XTmSfdqPyhfjUB0sVx6QEkTYDI390ayK8BcSAjh+da vrVcMF3LEhqSWYcK0JNDT3AebwM0wFKb7qX/mT0XK+dDIMaIatlbSCA4/WYaK02OyZxyGugCjnl v X-Google-Smtp-Source: AGHT+IGQfO59wdUy1L+JsGGdLxqtB27G80TOZycY5g2moZMJ+Qools8B9SzvO7sF+CScPDOhFaYOfg== X-Received: by 2002:a17:90a:ff0e:b0:2e2:d3ab:2d77 with SMTP id 98e67ed59e1d1-2e31538f3edmr14405032a91.39.1729007101493; Tue, 15 Oct 2024 08:45:01 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392f753b4sm1940460a91.49.2024.10.15.08.44.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Richard Henderson Subject: [PULL 02/33] exec/tswap: Massage target_needs_bswap() definition Date: Tue, 15 Oct 2024 12:44:11 -0300 Message-ID: <20241015154443.71763-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Invert target_needs_bswap() comparison to match the COMPILING_PER_TARGET definition (2 lines upper). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-Id: <20241010175246.15779-2-philmd@linaro.org> --- include/exec/tswap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/tswap.h b/include/exec/tswap.h index b7a41913475..ecd4faef015 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -28,7 +28,7 @@ bool target_words_bigendian(void); #ifdef COMPILING_PER_TARGET #define target_needs_bswap() (HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN) #else -#define target_needs_bswap() (target_words_bigendian() != HOST_BIG_ENDIAN) +#define target_needs_bswap() (HOST_BIG_ENDIAN != target_words_bigendian()) #endif /* COMPILING_PER_TARGET */ static inline uint16_t tswap16(uint16_t s) From patchwork Tue Oct 15 15:44:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7ADADCFC27C for ; Tue, 15 Oct 2024 15:45:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jjV-00008v-15; Tue, 15 Oct 2024 11:45:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jjT-00006l-Db for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:11 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jjS-0000hp-1m for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:11 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2e06acff261so3678285a91.2 for ; Tue, 15 Oct 2024 08:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007108; x=1729611908; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OHZo240/MKAErrBWgP22VqVce6gGXpeJw8VH+45Ycx8=; b=bF5XwocGiiIMkaND/mOr78bBQnuvMgxcoT/khKVInmDBm+XhH/zJ9n/1DPaaNz1JFN XTarrBCL67lA0Z+nX743vN7onYTdsdxdqbpd0OjPLsXv75s8Bo6Zp2iizUIr7o4+2PlD 7PClDzBRsIQ/loXeqGjHScaIFBJQwzkFkagt4lsH2M6QiL47S6KYnPuc9eD3NzheM11M /cDMAO0MZba8qYs1W//fxaZ7AMVmVJrEw78yitFEucmctujLWUOIULGqWrUrgo9vybNP Gl/8DYztW/9oRB1TgglXN9q/pLBSZhuIV60vVOoNPZb8//PgYRjltmPV+ya0BSSR0XpO QAYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007108; x=1729611908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OHZo240/MKAErrBWgP22VqVce6gGXpeJw8VH+45Ycx8=; b=rn9cUZ5tWmiK+hmxDGTc1+vyyF856DW8JsCq8haXc7vswpDz85GIO9l2JCZnbWtVO6 E9Y7Zw1nS3TeLYWCQHTvrls4Z3QzOsORNn2Mz015y+FzwUqGA9FPHg0bD2tUkROiv8Ds UrSzOUF3Gy1sgLNiPj4AOq0XU5QK8CIBH94rfIRYw+BoscCuemhKeqCw8uQLzcp2juAc h6gnbS13OpE2YxhyZ9wdQsD7LiRYLBCJrk6fryRcqecXXMEna90KsUHLL9KRlgXSezS9 9girt8w+Rz6Sw5y0h3VepXFF9nExt2QPyyGWJgNmDR9kcag7JpdTqdrhukBZlxmnN8f8 UgZQ== X-Gm-Message-State: AOJu0Yy1D6Ueu1SddwRxab69CuoLPtm4MXlfKg+WrJj2NyZ4XZRC5OmB 7LxdX5eoGH4oQNXlEvI1ljZbwzKQPmAJioFOepcdtSSrYB2eSn9odUa0+HKPVe0FnDZnzUtaOzb T X-Google-Smtp-Source: AGHT+IGXlQoL40ZaflYaRzMdlDI5rCeFVNJtXlZbSR7n5Hkr4o1y9AewTgLOHp9SmfkesWAE9VDWEQ== X-Received: by 2002:a17:90a:2d8e:b0:2e2:b513:fdca with SMTP id 98e67ed59e1d1-2e3ab820d96mr747060a91.20.1729007108327; Tue, 15 Oct 2024 08:45:08 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392ed396asm1971278a91.21.2024.10.15.08.45.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth Subject: [PULL 03/33] exec/memop: Remove unused memop_big_endian() helper Date: Tue, 15 Oct 2024 12:44:12 -0300 Message-ID: <20241015154443.71763-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=philmd@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Last use of memop_big_endian() was removed in commit 592134617c9 ("accel/tcg: Reorg system mode store helpers"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20241003234211.53644-3-philmd@linaro.org> --- include/exec/memop.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index b699bf76886..acdb40a9b3b 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -164,12 +164,6 @@ static inline MemOp size_memop(unsigned size) return (MemOp)ctz32(size); } -/* Big endianness from MemOp. */ -static inline bool memop_big_endian(MemOp op) -{ - return (op & MO_BSWAP) == MO_BE; -} - /** * memop_alignment_bits: * @memop: MemOp value From patchwork Tue Oct 15 15:44:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B68B4D1D879 for ; Tue, 15 Oct 2024 15:46:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jjc-0000I3-Kw; Tue, 15 Oct 2024 11:45:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jja-0000GE-LE for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:18 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jjY-0000j3-Qw for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:18 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2e188185365so4282474a91.1 for ; Tue, 15 Oct 2024 08:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007115; x=1729611915; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9XkclaxhDgiPYIH/QNOgI/sKQUHpGlRZU54F7qGZHXg=; b=b1HFCV3dpbcWQHKDfoaQerhWKsjbNAz2yYuNe/6MDoeoM24kBvL+x0QPOnFVqYtGUO IOC9HCU7UmKarGsgggoGtLD4VPuXv3RB6qoD9zWTQCHtEh372/5gz+TMEynQTZNaL9X5 A9YcByNUP5PB4iTFrhWfjVR0gjtV/CO0iwurFzeGJPXsYcWDOx1RM341bGSw3/vFxQnq n/N+CmmRuBOBTONqF6YG7eYjNkm46gg6fenXK4WgLERJzalE1DB2a/dkRb2hOwA+lEV8 Y0ndYCuJEjSIJnhI+wa+Gol0+M6DX5+fj4/BfEzCbb17CIXi2zG3H6WV/3leeWzP3v8F xMjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007115; x=1729611915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9XkclaxhDgiPYIH/QNOgI/sKQUHpGlRZU54F7qGZHXg=; b=rvlKo/74R8KrK2BQN90SNx5SrPR7grNx9v3dVVf7wSYHVjGHOtYs7FCD8JXg+2nekV PGwUuu4Y1H7lDScsv71KPFyfmOyy7wEHEWTUYPadcpO71OMkjhiZcK7TGwnZfNUSaOpZ u7V+6Sxr9IXAsC20KAUo5WX0Tp+DVJtIsHlQGJJ9eWfq+oWsr3vt7ok9tVvun0FpXarm HIq/f0G1rzDi0PFEojzd568aLcsLn42Imi4nntZY41xYU4iieFjlCkeZ9gGJYFow76Uc R1D9iK6tcxkkDsgyHAWsEmoBlw7pR7UY2Yp0XSj35bR+exkhXs2pTWYYFObvc/1YVLxa 9Vjw== X-Gm-Message-State: AOJu0Yym6vb8WaLTwWHDP6i/1nBMq36FCf7BreRAbuDY0tpvea+GgdiE Idh9EkmsS3Zr8iQk0rh5fh5XRvKLSZ3BecF0j22hEA1RF+FnMeKcNqaXFOimJXh2lOkjJHRwLdB 6 X-Google-Smtp-Source: AGHT+IFH7SQ2Jwfjk7m/lYRL9wsdXQWI6YTxXSa9KDKC26f3L9q3siWb5i0gHJHk2IfhXAp34dPCPQ== X-Received: by 2002:a17:90b:2242:b0:2e2:e743:7501 with SMTP id 98e67ed59e1d1-2e2f0a52ef5mr15627861a91.8.1729007115158; Tue, 15 Oct 2024 08:45:15 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392f60480sm1957290a91.40.2024.10.15.08.45.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 04/33] target/hexagon: Replace ldtul_p() -> ldl_p() Date: Tue, 15 Oct 2024 12:44:13 -0300 Message-ID: <20241015154443.71763-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=philmd@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Hexagon target is only built for 32-bit. Using ldtul_p() is pointless, replace by ldl_p(). Mechanical change doing: $ sed -i -e 's/ldtul_p/ldl_p/' \ $(git grep -wl ldtul_p target/hexagon/) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-3-philmd@linaro.org> --- target/hexagon/gdbstub.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 94e1db8ef8d..557b3029785 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -52,7 +52,7 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUHexagonState *env = cpu_env(cs); if (n == HEX_REG_P3_0_ALIASED) { - uint32_t p3_0 = ldtul_p(mem_buf); + uint32_t p3_0 = ldl_p(mem_buf); for (int i = 0; i < NUM_PREGS; i++) { env->pred[i] = extract32(p3_0, i * 8, 8); } @@ -60,14 +60,14 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } if (n < TOTAL_PER_THREAD_REGS) { - env->gpr[n] = ldtul_p(mem_buf); + env->gpr[n] = ldl_p(mem_buf); return sizeof(target_ulong); } n -= TOTAL_PER_THREAD_REGS; if (n < NUM_PREGS) { - env->pred[n] = ldtul_p(mem_buf) & 0xff; + env->pred[n] = ldl_p(mem_buf) & 0xff; return sizeof(uint8_t); } @@ -117,7 +117,7 @@ static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { - env->VRegs[n].uw[i] = ldtul_p(mem_buf); + env->VRegs[n].uw[i] = ldl_p(mem_buf); mem_buf += 4; } return MAX_VEC_SIZE_BYTES; @@ -127,7 +127,7 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { - env->QRegs[n].uw[i] = ldtul_p(mem_buf); + env->QRegs[n].uw[i] = ldl_p(mem_buf); mem_buf += 4; } return MAX_VEC_SIZE_BYTES / 8; From patchwork Tue Oct 15 15:44:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D1B8D1D879 for ; Tue, 15 Oct 2024 15:45:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jjk-0000Pf-2r; Tue, 15 Oct 2024 11:45:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jjh-0000Jl-MP for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:26 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jjf-0000jQ-SR for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:25 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2e2e050b1c3so3457605a91.0 for ; Tue, 15 Oct 2024 08:45:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007122; x=1729611922; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qKnzIyfB55jcDJiuOhbkwT1go1+QVX88i2HpqTUCIA8=; b=xhVdIf+nz21MyhAwPReP3N7C+ruQfpA0aw0y/6tWfVTaULFQNuSyKq20b5PX2xJKDh xBa6n8eQoy03NIIDOswLmT8gL8LST2lVDcHghrK/579a3cKLE+EKsOKQGL+k4UyhRpv8 2EH2s07pgsYHpT9VksPBBsTgaIrFzwhd6SFjPO5IxFrOchU25Bd5hoIyP6oYDCM5Ypks 3E2zwvEy62zihuCUmvBYnf/6bvV8BTkbvA0kXEW+rGtp6mIQPD6enhm5an3fawF3/Fq3 NJh4+vujelWYr0bZkXqLpevh5FjtwBTbRkOUEA74oXShJpXV7mSG0/52si3qsVoCnizh AkLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007122; x=1729611922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qKnzIyfB55jcDJiuOhbkwT1go1+QVX88i2HpqTUCIA8=; b=fZkOZJXtUHIx3AIH5VSw6aX6E0yq00DJXlBBjL/2y3t7dvrA93VCIrH2/0w2jFTZ9a ZMgmpp74MijUDJWPbOdn6MekBBGXXyJqK+YklI0phGZsmnTpkpbntnoGVxASIIBAkwvm MNs2ewpa9TWL0pm2rGfXJG1lp20fieSK01AixcPh8GWYTiyU2PebBArxYLkgkod30s9K kv88bEGxzl4Z2XG4zTYIZ7bO+PiJbB8T1LutbwuCs722BkyAZFBqGXaUo97YuDbPZ9jG 5PjpOt0KVKsLfb0myD7z59upxSVm00I24gSjGP9k0W39ykEHlpOShw0/Naxs4T4/vPdg N5Gg== X-Gm-Message-State: AOJu0Yz7ftu1mtU5oqsdinU2DZ4Sqra3sP65gxhu67j4dt6dqoWenasp 1i4F3J3f663sGeWSly4kr6EAG6VYQJxI92egNIib+1BCfVvRV8QGyEVBtx3OxgpeGXykWWvCNdl w X-Google-Smtp-Source: AGHT+IGXlXTobLjjFWgdi6VRhIDkgkA7Psdgd5HHHIfzpXR/cCIx/+Em5ScixYF3lJpVVNM0HPsNVw== X-Received: by 2002:a17:90a:3041:b0:2e0:8780:ecb with SMTP id 98e67ed59e1d1-2e2f0af2eaamr22888742a91.12.1729007122017; Tue, 15 Oct 2024 08:45:22 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392f5f7f7sm1941754a91.37.2024.10.15.08.45.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 05/33] target/alpha: Replace ldtul_p() -> ldq_p() Date: Tue, 15 Oct 2024 12:44:14 -0300 Message-ID: <20241015154443.71763-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=philmd@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Alpha target is only built for 64-bit. Using ldtul_p() is pointless, replace by ldq_p(). Mechanical change doing: $ sed -i -e 's/ldtul_p/ldq_p/' $(git grep -wl ldtul_p target/alpha/) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-4-philmd@linaro.org> --- target/alpha/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 13694fd321e..bf5091c2a6e 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -59,7 +59,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { CPUAlphaState *env = cpu_env(cs); - target_ulong tmp = ldtul_p(mem_buf); + target_ulong tmp = ldq_p(mem_buf); CPU_DoubleU d; switch (n) { From patchwork Tue Oct 15 15:44:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF204D1D87B for ; Tue, 15 Oct 2024 15:46:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jko-0001QQ-L0; Tue, 15 Oct 2024 11:46:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jjp-0000VM-J8 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:47 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jjm-0000kl-Qp for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:33 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-71e5827d6a7so2250022b3a.3 for ; Tue, 15 Oct 2024 08:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007129; x=1729611929; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fL2u07Qpq8qO+o5N1onMiU4q/NHO95fnaXoDim7+gRk=; b=fRgP2658NKvQqjuzZQDLtaEjqGp2YYDC51WJUdjAylu74evmIu4u92sCbbp1xZBKpG 3j4LR1uWiVjM9VGyQ1JFGCaHylhbYmMdEv2+kthEAlJW2wFWEcIgo7XhUZWsNpUcQh6F wzzW/azf85T1WYm6ZFOSXZhPyCbBHUjc4UFmd7vwfcLHkeLEvhkjmxX8T6ThWoo3tjHc /VgF5I/wL+kPWXLdKrx/Y/fJWD0UPIxigrj5HanjP7tcYVrrz9AI81ftT+aiu80YDBIq c71gjCNXEHc+VAcfRv6igZFzY//eIIGAFSdotdccHkCOcb/MLVwAHz4Pe/fuV8LFVHQJ IfUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007129; x=1729611929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fL2u07Qpq8qO+o5N1onMiU4q/NHO95fnaXoDim7+gRk=; b=t3NH7WJNSAUf43p7J9FIZxEPYBev+rqw6r+Pu2OttaCD34Y+2UwUMrOuOB3DDgFmiA GMGocVKWAFiSxD5CDouqZFswc1C1MXY3Ph/e6y82VCwKoF2QPBiwMH7NIwcrgMQy8qXO 002oFLE1ursRnWTDnpSHxIDFfMYaEm7TJH630Vql4/+TgvywHtIAC+/aylIk1Yj0uMcA iEIWw2RdvUEmgRqG4z8Ej0R1C8i6jEbkD0qKl4FS36yXnI9jD2CqgA2oJ2rbswWYRzKg 22Wni6VjtKBqU31RF5QJpmdN1ePmfXT+Xw3lsn/wp85Ucpot8j8XGJ+CMJKqWl0/zeoM gjYw== X-Gm-Message-State: AOJu0YyYurdL5aWiNFYr1vOivke00YyulOR01ORb8zP2BoftC9jHYRTo ubHWdVd6GJvD6DUF4NUeDBeW/H69F4pNKYn9UYubixNF0uhO0lv7f2bBEmcOcN+dU44aTwqBlrw w X-Google-Smtp-Source: AGHT+IFVB96zyIMaueeFm3yc+C5/3k/fnCEzDheT0JHm3UDRnymURMXvutSjmKpOd3ML3Ir2D1JE4Q== X-Received: by 2002:a05:6a21:1789:b0:1c4:9f31:ac9e with SMTP id adf61e73a8af0-1d8bcfc21f5mr22118453637.42.1729007129251; Tue, 15 Oct 2024 08:45:29 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392f72108sm1942941a91.47.2024.10.15.08.45.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Subject: [PULL 06/33] gdbstub/helpers: Introduce ldtul_$endian_p() helpers Date: Tue, 15 Oct 2024 12:44:15 -0300 Message-ID: <20241015154443.71763-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce ldtul_le_p() and ldtul_be_p() to use directly in place of ldtul_p() when a target endianness is fixed. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Acked-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20241010175246.15779-3-philmd@linaro.org> --- include/gdbstub/helpers.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h index 26140ef1ac0..6f7cc48adcb 100644 --- a/include/gdbstub/helpers.h +++ b/include/gdbstub/helpers.h @@ -95,9 +95,13 @@ static inline uint8_t *gdb_get_reg_ptr(GByteArray *buf, int len) #if TARGET_LONG_BITS == 64 #define gdb_get_regl(buf, val) gdb_get_reg64(buf, val) #define ldtul_p(addr) ldq_p(addr) +#define ldtul_le_p(addr) ldq_le_p(addr) +#define ldtul_be_p(addr) ldq_be_p(addr) #else #define gdb_get_regl(buf, val) gdb_get_reg32(buf, val) #define ldtul_p(addr) ldl_p(addr) +#define ldtul_le_p(addr) ldl_le_p(addr) +#define ldtul_be_p(addr) ldl_be_p(addr) #endif #endif /* _GDBSTUB_HELPERS_H_ */ From patchwork Tue Oct 15 15:44:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79BE9D1D879 for ; Tue, 15 Oct 2024 15:46:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jkc-00012G-HR; Tue, 15 Oct 2024 11:46:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jjw-0000ZI-Ql for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:47 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jju-0000lj-PA for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:40 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2e18293a5efso3805787a91.3 for ; Tue, 15 Oct 2024 08:45:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007136; x=1729611936; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QllJIAKdtcEv9cjfy79RaL0PjX8KiZ5Hky2rfsQ2CVs=; b=jRo+660Fcc4T94JesVWlyrX0qHX9aSlKg+7M+Kog27MRgXebx3AahZ4mzSROR1X9/a +B1yHpbfO6OF2bli1mO0ZEMyxLu6PNkBZbNiIUoczWN2Kex9h75v6s/EDeGVuG34RP0L WxAVns0QPMyeOCp4IxrTy+a1rmjWOY2OdXSKM41KIcWYzaZVrP0HEbUMiKeezP+IIDWY 0jBBijD6ICdEtU4I8QzDaCAiQqeEk7EG8+Vq9zKUwdBCzOk1ERWIyYEUUzIupmKRqTvb 5CWdzsu+BU/SarYCAXXJqkARqWc+HjTzyvMDAnVwfJvPd87u9hCuUJjHFdaa3kCM7Cky 1DRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007136; x=1729611936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QllJIAKdtcEv9cjfy79RaL0PjX8KiZ5Hky2rfsQ2CVs=; b=m/AKkCPcpkVVOEp/id4u4WVDauRSI4gqybmZfECGR7K5Fh7PNCEtF5dO4S/RxElhDv 7t9Altd7G9RG/dnIh6/sgMqNTprg7dwshmJDjUtR6e4lt9i+3UnEMOWNVNMvrl/d0uBz +nl6cYRKBUpS+iypSmw3JabaoaEjX7DfT9DvP6AK1WN27JqvTPvHN6zoNC8S/cNlq7Fq 2Jrv8lKnkBiwwF71/wzzqkiek6gwO8/onvNQ5WxGdJ7Zu0/P9rFFkZJ8XdXlaYVKD1RP 2RA5bGqTFBxBH5Zrnk91KPVfMsywKEiwMbPuyEldmyG6kTm0PpdlR1pDlVOTw/CBXEFv 2iOw== X-Gm-Message-State: AOJu0Yxl/T20rklenr7g6OE+x3m8xNzR5mQbH0IC7UV+l90unLu3wysf 3hPTG4NgMajHV04s0X5VOyzyu3DHxZhQORg7cZeY9CvBYZ8U+isg4w4dOak1CoOCwjfWNG9+yMu j X-Google-Smtp-Source: AGHT+IGoiM3T7PO4dBDPTAumqjeRvoJ/C3ysODdyeGfz8ofQdxoecEGHWQH5+MR87b5qgCo6YVKk1g== X-Received: by 2002:a17:90b:4a46:b0:2e2:bf7f:3369 with SMTP id 98e67ed59e1d1-2e3ab7c7935mr738147a91.5.1729007136172; Tue, 15 Oct 2024 08:45:36 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392e8e40dsm1961107a91.3.2024.10.15.08.45.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 07/33] target/alpha: Use explicit little-endian LD/ST API Date: Tue, 15 Oct 2024 12:44:16 -0300 Message-ID: <20241015154443.71763-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=philmd@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Alpha architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/alpha/); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-7-philmd@linaro.org> --- target/alpha/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index bf5091c2a6e..1a7e2dd9202 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -59,7 +59,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { CPUAlphaState *env = cpu_env(cs); - target_ulong tmp = ldq_p(mem_buf); + target_ulong tmp = ldq_le_p(mem_buf); CPU_DoubleU d; switch (n) { From patchwork Tue Oct 15 15:44:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 829C6D1D87B for ; Tue, 15 Oct 2024 15:48:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jkt-0001oI-9r; Tue, 15 Oct 2024 11:46:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jk3-0000gl-Ve for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:53 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jk1-0000mE-5f for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:47 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-207115e3056so45657745ad.2 for ; Tue, 15 Oct 2024 08:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007143; x=1729611943; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Tb1VVkfaxmHhJ+SeH6xxxqxEejCKf+mIQBUt9d+dxc=; b=oZRiD7ZOco4hqegh9q57m3e+tEHsWEEHcrv+ZYw7vveCPX84D0s2ifC8QD/yoBMtzE EfJtDQTSwLUs1OA3P1GNUKBhBBqeT8mK8VS1UPuUZw5Mi/bWwmU0DjNF6NpQwJWKsTQV F2kj2xlcJF31BOmsATI0GoH6ggJOo5kol0/6B/Q5USt5VAIq8061T/Dt+72P0K2w5lj3 0At/EupgzMQL5fsr9cuvG6vDdMTnAV0ucvDSQ0Y0tyIeAeZ0uOWp42Rv+kpELy93AxxV GA3Iu8JCXu3iQajX/3+BXx7tkU7ilpkHi2R+bF2tMULJmE5919MUEwOnloYPFQElzJnX Ax9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007143; x=1729611943; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Tb1VVkfaxmHhJ+SeH6xxxqxEejCKf+mIQBUt9d+dxc=; b=G2j6WRg5FBPexElJ2zmCU9zJ9KlSMrSIlyqwMj8ca9LztcXZB/tRorz25MykPT7sZ1 fiI1hS2x4GKcHZJ35z1GbUmwf3sLuiB22ZzuNhFH5ZeyD88DJdcohduLBRcUYEmaDvsc qtYESL2Lxx59C736eor4owRXIH189IYCZAf2qPjB1N/TJHfW8sukSHlbfmAhDlTZUVYf X1m3wXCyUScJN/9CpWdf/RHSJj+bBZczsm5VDfmdFqK5FjM+IRbVfYOIteJDzR/TZK1z oFlO3GCKW/g+rHhiYh88U4IeVBQSZ5s3pSPSdZbtbsvOtwZ8PN+uJ5Vr7YKM49Yc526C 1gcQ== X-Gm-Message-State: AOJu0Yzpo6HqTrpH5wwxQfgLlJQeFwElhUidiSwrflLBI71mcQnj+0PD 4Zdcuscx5xi2DI7EGiBuMxFNt2xWgMINNjBmsQcmefybQhBqIQ9CcgO+fris+JS+wQJCr96FXho R X-Google-Smtp-Source: AGHT+IGoJGc7Q5yk3RZ6evJdmqlw5meICqDdRbnm10rTD7MVvrMLmxZfe7wHvJ5bK9vpf7E03pKpjw== X-Received: by 2002:a17:90a:3ea7:b0:2e2:d197:40f3 with SMTP id 98e67ed59e1d1-2e3ab8e7b46mr685667a91.35.1729007143046; Tue, 15 Oct 2024 08:45:43 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392ed3704sm1985536a91.20.2024.10.15.08.45.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 08/33] target/hexagon: Use explicit little-endian LD/ST API Date: Tue, 15 Oct 2024 12:44:17 -0300 Message-ID: <20241015154443.71763-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Hexagon architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/hexagon/); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-8-philmd@linaro.org> --- target/hexagon/gdbstub.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 557b3029785..12d6b3bbcbb 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -52,7 +52,7 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUHexagonState *env = cpu_env(cs); if (n == HEX_REG_P3_0_ALIASED) { - uint32_t p3_0 = ldl_p(mem_buf); + uint32_t p3_0 = ldl_le_p(mem_buf); for (int i = 0; i < NUM_PREGS; i++) { env->pred[i] = extract32(p3_0, i * 8, 8); } @@ -60,14 +60,14 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } if (n < TOTAL_PER_THREAD_REGS) { - env->gpr[n] = ldl_p(mem_buf); + env->gpr[n] = ldl_le_p(mem_buf); return sizeof(target_ulong); } n -= TOTAL_PER_THREAD_REGS; if (n < NUM_PREGS) { - env->pred[n] = ldl_p(mem_buf) & 0xff; + env->pred[n] = ldl_le_p(mem_buf) & 0xff; return sizeof(uint8_t); } @@ -117,7 +117,7 @@ static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { - env->VRegs[n].uw[i] = ldl_p(mem_buf); + env->VRegs[n].uw[i] = ldl_le_p(mem_buf); mem_buf += 4; } return MAX_VEC_SIZE_BYTES; @@ -127,7 +127,7 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { - env->QRegs[n].uw[i] = ldl_p(mem_buf); + env->QRegs[n].uw[i] = ldl_le_p(mem_buf); mem_buf += 4; } return MAX_VEC_SIZE_BYTES / 8; From patchwork Tue Oct 15 15:44:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8627D1D879 for ; Tue, 15 Oct 2024 15:46:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jkk-0001Im-0u; Tue, 15 Oct 2024 11:46:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jkB-0000lk-Br for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:57 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jk9-0000my-1R for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:45:55 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-71e70c32cd7so1312317b3a.1 for ; Tue, 15 Oct 2024 08:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007151; x=1729611951; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VAYPvc4MvYXzz9JrX6iaI+URWPP2ZVGYdAtSbEKt48E=; b=ZcP43lYGBGFIasMjxFUsqAF/p+WpOd50uEudzdQe4a+sDNIWQ2pYziSRwDEt5Q2i33 7IdCVaRO9m6KKUWrZa5ct3jSqmrzJfUtVpGxM6PTUW12y7395F90S3UAJXzFvkcm5hdi 1AtHS1YSv6Orwpnw9luwI5ngSBB7ZSGAYpwNDyXHZY+xq2BZfgdg6GZFE4QTDYttNlL8 gU7EwUUHuPKYX7xvtJ5JJ49MfYIq94KSKvnZARI1UqMgv4mDwvG3ILCbzI0T3t31xDIQ AkHwPR2lUQyjjKAY4Mjv2+KPY0MqWylmjBrs0vembjD+GK5elcroqI/CCaaOBWyXZnnS sPAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007151; x=1729611951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VAYPvc4MvYXzz9JrX6iaI+URWPP2ZVGYdAtSbEKt48E=; b=NnKEwvhab09admFL89IMtJWkEcBROYw6boDYIwOiOKCPPdwIwLvpY+ED8qVGz3Xras PmkRnED/mRDXcsmT1aRQVQdsWAVm3oDCmf0JHzXYbyW9P/9pZh6FZgKSfzTVs1CPT7j2 YbWWAgVnFL92crUZU0ZBM9xnmsvmbXZ9HmTo/e5uUF+80gf87qkvdRcUKZGxzbwyH3wL +IXnCgkgn3PT9kaZfrrTAyjJEU7kxr/xc64arBKqdf4pqEdF89mYPebN0UnBOkbywAGa KJTaYWot/cVtO+xMxmihN6hgH9lSvIks4be+oPR2igEYM4T0cSrNoLqX1X7CbfRDljtX DUbQ== X-Gm-Message-State: AOJu0Yzz/YfNvrhDBOMTJo0TXWFhfkr6g5OxelmB+36330ftj347+wP6 ny9Rrm3ceDo/JnRWWGD3uu/45Ls1fqrldEbyqydfEc9GYOKBQFyG7DcrWuWZG6iPOiYwqv7XJ7P F X-Google-Smtp-Source: AGHT+IHah/txmS12fo5sQyETEbZR9GQoUzMT+84D1dMKydbhlAljrQV5zl4cpGc/M44skVdZCN8UTw== X-Received: by 2002:a05:6a00:174c:b0:71e:5e04:be9b with SMTP id d2e1a72fcca58-71e7da46331mr1331898b3a.12.1729007150701; Tue, 15 Oct 2024 08:45:50 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e77518a76sm1414240b3a.220.2024.10.15.08.45.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 09/33] hw/i386: Use explicit little-endian LD/ST API Date: Tue, 15 Oct 2024 12:44:18 -0300 Message-ID: <20241015154443.71763-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/i386/); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-9-philmd@linaro.org> --- hw/i386/multiboot.c | 39 +++++++++++++++++++-------------------- hw/i386/x86-common.c | 26 +++++++++++++------------- 2 files changed, 32 insertions(+), 33 deletions(-) diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index 3332712ab35..b2648bff71a 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -133,9 +133,9 @@ static void mb_add_mod(MultibootState *s, p = (char *)s->mb_buf + s->offset_mbinfo + MB_MOD_SIZE * s->mb_mods_count; - stl_p(p + MB_MOD_START, start); - stl_p(p + MB_MOD_END, end); - stl_p(p + MB_MOD_CMDLINE, cmdline_phys); + stl_le_p(p + MB_MOD_START, start); + stl_le_p(p + MB_MOD_END, end); + stl_le_p(p + MB_MOD_CMDLINE, cmdline_phys); mb_debug("mod%02d: "HWADDR_FMT_plx" - "HWADDR_FMT_plx, s->mb_mods_count, start, end); @@ -168,9 +168,9 @@ int load_multiboot(X86MachineState *x86ms, /* Ok, let's see if it is a multiboot image. The header is 12x32bit long, so the latest entry may be 8192 - 48. */ for (i = 0; i < (8192 - 48); i += 4) { - if (ldl_p(header+i) == 0x1BADB002) { - uint32_t checksum = ldl_p(header+i+8); - flags = ldl_p(header+i+4); + if (ldl_le_p(header + i) == 0x1BADB002) { + uint32_t checksum = ldl_le_p(header + i + 8); + flags = ldl_le_p(header + i + 4); checksum += flags; checksum += (uint32_t)0x1BADB002; if (!checksum) { @@ -223,11 +223,11 @@ int load_multiboot(X86MachineState *x86ms, mb_kernel_size, (size_t)mh_entry_addr); } else { /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */ - uint32_t mh_header_addr = ldl_p(header+i+12); - uint32_t mh_load_end_addr = ldl_p(header+i+20); - uint32_t mh_bss_end_addr = ldl_p(header+i+24); + uint32_t mh_header_addr = ldl_le_p(header + i + 12); + uint32_t mh_load_end_addr = ldl_le_p(header + i + 20); + uint32_t mh_bss_end_addr = ldl_le_p(header + i + 24); - mh_load_addr = ldl_p(header+i+16); + mh_load_addr = ldl_le_p(header + i + 16); if (mh_header_addr < mh_load_addr) { error_report("invalid load_addr address"); exit(1); @@ -239,7 +239,7 @@ int load_multiboot(X86MachineState *x86ms, uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr); uint32_t mb_load_size = 0; - mh_entry_addr = ldl_p(header+i+28); + mh_entry_addr = ldl_le_p(header + i + 28); if (mh_load_end_addr) { if (mh_load_end_addr < mh_load_addr) { @@ -364,22 +364,21 @@ int load_multiboot(X86MachineState *x86ms, /* Commandline support */ kcmdline = g_strdup_printf("%s %s", kernel_filename, kernel_cmdline); - stl_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline)); - - stl_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name)); - - stl_p(bootinfo + MBI_MODS_ADDR, mbs.mb_buf_phys + mbs.offset_mbinfo); - stl_p(bootinfo + MBI_MODS_COUNT, mbs.mb_mods_count); /* mods_count */ + stl_le_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline)); + stl_le_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, + bootloader_name)); + stl_le_p(bootinfo + MBI_MODS_ADDR, mbs.mb_buf_phys + mbs.offset_mbinfo); + stl_le_p(bootinfo + MBI_MODS_COUNT, mbs.mb_mods_count); /* mods_count */ /* the kernel is where we want it to be now */ - stl_p(bootinfo + MBI_FLAGS, MULTIBOOT_FLAGS_MEMORY + stl_le_p(bootinfo + MBI_FLAGS, MULTIBOOT_FLAGS_MEMORY | MULTIBOOT_FLAGS_BOOT_DEVICE | MULTIBOOT_FLAGS_CMDLINE | MULTIBOOT_FLAGS_MODULES | MULTIBOOT_FLAGS_MMAP | MULTIBOOT_FLAGS_BOOTLOADER); - stl_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */ - stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP); + stl_le_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */ + stl_le_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP); mb_debug("multiboot: entry_addr = %#x", mh_entry_addr); mb_debug(" mb_buf_phys = "HWADDR_FMT_plx, mbs.mb_buf_phys); diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 992ea1f25e9..b86c38212ea 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -586,7 +586,7 @@ static bool load_elfboot(const char *kernel_filename, uint64_t elf_low, elf_high; int kernel_size; - if (ldl_p(header) != 0x464c457f) { + if (ldl_le_p(header) != 0x464c457f) { return false; /* no elfboot */ } @@ -669,8 +669,8 @@ void x86_load_linux(X86MachineState *x86ms, * kernel protocol version. * Please see https://www.kernel.org/doc/Documentation/x86/boot.txt */ - if (ldl_p(header + 0x202) == 0x53726448) /* Magic signature "HdrS" */ { - protocol = lduw_p(header + 0x206); + if (ldl_le_p(header + 0x202) == 0x53726448) /* Magic signature "HdrS" */ { + protocol = lduw_le_p(header + 0x206); } else { /* * This could be a multiboot kernel. If it is, let's stop treating it @@ -762,7 +762,7 @@ void x86_load_linux(X86MachineState *x86ms, /* highest address for loading the initrd */ if (protocol >= 0x20c && - lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { + lduw_le_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { /* * Linux has supported initrd up to 4 GB for a very long time (2007, * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), @@ -781,7 +781,7 @@ void x86_load_linux(X86MachineState *x86ms, */ initrd_max = UINT32_MAX; } else if (protocol >= 0x203) { - initrd_max = ldl_p(header + 0x22c); + initrd_max = ldl_le_p(header + 0x22c); } else { initrd_max = 0x37ffffff; } @@ -797,10 +797,10 @@ void x86_load_linux(X86MachineState *x86ms, sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; if (protocol >= 0x202) { - stl_p(header + 0x228, cmdline_addr); + stl_le_p(header + 0x228, cmdline_addr); } else { - stw_p(header + 0x20, 0xA33F); - stw_p(header + 0x22, cmdline_addr - real_addr); + stw_le_p(header + 0x20, 0xA33F); + stw_le_p(header + 0x22, cmdline_addr - real_addr); } /* handle vga= parameter */ @@ -824,7 +824,7 @@ void x86_load_linux(X86MachineState *x86ms, exit(1); } } - stw_p(header + 0x1fa, video_mode); + stw_le_p(header + 0x1fa, video_mode); } /* loader type */ @@ -839,7 +839,7 @@ void x86_load_linux(X86MachineState *x86ms, /* heap */ if (protocol >= 0x201) { header[0x211] |= 0x80; /* CAN_USE_HEAP */ - stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); + stw_le_p(header + 0x224, cmdline_addr - real_addr - 0x200); } /* load initrd */ @@ -879,8 +879,8 @@ void x86_load_linux(X86MachineState *x86ms, sev_load_ctx.initrd_data = initrd_data; sev_load_ctx.initrd_size = initrd_size; - stl_p(header + 0x218, initrd_addr); - stl_p(header + 0x21c, initrd_size); + stl_le_p(header + 0x218, initrd_addr); + stl_le_p(header + 0x21c, initrd_size); } /* load kernel and setup */ @@ -926,7 +926,7 @@ void x86_load_linux(X86MachineState *x86ms, kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; kernel = g_realloc(kernel, kernel_size); - stq_p(header + 0x250, prot_addr + setup_data_offset); + stq_le_p(header + 0x250, prot_addr + setup_data_offset); setup_data = (struct setup_data *)(kernel + setup_data_offset); setup_data->next = 0; From patchwork Tue Oct 15 15:44:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64607CFC27C for ; Tue, 15 Oct 2024 15:47:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jkr-0001aO-65; Tue, 15 Oct 2024 11:46:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jkI-0000nd-0v for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:04 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jkF-0000ns-Db for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:01 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-7ea7e250c54so1544699a12.0 for ; Tue, 15 Oct 2024 08:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007157; x=1729611957; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IZLWKxN76C8sY7IOvNsANw/zHjCd07PTHy82cP8hbyw=; b=YIVWbctz/euO2msYVM+jEVt3Ne+kvsNrR7ofuLlTomoOs4FeAAG+AZM6h6Wu6x229t tEuD+8HhCRixK75sEyVr6KtIyZpKQVPQaGCOZKsv4fnyZdCd40R0ohK5z56xpOPIQ9rR 34yfg10hqf+znlTOVwzpBgsI7DLMvLmzD+oqoiV9V6IQJsOEL83DOxnUV7dbNnj0ezIH KnZHCPhJuANmDjP5ZW1EDihqMoPJx/dhNqeZSpxEGF0YucNHSEN7BEiXrEvX1BR5PvFe yPXu8VPrUyiqhK5K4qvhUBeKidjoE7XubF3v1by91GkJMOSkQDw0393Z9HfF47+VNPko iqjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007157; x=1729611957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IZLWKxN76C8sY7IOvNsANw/zHjCd07PTHy82cP8hbyw=; b=brj8+yq8Ogm+ktsNTnsSaaNqXC15jDtKqYcxvvfkuf3dq72q2cXb0diDDZy/jhsIqo iaJpbIgVz5M3ZVCF/RtXsz4WrJ3X5kX1LnXB1ixtZ2nV0dQIPzAjP6TcFqi1SxR1S1rg i5VvP5HV0P5B2k3H6o0lRe5JGleusgd2fT/RKv0ExkpQv9cQ0PhZj6RzQrORXGQzHBN+ 7LZ7HCa4f5IiDugSA/JAnijv9sjpuTJy4ZMuug760G++JqSWTRp4EFg2kfaGytdvl/4P Oq6pjvUiT9HwY6bN8L778nccKnURXKHprWhCJ1K0A3oQqO9MZvT9y+WUx/W/CwTQmPBi WA3w== X-Gm-Message-State: AOJu0Yx0l5ZlR3NUOIy5+hca/nNe8xqY4NYYvrESvZ5F0VVi624coBSg nMbAijtNec51TPj76of90GhcCs66MWVyM+0eo8EGgTb1WFEmC7Ar3cpwLvS/T/722zqqYZUivUP h X-Google-Smtp-Source: AGHT+IG06gqex6f9UGou6mQ13zmzsLysWsflt/rDmUAe3g7xPNTDKS3mnCwjLHCGRqfIdOumlSMZ3Q== X-Received: by 2002:a05:6a21:1743:b0:1d8:aca7:912 with SMTP id adf61e73a8af0-1d8c95d5a38mr18109100637.28.1729007157463; Tue, 15 Oct 2024 08:45:57 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e774cf306sm1409704b3a.153.2024.10.15.08.45.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:45:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 10/33] target/avr: Use explicit little-endian LD/ST API Date: Tue, 15 Oct 2024 12:44:19 -0300 Message-ID: <20241015154443.71763-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The AVR architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/avr/); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-11-philmd@linaro.org> --- target/avr/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index d6d3c1479b3..aea71282a58 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -69,13 +69,13 @@ int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* SP */ if (n == 33) { - env->sp = lduw_p(mem_buf); + env->sp = lduw_le_p(mem_buf); return 2; } /* PC */ if (n == 34) { - env->pc_w = ldl_p(mem_buf) / 2; + env->pc_w = ldl_le_p(mem_buf) / 2; return 4; } From patchwork Tue Oct 15 15:44:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 077B6D1D879 for ; Tue, 15 Oct 2024 15:47:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jl9-0002EP-08; Tue, 15 Oct 2024 11:46:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jkO-0000tu-LP for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:13 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jkM-0000oH-9b for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:08 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-7ea80863f12so1040569a12.1 for ; Tue, 15 Oct 2024 08:46:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007164; x=1729611964; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wE+j6sYSDQnj04FOXSrYmsK1n/6FhkfUBDKG2lPE568=; b=CzqHmWxM8wAqvx+avqXhpJQxTYV8lPbZNWc6+YLlYu4giE0JWOdfh+qyceECVFBYlr 1HGIGbDVbtY8KjS8jRsXpRjW9B8jEO3xNaRFvzWYLX2Nb/LM1HjuorXysHIFhd1CkZBJ 11STLNr5OSpjgF8S8mnvYDXuRZDO6QxQ5ZnaC6pomeZ/aXooAQ10EPTpwBEg0xG+3EIH 53JrbF0D2bL1r7mGfFDGi/KXgTVUaOraNnflcnyOpU0o5OqMjiENc30Pf7mU0o16aMVi KmbhyFiLwJ8fllQxXeijNzpzHC2FGgWYiF1Xl6/h8uWh3wX3wIYUO5Osd19/oiUvtZcX 05AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007164; x=1729611964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wE+j6sYSDQnj04FOXSrYmsK1n/6FhkfUBDKG2lPE568=; b=kHOtZhug5xCSBf42TUU5B/Phtw01HFLsSYhayWXSJurCv3GryH8bk4NrtJJzvSClEg ILauftPj7tisCOefDoaUZklbN7zNYyFo0TP36S64KsgDCthHCpIb5prZevokL2l542EE n9R3K7/82OuLtMTQnpU/wACWvVKHcBgqF19HK/OYylr5uchUHPYgq53GIHzhXt96N+eY K3MvK9d4PCx/amUL/KXce0uVDhXojASZPbQ7soHCi+EWtXdp4UJtY68NvuGD7jdhHJhi 41MDO22FwpkNVRB9jMspr2RPu8BhIZLf5cc+5lWl8qjjj9eQ4RU3SkUhudSrrq50u2To XrQg== X-Gm-Message-State: AOJu0YyFqYKm+alMB1GhRB5k8uJT44d8qOecf+AAjTvBhI5taseKbkD9 QWZNRmAuXwMiV6BfRyWXAb5HovWrukuHT6FkC1Oop4JoRf4brGzoTiFcX62litBZfQ71f4alimK s X-Google-Smtp-Source: AGHT+IG1yj44MqeuJgA21QW4HzJTiL7IB/LAz5feLWuAOXG9Jr+e4Nntj4InOfBlfAJ67X75y2S86Q== X-Received: by 2002:a05:6a21:3943:b0:1d8:af46:2152 with SMTP id adf61e73a8af0-1d905ec45c0mr886004637.11.1729007164507; Tue, 15 Oct 2024 08:46:04 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e77518a5fsm1398077b3a.214.2024.10.15.08.46.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , Richard Henderson Subject: [PULL 11/33] linux-user/i386: Use explicit little-endian LD/ST API Date: Tue, 15 Oct 2024 12:44:20 -0300 Message-ID: <20241015154443.71763-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20241003234211.53644-4-philmd@linaro.org> Reviewed-by: Richard Henderson --- linux-user/i386/signal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index cb90711834f..0f11dba831f 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -754,8 +754,8 @@ static bool restore_sigcontext(CPUX86State *env, struct target_sigcontext *sc) env->eip = tswapl(sc->rip); #endif - cpu_x86_load_seg(env, R_CS, lduw_p(&sc->cs) | 3); - cpu_x86_load_seg(env, R_SS, lduw_p(&sc->ss) | 3); + cpu_x86_load_seg(env, R_CS, lduw_le_p(&sc->cs) | 3); + cpu_x86_load_seg(env, R_SS, lduw_le_p(&sc->ss) | 3); tmpflags = tswapl(sc->eflags); env->eflags = (env->eflags & ~0x40DD5) | (tmpflags & 0x40DD5); From patchwork Tue Oct 15 15:44:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88994CFC27C for ; Tue, 15 Oct 2024 15:47:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlB-0002T8-Rl; Tue, 15 Oct 2024 11:46:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jkU-00012m-NJ for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:17 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jkS-0000p9-VZ for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:14 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-7ea7e2ff5ceso1792256a12.2 for ; Tue, 15 Oct 2024 08:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007171; x=1729611971; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Snu/XbO5DWXIOAW758ZcEcsN6Qt6EdTKtVraeirV4SA=; b=VtnSe7yOTyK9LIpZCZcYzsn8evD8gMpr9i7hBSmJIJFJDmXzdFgMy+bak4FxkZ+hmD fwuuYB3Wn8IGdj7NA3tNwPn1GlretOAC+Bl0TAbzApFe+4xFpaBM2M1wk7kqY1VCMe4e jUI+sYlqLuHCFpij+Fy8zmRCWJKKITEKQy6m4GUFvoOD4B80t72GupBGaO+gTaQZ7fRh chQOb9O8fwi2qXls6Rl5dujQoOTiXF5jj9nFF6qeBjb2j0fqR83cedvXi6wuw1aX1no+ DlXVgXqxSjiXLMHGgMXeHuCQ+dOlspEHZEFRykY8s89bbPUCSx3UTM3ejYMgEIPWT6Nw H6RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007171; x=1729611971; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Snu/XbO5DWXIOAW758ZcEcsN6Qt6EdTKtVraeirV4SA=; b=gmEnVB4+x/ie1s+dmwoSOeVEuFo0wtWXgWTpQT3ji57Z1WnzCXD6iJbSW2XSnNpPv3 qToqFM5uj1+HikJ272C+qqAS6oBBfTFgIVA3s3gwUFy6qgNSAlvSYhMMLb84/EEryDkQ hGYDEd+9LEe2d94k+WoT4R59JvWmlEZPewgalhKbTR8SRs6Vd8zi29c+TBfzztAeOPJM 1U5YfnfnncO60FuyynoOFW5xgwNNxaUCJLTCg13KLM9xJJMESrsQldMIAJlgrJCVbOBO 37Qc8QCGiRP5GP1jP2+4BDe3grCXoNv7h8CliUwU3n71OZQB2mhfUM48omxTXyNE+NAf nqMg== X-Gm-Message-State: AOJu0YylrW/Rgn0pSR/ffmZoTHk1qktcXKYMnpJEpbq0lEwHBdTROinE KBBlC73GfVs7SsMO/W8hoZ7fOoszHBNVmhHm8hOn3cKxLUChSk18jlx2i2VykeUWXYG9p/ERRLD 9 X-Google-Smtp-Source: AGHT+IHZqN4p43cCqYs2KuLdeVSQnz0NRMQlJ+DbSHB9oVkD3ZTjUfbi3c0E0azFSdrJQW/wEpow1w== X-Received: by 2002:a05:6a21:168e:b0:1d7:7ea:2f36 with SMTP id adf61e73a8af0-1d8bcefde33mr21415030637.4.1729007171317; Tue, 15 Oct 2024 08:46:11 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e7750a524sm1402861b3a.200.2024.10.15.08.46.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 12/33] target/loongarch: Use explicit little-endian LD/ST API Date: Tue, 15 Oct 2024 12:44:21 -0300 Message-ID: <20241015154443.71763-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The LoongArch architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/loongarch/); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-13-philmd@linaro.org> --- target/loongarch/gdbstub.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 3a03cf9cba9..dafa4feb75d 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -67,10 +67,10 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) int length = 0; if (is_la64(env)) { - tmp = ldq_p(mem_buf); + tmp = ldq_le_p(mem_buf); read_length = 8; } else { - tmp = ldl_p(mem_buf); + tmp = ldl_le_p(mem_buf); read_length = 4; } @@ -106,13 +106,13 @@ static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) int length = 0; if (0 <= n && n < 32) { - env->fpr[n].vreg.D(0) = ldq_p(mem_buf); + env->fpr[n].vreg.D(0) = ldq_le_p(mem_buf); length = 8; } else if (32 <= n && n < 40) { env->cf[n - 32] = ldub_p(mem_buf); length = 1; } else if (n == 40) { - env->fcsr0 = ldl_p(mem_buf); + env->fcsr0 = ldl_le_p(mem_buf); length = 4; } return length; From patchwork Tue Oct 15 15:44:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCF0CD1D882 for ; Tue, 15 Oct 2024 15:50:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlE-0002sE-Pr; Tue, 15 Oct 2024 11:47:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jkc-00014T-4W for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:27 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jka-0000q9-2B for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:21 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-7e6d04f74faso3572872a12.1 for ; Tue, 15 Oct 2024 08:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007178; x=1729611978; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TJ9wROiE5L2FprbXeD8aDG0nJOd3bETYw217/JvIATA=; b=HONkcfJCpWMGGUqKH/DlPPbbBhN8HB3vYF6JAhzGRvg3TTZtVCHJY/R1bu7kqDLp3P TxpQm9/k/J/Hb0peJhUU6PPu1EM/rpc4V9HvrsP1YwEN5c4pOu6Jp0DsXuZLEYX5slrO Q7LCdjZnRyEd6DmbYq1ZmOpotJ0pFavgwDX9WQqsRhMpsP09uls8nljfrZLOWVfWGF3j OjhuXBM1Bhe5/6yG6ifabNzRApkj09dse5zB+Whbw2sGZDTvCi6VQ9dBiYkvZokCZfdV kYO3HX2pWhWwlR3/D7geP1Z9xDcftR58EDgefctRka0fui+/BpDT8lylOZD7+fsm6gyw vzGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007178; x=1729611978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TJ9wROiE5L2FprbXeD8aDG0nJOd3bETYw217/JvIATA=; b=w/bIDNVp089lPdyjM6RxIizwckarc9nzr/OLNWJuZL2LslJ7BnvYg5gqFNQFgZa4Z/ uqEo8heRW/5pNUHLJheQU6SMqNB6MX5bC/arDXhBRyDM1cKP3/Vg2zJ6woYRIMcxQKvm yL25rpuCbNRwSkXkA4k7u/58SyFrs2ZcAOk42kgmz/vVf4RRfTFZhZrzZEDBNnGHbqWS X4Qblg+Mj+HPmulfk2wu7P94cMPQzJMpfckMkNePeYlyknpL7lw5/v+icjt/p9lxgxu8 QlasZvOBiOZyKKtQ5ebPSvN4yM6mY11OGLcByrcTUlMu7PLPzIP5rQsBW0ontfoYIZbk 96vA== X-Gm-Message-State: AOJu0YxeAaOkxSd0Cd6icPfWXUT206fiQYhCZ3kYFzHb8Gy6YQUgwJTn oMyk2iQ/x87Sm1GNUJ/SUGk1PjiVJQk3H5fPBwuABistTigfSyDrvOAwSBTddRj4Eub0mF+2Kco y X-Google-Smtp-Source: AGHT+IE61FUE6FkXT6kb2g1gsbTca+OBIGuMOx2CC2b/viDnw7r71KZWgwBu0LDgxkfqf8oPk8/+JQ== X-Received: by 2002:a05:6a21:390:b0:1d7:1288:8338 with SMTP id adf61e73a8af0-1d8bc8126a5mr23516679637.8.1729007178180; Tue, 15 Oct 2024 08:46:18 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e774a28d5sm1413705b3a.103.2024.10.15.08.46.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 13/33] target/tricore: Use explicit little-endian LD/ST API Date: Tue, 15 Oct 2024 12:44:22 -0300 Message-ID: <20241015154443.71763-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The TriCore architecture uses little endianness. Directly use the little-endian LD/ST API. Mechanical change using: $ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/tricore/); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004163042.85922-15-philmd@linaro.org> --- target/tricore/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c index 29a70051ffe..0b73b1280e0 100644 --- a/target/tricore/gdbstub.c +++ b/target/tricore/gdbstub.c @@ -124,7 +124,7 @@ int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUTriCoreState *env = cpu_env(cs); uint32_t tmp; - tmp = ldl_p(mem_buf); + tmp = ldl_le_p(mem_buf); if (n < 16) { /* data registers */ env->gpr_d[n] = tmp; From patchwork Tue Oct 15 15:44:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14024D1D885 for ; Tue, 15 Oct 2024 15:48:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlH-00039A-48; Tue, 15 Oct 2024 11:47:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jki-0001Ij-Vw for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:29 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jkh-0000qq-AR for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:28 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-20cb89a4e4cso24755355ad.3 for ; Tue, 15 Oct 2024 08:46:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007185; x=1729611985; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WPZ3O54SfWAZW6QbB+o6pdTzqrBR+joOSB0w++8bQOE=; b=rC1Whf0i32nTidP7DBpmvre+0GG7GZSoOxE+BazDM0/seSH0iUTx3tVti4wB2/MWqT ZZOe/BHbNFK2OFSHIPHH7e0+NHY+fsKEnd1A6H/lNDR5HEMgt/+UcEgN8DMswKHNXZTY sfBCtHn6Gf9wQzh0/2n0Un3matLBCADSy3bZcGhJMbohfZufVGZiW4pShMk4HKdpVG7Q gmizJ59LD912ko97pukBVydgvRcu/2nQUvjts3NtzKzYiWprnxGajQoTh0hIuRmF9/ii 4YCYM+aOAFpxMdixKeWrwvdPmIvKz0c1iml+lyCC3xbrFD6u1EP6kX0+BdUdESWrJcKB rUHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007185; x=1729611985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WPZ3O54SfWAZW6QbB+o6pdTzqrBR+joOSB0w++8bQOE=; b=WT+1Ob/piHgG8FnOGyN/Kle4+/Y//cCAZAFvuWL5fMEC05bc0UJ2m04qPqcDFdQxdR YE3uvcyhHM/ibFZoI93/yJGA0C+W3Fhp000rj++WKj+VkXQUYNbc+gZmU1zYtvwjI9Mm r3N+ZdSixMYw2NN2oM5UmtsdLH7v7ajS5vvFKqhrpTvYRKrkH3VgtrtSmMWlfHv3jC2R I/jjbZaAIGsvH6veaxOUEakGqqKBhALnwYu92SVeHu4MKoRPre0iyjrJNYa7IQJUWZx+ 9u5nIbQpFrHKkEjyNaNQlzGR1jtU/n5kMXzBsCnHdWfv/mDGZUfqZrcDAuXZ+0L/VxI3 4uDA== X-Gm-Message-State: AOJu0YzlIcbVw7F4bP7+c9ujx0LQe9QJWZEjlNjucXlKYYa8p67rjH7b HsD1WRUB/K/12BIK1k1s8r1dHFNTqpsblnG/I25rzzCk0hd0GriOOdu0O0U/LW1bXfgefNCHwEi A X-Google-Smtp-Source: AGHT+IHNrH5aeLxab4iEA0Gx5smKxNHh95eveecRpONFnpmScd38jOAlZOvb67Qwpkr06672VLvCtA== X-Received: by 2002:a17:902:d584:b0:20c:9d79:cf85 with SMTP id d9443c01a7336-20d27f2805fmr9244255ad.54.1729007185052; Tue, 15 Oct 2024 08:46:25 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1806c6a9sm13489765ad.302.2024.10.15.08.46.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 14/33] target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Date: Tue, 15 Oct 2024 12:44:23 -0300 Message-ID: <20241015154443.71763-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Directly use tcg_constant_tl() for constant integer, this save a call to tcg_gen_movi_tl(). Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004202621.4321-3-philmd@linaro.org> --- target/tricore/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index a46a03e1fd8..4a12d2ca191 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -2732,8 +2732,7 @@ static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); - tcg_gen_movi_tl(mask, 1); - tcg_gen_shl_tl(mask, mask, width); + tcg_gen_shl_tl(mask, tcg_constant_tl(1), width); tcg_gen_subi_tl(mask, mask, 1); tcg_gen_shl_tl(mask, mask, pos); From patchwork Tue Oct 15 15:44:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2423D1D882 for ; Tue, 15 Oct 2024 15:47:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlK-0003dJ-IO; Tue, 15 Oct 2024 11:47:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jkp-0001W6-7y for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:35 -0400 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jkn-0000s7-Iw for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:34 -0400 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-288642376bcso2446575fac.1 for ; Tue, 15 Oct 2024 08:46:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007192; x=1729611992; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h/M6ZeKd6OjvAtfWG6gTR4wPDGVzgIAmQPnpr57Wj6k=; b=OKCYJoBcDSK0ksovcO9hj+f8IGeLK5T3YIULW30rQ9qObfHkMVSnTSF+mPZK1U9oZm CRQHaa+OcZUBPw+KVsnfJuoLtmfsPxPd9gOOcA3LBjTS/tmpMqhGFxWHJFS0Z4k00vMP rrhEH9Tg63aEG508DAYrG2jA+Jg7/b4cB2aJX3Elpt0okWTGNYVDOFYHFMYtEJTWabT4 cyTeOB3lrGyQBzwXCX1+GqPw0LTX3WMTR+v/FkjTE+AKjUS1OdjRkTaA3/shJSdFEIXt Isd60DMwjVMRLcJcf9N6Rs/lTAKKz+UfkhaTEcg6AU1MWVjmtgyGIqR5zlJhQKoiUUgz VpFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007192; x=1729611992; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h/M6ZeKd6OjvAtfWG6gTR4wPDGVzgIAmQPnpr57Wj6k=; b=n7fZLtzIbM/zZByAAzvUoCpmCKsW6E+EEfHMofWa9Pn8pJvGMv4iuPo/HaMPlL+Zfj xAn4RxxFORB8jyIfogwFe/sETT6rWXHrL24art4hdNB/HjhVRhm60S5AFD/18AVTjXyW Dh+E24ooaLUiuv0W9RTTPc7bLo2hB1dxdERLVgvSvLWyvIXsM5B6YIyij/A+Aaxdfxv5 +5eHZFgwF9XXXWJXtm+5hDa28bcheJkwzOiiqzm6IuWkuoFacVztIHaiPHFdRqG7krUJ JEGlP2kHuRLzzeX8TyZH9ZeHfVRDrG8F0J9FhDASsEuH45prJuNJx866p6+EBVD6rzj2 dQqA== X-Gm-Message-State: AOJu0Yy8XC0pjzzvsCvIbdVbx5BjKLTmmssdsKQkFykLurPKBnzo0uFi xPoft3iir3O/xrOlrvLItXBe92Kb0Lbn01IslSHrxMtQ+EOvfv+6NNKICzS5V97SrHkZm5XsJlt I X-Google-Smtp-Source: AGHT+IEz7m3HFPxuW9kgXku+KQ4th/nTbLtPWGSpqvoJJzPsNUesHc8oLcS4d6+UI2mN3KDXR3c4WQ== X-Received: by 2002:a05:6870:c111:b0:288:60d6:f183 with SMTP id 586e51a60fabf-28887478de5mr6900285fac.38.1729007191877; Tue, 15 Oct 2024 08:46:31 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ea9c71a8aesm1509253a12.81.2024.10.15.08.46.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 15/33] target/ppc: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Date: Tue, 15 Oct 2024 12:44:24 -0300 Message-ID: <20241015154443.71763-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=philmd@linaro.org; helo=mail-oa1-x33.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Directly use tcg_constant_tl() for constant integer, this save a call to tcg_gen_movi_tl() and a temp register. Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004202621.4321-4-philmd@linaro.org> --- target/ppc/translate.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 71513ba9646..7689b2ac2e1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1588,16 +1588,13 @@ static opc_handler_t invalid_handler = { static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) { TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); TCGv_i32 t = tcg_temp_new_i32(); - tcg_gen_movi_tl(t0, CRF_EQ); - tcg_gen_movi_tl(t1, CRF_LT); tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), - t0, arg0, arg1, t1, t0); - tcg_gen_movi_tl(t1, CRF_GT); + t0, arg0, arg1, + tcg_constant_tl(CRF_LT), tcg_constant_tl(CRF_EQ)); tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), - t0, arg0, arg1, t1, t0); + t0, arg0, arg1, tcg_constant_tl(CRF_GT), t0); tcg_gen_trunc_tl_i32(t, t0); tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); @@ -2974,8 +2971,8 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ - tcg_gen_movi_tl(u, 1 << (memop_size(memop) * 8 - 1)); - tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); + tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, + tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); } static void gen_ld_atomic(DisasContext *ctx, MemOp memop) From patchwork Tue Oct 15 15:44:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56D9AD1D87B for ; Tue, 15 Oct 2024 15:50:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlO-00040e-0V; Tue, 15 Oct 2024 11:47:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jky-00023Q-9n for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:52 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jkw-0000sy-1K for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:43 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-20cd76c513cso22067705ad.3 for ; Tue, 15 Oct 2024 08:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007200; x=1729612000; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O3CwF/pvrtCvTLmBwFN1fDWOJO8U19FSddrcPe726vo=; b=SYOxRiWCU3NIq6MAmQMIyIleLr8lYENJ7BVX9E1ijHPbVJim4Ekq3TBUJnMvrAPpyu XOFN9AN0DaI6wu04n8mEHr3u+QV6xfc54fPn+byLKRON8jd7mpZX7Xw6wi1sifgmAIHG EGZnpK0bjbVbPK/bMemCTvBLKUMZWL12xsjXcBZR619VIcSeeyj+XDkZWOTZ+ZqVOiVS JNyxU9SmBG9rwd0BlmFYTuYv0ESq7zCDBot1lU1hgXaEfkmTrzC2FbulpcrwLyAtjchg YvL8K/Gj0g7vPfvS9C/U2Hc+b5kF4Ax6sdHLseC1kVCyWBETXwKzDSbUPdtAmomrq7CZ 2emQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007200; x=1729612000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O3CwF/pvrtCvTLmBwFN1fDWOJO8U19FSddrcPe726vo=; b=HzklblwHmuKc0QbL0hmZxE2LOi/PAr1bhHi3zMTzKHAySfaKdafmM5EsAqHyhbal8X Mj+MHHlSEKDIW84/GsHBSrbbrBG982YdO313xX/FmRrI2Ltt+QXa+v8UuqT0Q5Y/3sHr IWPj5+MO6Kd1DIi+p8saLDsT3tAwQOdVKoHjv9akVZM/4iP3hVQL4Z/aHIIU8AYNbY9Q zwFkjSZcovEZUbT77DPwy9lIY3vJIHIa6WMvmnHBtX0NZ+B5MAQWEqL7DuY+zjNB049S zDMahGXDX2PLMdpQ0AziVo+BRNTcBpFjpyPNyOp0bkZR4ZLDzFYD8g5/p2nj8bxOgZcR irBg== X-Gm-Message-State: AOJu0YxSyCC+h6BnhClsVLfCU8LRmAzSyEcvB+XDruNINeer5lOI7V5j Ua1pmDOSzLQ9ttnHtL18uHb6SQrC1hbHTsfxQaISmFHWgU+0LCeRfzFcuORuwuumy2+lEk8xt/S w X-Google-Smtp-Source: AGHT+IE3mxs8F8RQfXvk/UzQ7THNli/ACGhumpWbPhRQVmaCgaZImax8PDXgVtm4G7yy5ifxjtbU6g== X-Received: by 2002:a17:902:db12:b0:20b:c1e4:2d70 with SMTP id d9443c01a7336-20ca147e89bmr214989295ad.23.1729007198962; Tue, 15 Oct 2024 08:46:38 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d18036593sm13536675ad.164.2024.10.15.08.46.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , Pierrick Bouvier Subject: [PULL 16/33] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry Date: Tue, 15 Oct 2024 12:44:25 -0300 Message-ID: <20241015154443.71763-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move code evaluation from preprocessor to compiler so both if() ladders are processed. Mostly style change. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Message-Id: <20240930073450.33195-8-philmd@linaro.org> --- hw/xtensa/xtfpga.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 45b29d3b4e8..398e6256e1d 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -415,8 +415,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) } } if (entry_point != env->pc) { - uint8_t boot[] = { -#if TARGET_BIG_ENDIAN + uint8_t boot_be[] = { 0x60, 0x00, 0x08, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -425,7 +424,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 0x0a, 0x00, 0x00, /* jx a0 */ -#else + }; + uint8_t boot_le[] = { 0x06, 0x02, 0x00, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -434,14 +434,16 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 0xa0, 0x00, 0x00, /* jx a0 */ -#endif }; + const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be) + : sizeof(boot_le); + uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le; uint32_t entry_pc = tswap32(entry_point); uint32_t entry_a2 = tswap32(tagptr); memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); - cpu_physical_memory_write(env->pc, boot, sizeof(boot)); + cpu_physical_memory_write(env->pc, boot, boot_sz); } } else { if (flash) { From patchwork Tue Oct 15 15:44:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32682D1D87B for ; Tue, 15 Oct 2024 15:50:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlD-0002f4-BP; Tue, 15 Oct 2024 11:46:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jl5-00028o-4j for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:52 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jl2-0000ub-H2 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:49 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-20cbcd71012so31043135ad.3 for ; Tue, 15 Oct 2024 08:46:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007207; x=1729612007; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eW4qiUY1SBbVKJJvqRXRWIOZdgv3cj76vj7S3dJPHUU=; b=MkUPYbYiRO1+j0D/uoQzMgNIuVqMLCuuZAfmt1MVBDgE5oLfyBsXgz249klmlwdcGV gFTmETx7ruYM5FLiyk7mbKmjZQ9FGNqhMSQiGrjRY0a74uuhPNqqeqEAybM5KKmglb+w uc4eI4lDIzD8bGeN2W6/TwxV71GjUET0bp7f2jE4htSKQ3bbpKwyuKZ/SF/pZBlVZD4g VIGAkneB8ZivHzBZsMOsTK2dbogeORIwRyPlDTdkGc3YnaocTF5qdH666jHVa19SQ+ex ZraBSf8pYRYL+D19esUAuqAuucyWCKVTStUe/7egtaRPIVqIkKxXSf7uJlfoEOE9I6uS JLww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007207; x=1729612007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eW4qiUY1SBbVKJJvqRXRWIOZdgv3cj76vj7S3dJPHUU=; b=MRJvxPZgbsW+z8ZpJLTOrxquFc1CFSYxd3oUuBhBmdQU9L9hCfQ7KloTFELj+L52Gc g/1j0zxUeDFn/+Nc6tYOO6Pze/1d/QkpYW28DJoj8Z90P6iPH2nuL2vsp1TOBPTta/wA iflm1WkavY9VnKASPsCtyHobfIEhpvaBSzQem6OPRTugaQWczbGjSjECQDu0rwYIvvO/ ieqZy9Ruz8OdNg9RDXiR+c5MoSKqgOkqjOKpF49BiFrGgbZHyOXVKZbwFMoKdvg0susn MNmb2fONR8SS/F/ntH94iGWqY7Q9pFKEIfPy7+T/6NHuh26pyJHDf4j7bp2dgf71eu4A 8mfw== X-Gm-Message-State: AOJu0YwfhuJvMTLG0AW8Nqhbx82Y9Zp02/OrBDZc6CngARD6Nt8ExsoJ N2i4y7UQ75fV7vQr/zxaPOBCnQQhqnCYKCgLV1bbMNDrlOEKjnBOVuzzi5BLUd1M+Z5DSR7V0i6 P X-Google-Smtp-Source: AGHT+IE1/HHdRZpUByX513Ft8e3jFhEioi5m+hE3WlcP9S0I2JpzeKAHc/FioN5NnJPvRm+9evWWYw== X-Received: by 2002:a17:902:e749:b0:20c:716c:5c2 with SMTP id d9443c01a7336-20cbb1bb0f5mr141110715ad.13.1729007206847; Tue, 15 Oct 2024 08:46:46 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1806c713sm13409135ad.303.2024.10.15.08.46.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 17/33] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Date: Tue, 15 Oct 2024 12:44:26 -0300 Message-ID: <20241015154443.71763-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In order to re-use cpu_is_bigendian(), declare it on "internal.h" after renaming it as mips_env_is_bigendian(). Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-2-philmd@linaro.org> --- target/mips/internal.h | 5 +++++ target/mips/tcg/ldst_helper.c | 15 +++++---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index a9a22ea00ec..84c8e5e1ae7 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -225,6 +225,11 @@ static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) } } +static inline bool mips_env_is_bigendian(CPUMIPSState *env) +{ + return extract32(env->CP0_Config0, CP0C0_BE, 1); +} + static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 97056d00a27..f92a923d7ad 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -53,11 +53,6 @@ HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) #endif /* !CONFIG_USER_ONLY */ -static inline bool cpu_is_bigendian(CPUMIPSState *env) -{ - return extract32(env->CP0_Config0, CP0C0_BE, 1); -} - static inline target_ulong get_lmask(CPUMIPSState *env, target_ulong value, unsigned bits) { @@ -65,7 +60,7 @@ static inline target_ulong get_lmask(CPUMIPSState *env, value &= mask; - if (!cpu_is_bigendian(env)) { + if (!mips_env_is_bigendian(env)) { value ^= mask; } @@ -76,7 +71,7 @@ void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { target_ulong lmask = get_lmask(env, arg2, 32); - int dir = cpu_is_bigendian(env) ? 1 : -1; + int dir = mips_env_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); @@ -100,7 +95,7 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { target_ulong lmask = get_lmask(env, arg2, 32); - int dir = cpu_is_bigendian(env) ? 1 : -1; + int dir = mips_env_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); @@ -130,7 +125,7 @@ void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { target_ulong lmask = get_lmask(env, arg2, 64); - int dir = cpu_is_bigendian(env) ? 1 : -1; + int dir = mips_env_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); @@ -174,7 +169,7 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { target_ulong lmask = get_lmask(env, arg2, 64); - int dir = cpu_is_bigendian(env) ? 1 : -1; + int dir = mips_env_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); From patchwork Tue Oct 15 15:44:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF689CFC27C for ; Tue, 15 Oct 2024 15:48:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlG-0002zn-DF; Tue, 15 Oct 2024 11:47:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jlB-0002SV-91 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:57 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jl9-0000wI-Fi for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:46:56 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-20cdb889222so23524965ad.3 for ; Tue, 15 Oct 2024 08:46:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007214; x=1729612014; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Oh4eoC7A4RtAScWxiuA7lur7cdy4r2Qar3xooL6q0Pc=; b=LWLTip+aaJ3Ya7d8LqFjd0C5SRLVH9fi59shFjwu6hM4vivPLjFF2y25Bysk9LVkOM E3eYYStVqq+u4igdFV9sHUQZIunC84L4o7Gc9IuIzF3ZjLCPD9XIbV4PklGNaOnEnMVl OJXVjTeX2udCqFKGIpFy/CpVjBYvA5X5BNetfCVi2O+4N7WlKZs3kwPOSUg98l1v7FbT ul4H27H8dhzJ+wzLECHM8EExgL2jPJGsraIODKeZDQgsE2VhztQvTCaPC3nUG1Eh03Ne v6HWwUdINISyXGEinks9c+5zax19nn84W54G+6CvRdPnkJg7EnmwXf+pRusLWqGoMWit FdyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007214; x=1729612014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Oh4eoC7A4RtAScWxiuA7lur7cdy4r2Qar3xooL6q0Pc=; b=ebmi6HUsfGgexWUwRDTvP37IAu9QEnLTumGxTLU2/qkTK+EPXg+xHe8UWkOfMuFwqO RhnCi6njcGfBxhMU0i6XJtg9VWL9t972xVLVC066chzAZ4qgE7BLftZFtQ3qng86xzF3 +MdXX+Tz1u6UZJfnCr+3b+4sjF2Pb/xkl3aowqhzdEFm6DAz73LHW5FwDc/dWva05fkL RE3EmsR6e3odl/AOvljaWZoSv91L9yvQneZLoYrKazyanf7UcgmOsxXuLjJX2cfx4qRt fqVG/5nTfYqQkQYKHIZsMEdBP/jnfAQHivJCBGOiOOLJOPwBAJtIh8XBG1eeYazZoipb Jb+Q== X-Gm-Message-State: AOJu0YznDmuASlyio0g/PcGLvvUdpfPJQfOYrQkl/GvpkMui7punW3Wb 3Jy3Q5eY0zbZA/TimcWW3vdXqm8T1tH/0Jlpw665/1saP6w1jT2LYe9ETp2hq1WBgYMKQdxhrCg y X-Google-Smtp-Source: AGHT+IEcCDEO14LWzBLs+GMWQirR1q8cmIq9rlQs4gQyMGBCPaSU0/p+LTCkND4/YD8+5qIKQhe0Ig== X-Received: by 2002:a17:902:fc4c:b0:20c:8cf9:6147 with SMTP id d9443c01a7336-20ca13f6106mr185357835ad.1.1729007213720; Tue, 15 Oct 2024 08:46:53 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d180382a5sm13428565ad.129.2024.10.15.08.46.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:46:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 18/33] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() Date: Tue, 15 Oct 2024 12:44:27 -0300 Message-ID: <20241015154443.71763-19-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Methods using the 'cpu_' prefix usually take a (Arch)CPUState argument. Since this method takes a DisasContext argument, rename it as disas_is_bigendian(). Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-3-philmd@linaro.org> --- target/mips/tcg/translate.h | 2 +- target/mips/tcg/translate.c | 6 +++--- target/mips/tcg/nanomips_translate.c.inc | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 2b6646b339b..e81a8d5eb9b 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -235,7 +235,7 @@ bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { return FUNC(ctx, a, __VA_ARGS__); } -static inline bool cpu_is_bigendian(DisasContext *ctx) +static inline bool disas_is_bigendian(DisasContext *ctx) { return extract32(ctx->CP0_Config0, CP0C0_BE, 1); } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 50d8537a3b3..3deb48ace9d 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -2010,7 +2010,7 @@ static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr, */ tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); tcg_gen_andi_tl(t1, addr, sizem1); - if (!cpu_is_bigendian(ctx)) { + if (!disas_is_bigendian(ctx)) { tcg_gen_xori_tl(t1, t1, sizem1); } tcg_gen_shli_tl(t1, t1, 3); @@ -2037,7 +2037,7 @@ static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr, */ tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); tcg_gen_andi_tl(t1, addr, sizem1); - if (cpu_is_bigendian(ctx)) { + if (disas_is_bigendian(ctx)) { tcg_gen_xori_tl(t1, t1, sizem1); } tcg_gen_shli_tl(t1, t1, 3); @@ -10856,7 +10856,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); - if (cpu_is_bigendian(ctx)) { + if (disas_is_bigendian(ctx)) { gen_load_fpr32(ctx, fp, fs); gen_load_fpr32h(ctx, fph, ft); gen_store_fpr32h(ctx, fp, fd); diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index b4b746d4187..6e0df1a8c36 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -999,7 +999,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, gen_base_offset_addr(ctx, taddr, base, offset); tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN); - if (cpu_is_bigendian(ctx)) { + if (disas_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { tcg_gen_extr_i64_tl(tmp1, tmp2, tval); @@ -1031,7 +1031,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, gen_load_gpr(tmp1, reg1); gen_load_gpr(tmp2, reg2); - if (cpu_is_bigendian(ctx)) { + if (disas_is_bigendian(ctx)) { tcg_gen_concat_tl_i64(tval, tmp2, tmp1); } else { tcg_gen_concat_tl_i64(tval, tmp1, tmp2); From patchwork Tue Oct 15 15:44:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F653D1D87B for ; Tue, 15 Oct 2024 15:47:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlY-0004rs-SK; Tue, 15 Oct 2024 11:47:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jlI-0003MY-Ce for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:04 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jlG-0000xi-Lx for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:04 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2e2e23f2931so4275453a91.0 for ; Tue, 15 Oct 2024 08:47:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007221; x=1729612021; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DIdGHos2kceOOOIgzSCtXbavAnuw+Mxycbvbjx7Wmpw=; b=WQeoiZ9CpjZvAGMq4L9OSsIpc0E2JWa/gmcKa+tR1XV9w3Z9xGK9fjKJNg0YN6fMnw t/DSfo9w4QJGjMkuvaZjjf9J0LUj6bSkclpzUgao+02Jap/oOYPkE0m7SvuLMe8e+1Eq ZzY9BYU/HXcz/cDGtck/tugf0tFM00pD3IH9dBQQpjekf9Fx5Zz6u+IUXsICY2D7QI/D aWS/E3FgPxsg4rFy1dMxNQ1g5mUd7KrsH8G3ge7+nVg7RYE0zQvJYRa+Jw9I0TxebV+3 +ugQyGrZKSyWAptVDCd+gvrvx+02NqFAkFincnAknp4ndX9vfFX0ITwivaT8n28v9qaj UdeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007221; x=1729612021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DIdGHos2kceOOOIgzSCtXbavAnuw+Mxycbvbjx7Wmpw=; b=WUCJ48lzGMuZvm+oyt76/vNQ0Rj9plfsi5Ys6KCsDU3FIeVYzEEZX3FkJ0e25L0dib iN8aX9Rco2ynxckz00gYLeykPCTe4kqj60aoVAcBw1ctO36LwKDBVnhTExV3k9K9n5hK pVflnIiHnR24zfxA0yupYL5uVjWJ5c6dBajm58OdhEc5ih0zrfzYakyM+pm2hhpfQzLH t0JiFkmMaxbTCQpLOIenQ8ec2GLb7ECheHG5B2cmPC4+mlBdhaLhjwBUEs1YtfdQ9yHY sHgL8dMf9gW2ojZkXDRILTTcRpqoTihmTXGf+E8NJQaoANqmfLbRZ0nLmmvnZSrNrGr2 DLRg== X-Gm-Message-State: AOJu0Yw7+GPtLcvfnxhEobyntaH4DsjLVW5L3pc7rWC8f92wrYiAOSUi IN9hVO3fAwXdBrBrnESGEvDsD5ZEe2ftjJyzOzYGgOZop3Ke/1OVmyFJ15d8tkEupSJe5SHYVp6 I X-Google-Smtp-Source: AGHT+IGnQ9w3Vdc2tRELiZt2y5uf6zP6f/6pQjG9xa6Tu6Tr1CM9eRpSOfJMTVYqqJWM5JtXHqwK/Q== X-Received: by 2002:a17:90a:ae0b:b0:2e2:b514:ca1 with SMTP id 98e67ed59e1d1-2e3151b78b6mr16398981a91.6.1729007220903; Tue, 15 Oct 2024 08:47:00 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e392e8cf1csm1957605a91.6.2024.10.15.08.46.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 19/33] target/mips: Introduce mo_endian_env() helper Date: Tue, 15 Oct 2024 12:44:28 -0300 Message-ID: <20241015154443.71763-20-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=philmd@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce mo_endian_env() which returns the endian MemOp corresponding to the vCPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-4-philmd@linaro.org> --- target/mips/internal.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/internal.h b/target/mips/internal.h index 84c8e5e1ae7..91c786cff8a 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -230,6 +230,11 @@ static inline bool mips_env_is_bigendian(CPUMIPSState *env) return extract32(env->CP0_Config0, CP0C0_BE, 1); } +static inline MemOp mo_endian_env(CPUMIPSState *env) +{ + return mips_env_is_bigendian(env) ? MO_BE : MO_LE; +} + static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { From patchwork Tue Oct 15 15:44:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2911ED1D87B for ; Tue, 15 Oct 2024 15:47:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlY-0004rw-SD; Tue, 15 Oct 2024 11:47:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jlP-0004NI-NG for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:11 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jlN-0000zA-GJ for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:10 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-20b5affde14so34058195ad.3 for ; Tue, 15 Oct 2024 08:47:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007228; x=1729612028; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LBs9jz8Noj8v7jUvWI495axiHObd3uNNAVFIb2VRWYI=; b=RvgUw0khACxFqevrOmcgS92Q3GisCIGyNCFztVIVCbC6JXPywse74i90a184T4Aqsu cy3P1QrzroEXZ9M1GfJ2+ZFE9WrarZDaXJ0VSg43g0mxdozGbVyvWeqiPkRYm50nw2ZZ rgTzo8N2nCcTCbjo1dOmrqXq+C2H6AUx79lCNSgqR+3YxtjdYOr8ivV6yRu8PWTkWz1A K0fpCI71HOwaAQPzcVjLVHAqRkI5Q7Hatxx2NZ5aD3k2x2vih0lK8ozL1XO/ahaaGVv/ d+SLxjzxUKx6JdFnlUjqF26RmpBl99r5cUOXlv/wmovzscd0oT7bIXmGTZ3f+XE9CxZ3 fbmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007228; x=1729612028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LBs9jz8Noj8v7jUvWI495axiHObd3uNNAVFIb2VRWYI=; b=j9wQ+ezh9YqXX1ewJaRrNiIBSojzglRgc0Y7AgMQ6vc7sPdhdUtcg+8fTZGtOt7n9M 7uPd3207DvcoZF4HwnUxwzsZDb7ndmG2a/s9EvmG6XkPw87IZlWB9EDGyOO29/Dtvbo7 GnFqoXgi8UEkQ0ht1LNoe5xvVc9WoscBijqwPV0/nAKVz+nMud20bHmcNtBIZOLhjuAK rzeQ14IZzy2rwKn9yWE+NZvJrYb/1C66A+km6bIZ9F+vLFrA3YwDhEOe8k9HHEDwxOG8 r4HzejFeH+bcvT3lB2vXoch83yinc8iyiClqhP10JE6yhmZOVtSeZRTmcHzsdptWAgyb gpRQ== X-Gm-Message-State: AOJu0Yy+eSCt+6FP4KE/aP1undH/1hV9TJc9gLP0Ki1FkAYu5vqGKy+X +pT+OcwIQNTc56nAyZCSlThN87JVPv01m8rw1iKjdlxJHxHzWBErNwwFPsyFExbspBppeJP/o4W U X-Google-Smtp-Source: AGHT+IHmThAZj0IkdllI/xICeINoeZBTbsKb8AIDkdZH3gRjB7r6uM4yUSYNsovzIm1VWs0S2pQVUw== X-Received: by 2002:a17:902:e752:b0:20c:f39e:4c15 with SMTP id d9443c01a7336-20d27ec931dmr9553815ad.22.1729007227996; Tue, 15 Oct 2024 08:47:07 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b67dsm13523355ad.195.2024.10.15.08.47.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 20/33] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Date: Tue, 15 Oct 2024 12:44:29 -0300 Message-ID: <20241015154443.71763-21-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace compile-time MO_TE evaluation by runtime mo_endian_env() one, which expand target endianness from vCPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-5-philmd@linaro.org> --- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 3836137750e..e98bb959517 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -601,7 +601,7 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op, return false; } - oi = make_memop_idx(op | MO_TE, ptw_mmu_idx); + oi = make_memop_idx(op | mo_endian_env(env), ptw_mmu_idx); if (op == MO_64) { *pte = cpu_ldq_mmu(env, vaddr, oi, 0); } else { From patchwork Tue Oct 15 15:44:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9F5DD1D882 for ; Tue, 15 Oct 2024 15:47:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jle-0005NI-5t; Tue, 15 Oct 2024 11:47:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jlW-0004sM-Or for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:19 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jlU-00010W-U8 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:18 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-71e3fce4a60so2832827b3a.0 for ; Tue, 15 Oct 2024 08:47:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007235; x=1729612035; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e10gg62bVZR218Yi+lSWU64iaPNDemXQBedt5af7g0A=; b=OnVOx5ldc1JcdM4L2Rnon4BAA3sJRrMqq1LFnhNprLdLt2CMXWwjZKGnE6Mp/7zZ/w xzIQWe/xoiSfQBJqAKpgnGkjAPfHx5erTkhiZno6YqNTIIDOIrkGIwuq16IHJ3e8ccOd EO24xiSf2Gjl5jTbZnr0gzklrws+7cF+0cLpiB1h6VezRhEiJHD/esnrYUlXhug9rBPL kPuX2gHyP6PALx/4VxUgxm30+n8AzUaCeiWTSxeFZh9vrOdi2AVqlXg/jnpol0b8P0HD nTphx8BCyG9QeVDVUpXC3AAC3OWKaCZTL5u9EnooqbO5QATtdiWWMaeW7ZgEKgpV5nuU TBUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007235; x=1729612035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e10gg62bVZR218Yi+lSWU64iaPNDemXQBedt5af7g0A=; b=T5BV1BGcnr56XOq6YxLcrW1KT9aR0ZlXKNbVr1Y5EFNSy0iMdybHCZxqu7elz4XuhN /BMXzlP67Y8W4PXX8eMsgqVBCt8lORonnnxGcGZk9SIQ0ZAsEsAScF0p2xZ0jWFeFerq FEy058jBALLi+3FRNu8c+Dtv2fSiZtfO2s2fNuqMWyJCair8nuU1TZqIEQ3ppcwB1XfU k/OMmxCqkDG9oi9wwDmU6qiZh06QTDf8GMf3ajHwn2ll7Duxte+bG8dO5sWhuFJjngfG 12NuilqlV9sd2UY081EhM8Gj1OtxXyXF8qMLv65ANsutzcf9Otc6owb4c0X6i1ry7mgd VNuA== X-Gm-Message-State: AOJu0YwxyPwIDA9+ohQ4qfhmd/5NFpkN5pWpXZ1rUA+XK99v6nI0leq0 fA4Ub6I1UyY0sYJrcrixpW/hazk7YD6/KF19LWyRwkHH/dx+jWSjglIYtVHTQyZA87Y4iccfzJw 3 X-Google-Smtp-Source: AGHT+IFLJZ8vUemhdWtsGqnmEZti9p3l/91aeBAnw9CJlYOaZmJIkDpo/P8ENyCG9uwUU3UdpjbN8A== X-Received: by 2002:a05:6a00:3392:b0:710:5848:8ae1 with SMTP id d2e1a72fcca58-71e7da10f78mr1179926b3a.4.1729007235181; Tue, 15 Oct 2024 08:47:15 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e774cc2c7sm1410866b3a.164.2024.10.15.08.47.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 21/33] target/mips: Convert mips16e decr_and_load/store() macros to functions Date: Tue, 15 Oct 2024 12:44:30 -0300 Message-ID: <20241015154443.71763-22-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Functions are easier to rework than macros. Besides, there is no gain here in inlining these. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-6-philmd@linaro.org> --- target/mips/tcg/mips16e_translate.c.inc | 101 +++++++++++++----------- 1 file changed, 53 insertions(+), 48 deletions(-) diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index 5cffe0e412d..cabc17345f4 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -122,11 +122,23 @@ enum { static int xlat(int r) { - static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; return map[r]; } +static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0) +{ + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + tcg_gen_movi_tl(t2, -4); + gen_op_addr_add(ctx, t0, t0, t2); + gen_load_gpr(t1, regidx); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); +} + static void gen_mips16_save(DisasContext *ctx, int xsregs, int aregs, int do_ra, int do_s0, int do_s1, @@ -196,46 +208,38 @@ static void gen_mips16_save(DisasContext *ctx, gen_load_gpr(t0, 29); -#define DECR_AND_STORE(reg) do { \ - tcg_gen_movi_tl(t2, -4); \ - gen_op_addr_add(ctx, t0, t0, t2); \ - gen_load_gpr(t1, reg); \ - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \ - ctx->default_tcg_memop_mask); \ - } while (0) - if (do_ra) { - DECR_AND_STORE(31); + decr_and_store(ctx, 31, t0); } switch (xsregs) { case 7: - DECR_AND_STORE(30); + decr_and_store(ctx, 30, t0); /* Fall through */ case 6: - DECR_AND_STORE(23); + decr_and_store(ctx, 23, t0); /* Fall through */ case 5: - DECR_AND_STORE(22); + decr_and_store(ctx, 22, t0); /* Fall through */ case 4: - DECR_AND_STORE(21); + decr_and_store(ctx, 21, t0); /* Fall through */ case 3: - DECR_AND_STORE(20); + decr_and_store(ctx, 20, t0); /* Fall through */ case 2: - DECR_AND_STORE(19); + decr_and_store(ctx, 19, t0); /* Fall through */ case 1: - DECR_AND_STORE(18); + decr_and_store(ctx, 18, t0); } if (do_s1) { - DECR_AND_STORE(17); + decr_and_store(ctx, 17, t0); } if (do_s0) { - DECR_AND_STORE(16); + decr_and_store(ctx, 16, t0); } switch (aregs) { @@ -270,23 +274,34 @@ static void gen_mips16_save(DisasContext *ctx, } if (astatic > 0) { - DECR_AND_STORE(7); + decr_and_store(ctx, 7, t0); if (astatic > 1) { - DECR_AND_STORE(6); + decr_and_store(ctx, 6, t0); if (astatic > 2) { - DECR_AND_STORE(5); + decr_and_store(ctx, 5, t0); if (astatic > 3) { - DECR_AND_STORE(4); + decr_and_store(ctx, 4, t0); } } } } -#undef DECR_AND_STORE tcg_gen_movi_tl(t2, -framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); } +static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0) +{ + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + tcg_gen_movi_tl(t2, -4); + gen_op_addr_add(ctx, t0, t0, t2); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); + gen_store_gpr(t1, regidx); +} + static void gen_mips16_restore(DisasContext *ctx, int xsregs, int aregs, int do_ra, int do_s0, int do_s1, @@ -294,52 +309,43 @@ static void gen_mips16_restore(DisasContext *ctx, { int astatic; TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); TCGv t2 = tcg_temp_new(); tcg_gen_movi_tl(t2, framesize); gen_op_addr_add(ctx, t0, cpu_gpr[29], t2); -#define DECR_AND_LOAD(reg) do { \ - tcg_gen_movi_tl(t2, -4); \ - gen_op_addr_add(ctx, t0, t0, t2); \ - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \ - ctx->default_tcg_memop_mask); \ - gen_store_gpr(t1, reg); \ - } while (0) - if (do_ra) { - DECR_AND_LOAD(31); + decr_and_load(ctx, 31, t0); } switch (xsregs) { case 7: - DECR_AND_LOAD(30); + decr_and_load(ctx, 30, t0); /* Fall through */ case 6: - DECR_AND_LOAD(23); + decr_and_load(ctx, 23, t0); /* Fall through */ case 5: - DECR_AND_LOAD(22); + decr_and_load(ctx, 22, t0); /* Fall through */ case 4: - DECR_AND_LOAD(21); + decr_and_load(ctx, 21, t0); /* Fall through */ case 3: - DECR_AND_LOAD(20); + decr_and_load(ctx, 20, t0); /* Fall through */ case 2: - DECR_AND_LOAD(19); + decr_and_load(ctx, 19, t0); /* Fall through */ case 1: - DECR_AND_LOAD(18); + decr_and_load(ctx, 18, t0); } if (do_s1) { - DECR_AND_LOAD(17); + decr_and_load(ctx, 17, t0); } if (do_s0) { - DECR_AND_LOAD(16); + decr_and_load(ctx, 16, t0); } switch (aregs) { @@ -374,18 +380,17 @@ static void gen_mips16_restore(DisasContext *ctx, } if (astatic > 0) { - DECR_AND_LOAD(7); + decr_and_load(ctx, 7, t0); if (astatic > 1) { - DECR_AND_LOAD(6); + decr_and_load(ctx, 6, t0); if (astatic > 2) { - DECR_AND_LOAD(5); + decr_and_load(ctx, 5, t0); if (astatic > 3) { - DECR_AND_LOAD(4); + decr_and_load(ctx, 4, t0); } } } } -#undef DECR_AND_LOAD tcg_gen_movi_tl(t2, framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); From patchwork Tue Oct 15 15:44:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4227D1D87B for ; Tue, 15 Oct 2024 15:47:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlg-0005fp-A2; Tue, 15 Oct 2024 11:47:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jld-0005Gt-76 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:25 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jlb-00011E-GY for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:24 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-71e4e481692so3060990b3a.1 for ; Tue, 15 Oct 2024 08:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007242; x=1729612042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xGnol72aGQVf38Y6d7/nrQevxwXxOL9LU8zx2/PrN8w=; b=DZn2+7GeMYmDdOaPCfNnsnWRtaFGnpsCg3DgBCNAlsZBnS1OaPGOl+OHNmAu36ewBr pYR/G8u7hmay5OHwUUiwBRs0OvPaZHtluiDStCgV7AE9peReNG99bYOWgPA6iURk/5uD P+6fyNLqRkRtA9lThd73h8LMqrejfzmvAJbCDbqZDxD4yA+C85xF8Nhy10Bpevx258+k JA7hAuqFiePUZISYoomTlA9ZDrRuIvokFuw03xdQp41nAUIpra3j/cGO0YXh9NL2xU8a QNcV1GqeS0LaoG74QnwBUfhCB/xVg/BoYzCERhHNOsUGL5du/7zWd50YdxMvA7v/82xt NQrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007242; x=1729612042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xGnol72aGQVf38Y6d7/nrQevxwXxOL9LU8zx2/PrN8w=; b=BE/OrjFfdn2nn6l8eE69LNs+/qFl82NpgmAjqeqwmhiW3uBIViLGAP5t1vxHnpm+L3 BVTzc8fUdhRU/YHAMYy9oDqfRLObwptDoAuwdFxFFQc5jP/mtesTCWnfvE0mRpkomdq5 w2dcR2TEzPCrC/B8g1z0Yl6GBbwjsbftIySUCJzfU1RLgC4qVFTOsTUDu+kO2EVnksPS eqnAavEQGReavhb28R3Xjhsc6qyX+eU4yNTTVqBJ7Az5LZhVTBYqNE7djtANmNVf2mOy xXXP3pdb8ZKeA0ADSEqqSxlfJAvGCy7ciwXP/hmeoef1AKnaHXDkY+BZ07eLEB0c0urJ k7Pg== X-Gm-Message-State: AOJu0Yzf4QyTut/Xnlo62DJo3Z/oe551DYs3obn0wirRT5V6vOHJlQI+ CBvNcKDn5kDaPeompwowWAP92bSF2USAxRvv5Q0vYIwh8HOrepcZEsHLjuTBbA35yS7l5oZYFti R X-Google-Smtp-Source: AGHT+IHlWgmtdgOP19ho1QqJ7f9QRhwvRXMd3xzuNc3tSk3+5+JGdhgahsJSi6wT4eLZis6I2wJmIw== X-Received: by 2002:a05:6a20:e613:b0:1cf:4679:9b97 with SMTP id adf61e73a8af0-1d8c969991cmr14944384637.37.1729007241956; Tue, 15 Oct 2024 08:47:21 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e774a41afsm1412231b3a.113.2024.10.15.08.47.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 22/33] target/mips: Factor mo_endian_rev() out of MXU code Date: Tue, 15 Oct 2024 12:44:31 -0300 Message-ID: <20241015154443.71763-23-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of swapping the reversed target endianness using MO_BSWAP, directly return the correct endianness. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-7-philmd@linaro.org> --- target/mips/tcg/translate.h | 5 +++++ target/mips/tcg/mxu_translate.c | 8 ++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index e81a8d5eb9b..c55f90e741b 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -240,4 +240,9 @@ static inline bool disas_is_bigendian(DisasContext *ctx) return extract32(ctx->CP0_Config0, CP0C0_BE, 1); } +static inline MemOp mo_endian_rev(DisasContext *dc, bool reversed) +{ + return disas_is_bigendian(dc) ^ reversed ? MO_BE : MO_LE; +} + #endif diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index c517258ac5a..dd512ce7a48 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -1533,7 +1533,7 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc) tcg_gen_add_tl(t0, t0, t1); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + MO_SL | mo_endian_rev(ctx, reversed) | ctx->default_tcg_memop_mask); gen_store_mxu_gpr(t1, XRa); @@ -1569,7 +1569,7 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc) gen_load_mxu_gpr(t1, XRa); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + MO_SL | mo_endian_rev(ctx, reversed) | ctx->default_tcg_memop_mask); if (postinc) { @@ -1605,7 +1605,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed, tcg_gen_add_tl(t0, t0, t1); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + MO_SL | mo_endian_rev(ctx, reversed) | ctx->default_tcg_memop_mask); gen_store_mxu_gpr(t1, XRa); @@ -1675,7 +1675,7 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed, gen_load_mxu_gpr(t1, XRa); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - (MO_TESL ^ (reversed ? MO_BSWAP : 0)) | + MO_SL | mo_endian_rev(ctx, reversed) | ctx->default_tcg_memop_mask); if (postinc) { From patchwork Tue Oct 15 15:44:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22FBACFC27C for ; Tue, 15 Oct 2024 15:50:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jls-0006bo-5o; Tue, 15 Oct 2024 11:47:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jln-0006MH-15 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:35 -0400 Received: from mail-il1-x135.google.com ([2607:f8b0:4864:20::135]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jlj-00011l-8b for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:34 -0400 Received: by mail-il1-x135.google.com with SMTP id e9e14a558f8ab-3a3a5cd2a3bso30760115ab.3 for ; Tue, 15 Oct 2024 08:47:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007249; x=1729612049; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6YijR6TT6pBCn2XLXqfhKFaqvpl42j47NCZwcHKcJxE=; b=FSw8PWt4i2jhmk4fDhHBPpAb2AQzFNKb69H5rZDjpOZ/AoejfViuDIu//eMX/7G/kg TnEtGK5f7AiAe0bJU5Q23O0TLzWLnz0CAGLWYIiUTewlSR8t4iJZvHVAcUKvurYFllkR IoGLN7Saw/8QVMdGZ8v06C1cuEsp0kOKoXtvbBPRA7yFGFio8Z6AeyCwtIA6wORGzme6 BCge6ociBKOjNXKxqGhKEYFnNRE8W/YKz7Y8kpM2kpMQh/wy0m+/OqLFw0klQWUdupgg bGHcaklRuPkWSDWsr3avUAqwrLX9gzd8r+TjIbCr8HnnzMtuBcNpqklkwPGNGxoLFNpf msRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007249; x=1729612049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6YijR6TT6pBCn2XLXqfhKFaqvpl42j47NCZwcHKcJxE=; b=XNDMKMfl4hTTGTnATLj1Jft36rS7TnoFDKna8QYnmqa0dm0IQj1EpzBZYT9BS0ZsdQ 95gg+xdX1/GdZN40HeXlAktEP17sFo4cZrTxulETqMAG0sKlyVQX9gcDKMgiRSweebBa OgiOkzUprHidpaZBa6gr+32hIIugkDcecBRrWvP7cH8cUdMIdv3OcP+Ld0ewoAJAidmP NZF41VYnj+1FRvSzhQ+8lz+9EAUaS474Jb1AAI1VfC033W7W3IPMi+hPn31ua34wz9iE JjWpdk5kSoIosRHZeFXmKeEvPAX+AedwcWjpehpc3le+08ZWFTvP7HKVBP5tIjcSIbsm dwSA== X-Gm-Message-State: AOJu0YwJpmtzbgc5jLCCWAfXHhqFx4zOXHJrDPxsFcXNSYpBo7UUbAsc r7tXVhQLDfh9ynsegqQuB/eapd0p7YDQ/vzUudBnzcz9l4gGqPsWQn8aqtYRtX+yPkEC+f5F13t U X-Google-Smtp-Source: AGHT+IG7P3p6En+0+QE8ZjqLd4USx+4xKjrLz4O/77IjURK0wNmsWkBUtinSfF6jCsUQ3j0unzLW0w== X-Received: by 2002:a05:6e02:b48:b0:3a3:97b6:74e6 with SMTP id e9e14a558f8ab-3a3dc4a9b22mr10397235ab.8.1729007249141; Tue, 15 Oct 2024 08:47:29 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ea9c6d2b56sm1508702a12.43.2024.10.15.08.47.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 23/33] target/mips: Explode MO_TExx -> MO_TE | MO_xx Date: Tue, 15 Oct 2024 12:44:32 -0300 Message-ID: <20241015154443.71763-24-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-il1-x135.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/mips); \ done manually remove superfluous parenthesis in nanoMIPS gen_save(). Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-8-philmd@linaro.org> --- target/mips/tcg/translate.c | 120 +++++++++++----------- target/mips/tcg/tx79_translate.c | 8 +- target/mips/tcg/micromips_translate.c.inc | 22 ++-- target/mips/tcg/mips16e_translate.c.inc | 10 +- target/mips/tcg/nanomips_translate.c.inc | 38 +++---- 5 files changed, 100 insertions(+), 98 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 3deb48ace9d..6f047d6069a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \ } #endif -OP_LD_ATOMIC(ll, MO_TESL); +OP_LD_ATOMIC(ll, MO_TE | MO_SL); #if defined(TARGET_MIPS64) -OP_LD_ATOMIC(lld, MO_TEUQ); +OP_LD_ATOMIC(lld, MO_TE | MO_UQ); #endif #undef OP_LD_ATOMIC @@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, switch (opc) { #if defined(TARGET_MIPS64) case OPC_LWU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; case OPC_LD: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LDL: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ); + gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDR: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ); + gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDPC: t1 = tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ); gen_store_gpr(t0, rt); break; #endif case OPC_LWPC: t1 = tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL); gen_store_gpr(t0, rt); break; case OPC_LWE: mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_LW: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_LH: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_LHU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWL: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL); + gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWR: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL); + gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt, switch (opc) { #if defined(TARGET_MIPS64) case OPC_SD: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_SDL: @@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt, mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_SW: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; case OPC_SHE: mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_SH: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_SBE: @@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, case OPC_LWC1: { TCGv_i32 fp0 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, ft); } @@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, ft); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); } break; case OPC_LDC1: { TCGv_i64 fp0 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, fp0, ft); } @@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, ft); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); } break; @@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, case R6_OPC_LWPC: offset = sextract32(ctx->opcode << 2, 0, 21); addr = addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL); + gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL); break; #if defined(TARGET_MIPS64) case OPC_LWUPC: check_mips_64(ctx); offset = sextract32(ctx->opcode << 2, 0, 21); addr = addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL); + gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL); break; #endif default: @@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, check_mips_64(ctx); offset = sextract32(ctx->opcode << 3, 0, 21); addr = addr_add(ctx, (pc & ~0x7), offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ); + gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ); break; #endif default: @@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, case OPC_GSLQ: t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rt); gen_store_gpr(t0, lsq_rt1); @@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, check_cp1_enabled(ctx); t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t0, lsq_rt1); @@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_gpr(t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_GSSQC1: @@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_fpr64(ctx, t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_fpr32(ctx, fp0, rt); t1 = tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL); + gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_fpr32(ctx, fp0, rt); t1 = tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL); + gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 = tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); + gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; case OPC_GSLDRC1: @@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 = tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); + gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; #endif @@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, gen_store_gpr(t0, rt); break; case OPC_GSLHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } fp0 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, rt); break; @@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t0, rt); break; @@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, case OPC_GSSHX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_GSSWX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif case OPC_GSSWXC1: fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, rt); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDXC1: t1 = tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i32 fp0 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fd); } @@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, check_cp1_registers(ctx, fd); { TCGv_i64 fp0 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i64 fp0 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL); } break; case OPC_SDXC1: @@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); } break; case OPC_SUXC1: @@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); } break; } @@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd) gen_op_addr_add(ctx, t0, t1, t0); } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL); gen_store_gpr(t1, rd); } @@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rd); break; case OPC_LHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW); gen_store_gpr(t0, rd); break; case OPC_LWX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); gen_store_gpr(t0, rd); break; #if defined(TARGET_MIPS64) case OPC_LDX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ); gen_store_gpr(t0, rd); break; #endif @@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) } break; case R6_OPC_SC: - gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); break; case R6_OPC_LL: gen_ld(ctx, op1, rt, rs, imm); @@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) #endif #if defined(TARGET_MIPS64) case R6_OPC_SCD: - gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); break; case R6_OPC_LLD: gen_ld(ctx, op1, rt, rs, imm); @@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) return; case OPC_SCE: check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true); return; case OPC_CACHEE: check_eva(ctx); @@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } - gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); break; case OPC_CACHE: check_cp0_enabled(ctx); @@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) check_insn_opc_user_only(ctx, INSN_R5900); } check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); + gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ if (ctx->insn_flags & ISA_MIPS_R6) { diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index dd6fb8a7bd7..1d290b86a98 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) tcg_gen_andi_tl(addr, addr, ~0xf); /* Lower half */ - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); gen_store_gpr(t0, a->rt); /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); gen_store_gpr_hi(t0, a->rt); return true; } @@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a) /* Lower half */ gen_load_gpr(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); gen_load_gpr_hi(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); return true; } diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 75108317019..343d64a0e85 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SWP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; #ifdef TARGET_MIPS64 @@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SDP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, offset); break; case SC: - gen_st_cond(ctx, rt, rs, offset, MO_TESL, false); + gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false); break; #if defined(TARGET_MIPS64) case SCD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, offset, MO_TEUQ, false); + gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false); break; #endif case LD_EVA: @@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) mips32_op = OPC_SHE; goto do_st_lr; case SCE: - gen_st_cond(ctx, rt, rs, offset, MO_TESL, true); + gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true); break; case SWE: mips32_op = OPC_SWE; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index cabc17345f4..f80d35225e8 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0) tcg_gen_movi_tl(t2, -4); gen_op_addr_add(ctx, t0, t0, t2); gen_load_gpr(t1, regidx); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); } @@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx, case 4: gen_base_offset_addr(ctx, t0, 29, 12); gen_load_gpr(t1, 7); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 3: gen_base_offset_addr(ctx, t0, 29, 8); gen_load_gpr(t1, 6); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 2: gen_base_offset_addr(ctx, t0, 29, 4); gen_load_gpr(t1, 5); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 1: gen_base_offset_addr(ctx, t0, 29, 0); gen_load_gpr(t1, 4); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | ctx->default_tcg_memop_mask); } diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 6e0df1a8c36..06204585f23 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, TCGv tmp2 = tcg_temp_new(); gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIGN); if (disas_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { @@ -1075,7 +1075,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count, gen_base_offset_addr(ctx, va, 29, this_offset); gen_load_gpr(t0, this_rt); tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, - (MO_TEUL | ctx->default_tcg_memop_mask)); + MO_TE | MO_UL | ctx->default_tcg_memop_mask); counter++; } @@ -1095,7 +1095,7 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); int this_offset = u - ((counter + 1) << 2); gen_base_offset_addr(ctx, va, 29, this_offset); - tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, this_rt); @@ -2647,13 +2647,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) case NM_LHX: /*case NM_LHXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TESW | ctx->default_tcg_memop_mask); + MO_TE | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LWX: /*case NM_LWXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TESL | ctx->default_tcg_memop_mask); + MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LBUX: @@ -2663,7 +2663,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) case NM_LHUX: /*case NM_LHUXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TEUW | ctx->default_tcg_memop_mask); + MO_TE | MO_UW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_SBX: @@ -2676,14 +2676,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUW | ctx->default_tcg_memop_mask); + MO_TE | MO_UW | ctx->default_tcg_memop_mask); break; case NM_SWX: /*case NM_SWXS:*/ check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUL | ctx->default_tcg_memop_mask); + MO_TE | MO_UL | ctx->default_tcg_memop_mask); break; case NM_LWC1X: /*case NM_LWC1XS:*/ @@ -3737,7 +3737,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) tcg_gen_movi_tl(t0, addr); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, - MO_TESL | ctx->default_tcg_memop_mask); + MO_TE | MO_SL + | ctx->default_tcg_memop_mask); } break; case NM_SWPC48: @@ -3754,7 +3755,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUL | ctx->default_tcg_memop_mask); + MO_TE | MO_UL + | ctx->default_tcg_memop_mask); } break; default: @@ -4132,14 +4134,14 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) switch (extract32(ctx->opcode, 11, 4)) { case NM_UALH: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | - MO_UNALN); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, + MO_TE | MO_SW | MO_UNALN); gen_store_gpr(t0, rt); break; case NM_UASH: gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | - MO_UNALN); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_TE | MO_UW | MO_UNALN); break; } } @@ -4161,7 +4163,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_P_SC: switch (ctx->opcode & 0x03) { case NM_SC: - gen_st_cond(ctx, rt, rs, s, MO_TESL, false); + gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false); break; case NM_SCWP: check_xnp(ctx); @@ -4274,7 +4276,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_xnp(ctx); check_eva(ctx); check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, s, MO_TESL, true); + gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true); break; case NM_SCWPE: check_xnp(ctx); @@ -4317,7 +4319,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) switch (extract32(ctx->opcode, 11, 1)) { case NM_LWM: tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx, - memop | MO_TESL); + memop | MO_TE | MO_SL); gen_store_gpr(t1, this_rt); if ((this_rt == rs) && (counter != (count - 1))) { @@ -4328,7 +4330,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) this_rt = (rt == 0) ? 0 : this_rt; gen_load_gpr(t1, this_rt); tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx, - memop | MO_TEUL); + memop | MO_TE | MO_UL); break; } counter++; From patchwork Tue Oct 15 15:44:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A303D1D87B for ; Tue, 15 Oct 2024 15:48:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jlx-0006nd-D7; Tue, 15 Oct 2024 11:47:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jlr-0006c5-B5 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:40 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jlp-00012P-OJ for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:39 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-20caccadbeeso41651395ad.2 for ; Tue, 15 Oct 2024 08:47:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007256; x=1729612056; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TLrx6EmGTvRMia9SJl0yo7FPDa0fQJjS3ptDOLc8dGQ=; b=qP3P2GJ3F0nVU/+2ahcZtarhQ6JASmY4Ff4T5poJ+Km4+fkCyjJmZfbMuTpF0Mrltr b/8vMfNzRM5w9wVnpm0k0rbR9SDWzsruz5JJ90rK/UO30MFNEfSWWp8nJC5zSkPgXDe3 HGMxBCv8SknXDoNG3X5L1sJaj13TGQpq/mdfJD9OKeQjuX3YKQH7ZrOGmSQHSqRU8tnN rerxy9oXozUH9zqM7T5xx1EVkiw/bUqjDwS/S+qQxw57aiDilNZ6HiDymsZiLBlYnbz7 RsxDXA87MxNUj1qf9b4dAYrKnRjsnkrHRICk7uepLLwH23ZXvweCSKHRrDJyiwPxhrU5 J+Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007256; x=1729612056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TLrx6EmGTvRMia9SJl0yo7FPDa0fQJjS3ptDOLc8dGQ=; b=Kj6ZgalO1mxjUnSmNK/p1YsC956nuEvCaLQ90n8ypM4ZSdkYwGmDwXZ1V/qjrtg3zw GiyNjp1YRBgV+gfBDIL6lsjlTOIy1QRYSwTVa6lURwc30fBO/gdLokB++KdRcaJItwXj KYu44R7lnxL4AGv4eHFoSr2zQIu/7WpajjAEKPYjUuuBKobidndrUgdJYmXNzKs3PUY0 PihclYZkgDV7Fevg7AHtRZVM51oiP3ft585CJdpxVxl6+gvH9ev0UmwiTK0X4E+VkEfB HSf/1MypPNNg+0XfCZX0wmzWyzsWOcgRQx6V0sNOCZ5NvhfNj9EKw/YnOfy5BgCEYsgy XJOA== X-Gm-Message-State: AOJu0YyjOewy038aLpzaTWau950iuJsonksjaKd29GeQeAojKzy6rUl7 wa5axDAaggx/eN/JWqj2EJ6vE9g+SvVtFF9Vt1/dehcKsGV7USCyKBo1ff4sXKFn4aG9jK8P75d f X-Google-Smtp-Source: AGHT+IEPYGVhaHR3UOQ0OYfQPJLREiwux6vCRx1U5/EnPsydQBhqCiPNjzM7XOamrxVLZAjlUwBlug== X-Received: by 2002:a17:902:ea0e:b0:20c:bcf1:c70e with SMTP id d9443c01a7336-20cbcf1f8a1mr148488305ad.13.1729007256109; Tue, 15 Oct 2024 08:47:36 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b5e5sm13561495ad.197.2024.10.15.08.47.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 24/33] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() Date: Tue, 15 Oct 2024 12:44:33 -0300 Message-ID: <20241015154443.71763-25-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In commit 6d0cad12594 ("target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*") we renamed the argument of the user definition. Rename the system part for coherency. Since the argument is ignored, prefix with 'ignored_'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-9-philmd@linaro.org> --- target/mips/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6f047d6069a..6ba8371658c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1957,7 +1957,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \ } #else -#define OP_LD_ATOMIC(insn, fname) \ +#define OP_LD_ATOMIC(insn, ignored_memop) \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ DisasContext *ctx) \ { \ From patchwork Tue Oct 15 15:44:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52744D1D87B for ; Tue, 15 Oct 2024 15:47:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jm2-0007Tp-Qh; Tue, 15 Oct 2024 11:47:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jlz-00075x-6u for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:47 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jlx-00013Q-EU for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:46 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-208cf673b8dso58407425ad.3 for ; Tue, 15 Oct 2024 08:47:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007264; x=1729612064; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FYXizewLL7ilBr1Rp+xOggMM2d6Y9oiIIvLHYNQfqQw=; b=x41xV7DTaoM2zY3/4Ud01/O6eacrikT+Q6C+CTNcRjfugEtiAZyEHeC+lTfNPwPbBi 1dpWJr4DTNHlIuCCt8gAh/BoH5OhVqfDI6VjUQ5UQlQHXq/nD/xSZ18msl/8+c4y51v9 WSifYhda8AZv6b8AEtlUviY2qJbNcjugu7HYxDpW4YSkoX9mLqnIilN51XAzuaQtPB61 etvDpGzKgWN6pU8hVzJFv42rxEOhNIbAtY9Rv1HixfjZIBUQqKwO6lyxtPgWcpA7Qejt 2HI47O5BLyzBqjmSi4LRhJCQFVWsvSygx61qkch8YAILOA6TifDU6DDeQ89sotqxGAxQ xyRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007264; x=1729612064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FYXizewLL7ilBr1Rp+xOggMM2d6Y9oiIIvLHYNQfqQw=; b=hP89Za9yfp1FxbIqMo9R+YvX7tZ+6gbXLgAY1NaX2OS2rsg6OBE8DOISWDK6i9v8pr A5tYI3qQoc3kwZx/WfgTwdx+deM454VtTH+kodo7pooPnsT2W0/cR/LBDHDohj2/3tTv 6Hrp6oO8dW4ikveHQYLMO2xaoNvF0CNFi7LKtdcNawFEdKc/pjVeAH3VE84i/ZjGSj37 ObTJXRgtXisP9YB0zHGPbB+PhxtenP2Ftp//f1r9PYkQtalOqqFVgQOyQyKVIevimShM HhDOafoQHSMa5jElBB7vZj/UObk2lsZRVLYlh371QTv31h5EEQIjRCnh1sYIIMBm+AiF lMkw== X-Gm-Message-State: AOJu0YwBOgx6izToHBGDO4Q4XR3VFQaOomt8EqB4/XefCEFCefcjUj/B pyt0Z8V3Wl0nFX9S39J48KHCc3YMkvZC3zSXxfpaF7IfCLd1/gv3qDK3psjl5FEmh9gMkD6gHiC l X-Google-Smtp-Source: AGHT+IGqQhLi7dQ4HbQJlSiDRI9jBRrGCC06AFCm1HbYQiBGP6ghDXTPSmL3g3zM6lT2bPijwL3J/g== X-Received: by 2002:a17:902:f78b:b0:206:aac4:b844 with SMTP id d9443c01a7336-20d27e59c0bmr12439765ad.6.1729007263737; Tue, 15 Oct 2024 08:47:43 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1807100asm13470765ad.304.2024.10.15.08.47.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 25/33] target/mips: Remove unused MEMOP_IDX() macro Date: Tue, 15 Oct 2024 12:44:34 -0300 Message-ID: <20241015154443.71763-26-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org MEMOP_IDX() is unused since commit 948f88661c6 ("target/mips: Use cpu_*_data_ra for msa load/store"), remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241014232235.51988-1-philmd@linaro.org> --- target/mips/tcg/msa_helper.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index d2181763e72..1d40383ca4f 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8211,14 +8211,6 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, /* Element-by-element access macros */ #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) -#if !defined(CONFIG_USER_ONLY) -#define MEMOP_IDX(DF) \ - MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \ - mips_env_mmu_index(env)); -#else -#define MEMOP_IDX(DF) -#endif - #if TARGET_BIG_ENDIAN static inline uint64_t bswap16x4(uint64_t x) { From patchwork Tue Oct 15 15:44:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64B07CFC27C for ; Tue, 15 Oct 2024 15:51:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jm9-0000BZ-Fw; Tue, 15 Oct 2024 11:47:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jm6-0008Ev-NL for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:54 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jm5-00014A-3i for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:47:54 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-20c8b557f91so45151285ad.2 for ; Tue, 15 Oct 2024 08:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007271; x=1729612071; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ng190dTBKHEnCOYKEZzpr313ucrQGKJ5Mjtr4qqtcdc=; b=PvDaiX4F68TKaKVDexUJyj46TUQY3uFbc5TIBhXf2nCfPB4MtGwhVSDuUKzGuvv4I/ AFo5LP2euVdRmVrFxZ/OTBzhjxeUHLmc2DxIuHiOE2rIo0x5eFXejjxzHMpgkdaUuvB+ y2mIMf0lXN9C9AOOTCt/Cb2P9/klGTyN9n1ySI50+PxQzQY59lsTTyqT5eqB4epgvwuj gkGzrWxZo9u5Sz9dKIdUH7O+6g9D+gaY0gQZRU6V6df6t0zROsnYdlMnexVK83xBEPTO aL4dEJeCC4m33/eYEDm73buuDsQRAw1EsfL+ieR9wgICkUzDEE5A1TfC91eG+lxc1GXg J61A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007271; x=1729612071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ng190dTBKHEnCOYKEZzpr313ucrQGKJ5Mjtr4qqtcdc=; b=XJMJv78//lfldZf/oPsqtfTK3qibYgI+/Ir1T1623TtLmWyjaQWi7o7v+oBhNpLoZ7 5IgfXfO+oe0atCHNQMTHHyOWqtT6wJMpKN+Bpm/lJbXFIBYME8h9BOIwtzBGra4fnU09 fytW8Y3dI3lxJqhJVx9dEeSWsTLwVF0r1eF1pV95+QRlBEM0EXE+DEeEDOkUyyqcBb1J JirqzmaXRiRTOf82UCORHL1YMUlgWBTuz8mpjwvxc4KrDaIwzC+1d3bFCY+F7DSsaec6 lUlMuiLTMD+fR+gq9JuVJagjHqUUyyWZxF1CeOrMBYWTlFfz2dHWVM3jaowBnbuA8cMT 5yEA== X-Gm-Message-State: AOJu0YwgIJN2nJhc2Pk0Y/pw9rR56Kw48Oz7HyMvIZXnkm2PI1l3iauH C/4bdqauJ9amcbcR9Db8FtjwvZPo+8EXlgSWQ+DczZUsPcpyqc3DcI55gnJrlYEztQfPb44xZQG f X-Google-Smtp-Source: AGHT+IEJGJ45nvBF/19W/qtWHpqFVBg2wZnf2lGU0yg79DGADKXdSMa9jLKg1kHakg1jTZs+FgId4A== X-Received: by 2002:a17:90b:17c2:b0:2e2:dd25:9b00 with SMTP id 98e67ed59e1d1-2e3ab821dc7mr713390a91.22.1729007271431; Tue, 15 Oct 2024 08:47:51 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2f037c72csm5716230a91.1.2024.10.15.08.47.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 26/33] target/mips: Introduce mo_endian() helper Date: Tue, 15 Oct 2024 12:44:35 -0300 Message-ID: <20241015154443.71763-27-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce mo_endian() which returns the endian MemOp corresponding to the vCPU DisasContext. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-10-philmd@linaro.org> --- target/mips/tcg/translate.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index c55f90e741b..49ff6b8cd80 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -240,6 +240,11 @@ static inline bool disas_is_bigendian(DisasContext *ctx) return extract32(ctx->CP0_Config0, CP0C0_BE, 1); } +static inline MemOp mo_endian(DisasContext *dc) +{ + return disas_is_bigendian(dc) ? MO_BE : MO_LE; +} + static inline MemOp mo_endian_rev(DisasContext *dc, bool reversed) { return disas_is_bigendian(dc) ^ reversed ? MO_BE : MO_LE; From patchwork Tue Oct 15 15:44:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86B94D1D87B for ; Tue, 15 Oct 2024 15:50:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jmZ-0001eJ-4o; Tue, 15 Oct 2024 11:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jmI-0001N5-0Z for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:11 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jmE-00014a-Bq for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:05 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-20cb47387ceso31127195ad.1 for ; Tue, 15 Oct 2024 08:48:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007281; x=1729612081; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rF1ojij3TR1AnKGJCPi5nkzBARfzhp/al33DST0Rg3Y=; b=LApVN5UgdZt/JwSYovHFzzaUQ2E8r77qRd03CaQMetILwDSZOKmNWjG9evaarQkmkh +DT4BiUs88HyT288gqxPzNnzqGTYIYTBuHik5rBXeUQaO9p0pOnS+Fjg3G9alLuCkehq RLnbZ0Twdb4TTO3uwngVf/TYc+sBUo7fKzW1P8jdyIDcKToxVh7SvM1x6ix/9V4Kk487 FHMZx1ofkzm/1bF2HbXfwCvt/YsovBM4mj5yXPsUJV+n5KhcYiFcVpE4+tlPj8oHHE/+ EfvVTR8QxRJDu3dsgTEfus2MnFI/f7Nh4uiHW0hq7BtGhrUaxuknPVo56vTBzcNJJdBA OmNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007281; x=1729612081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rF1ojij3TR1AnKGJCPi5nkzBARfzhp/al33DST0Rg3Y=; b=XiJKRBvonTm+r+q+sW4pS9P8R4oCvfMZiAG7XXHuXQcY3VCgCNRjoiMMlCgK5PCmo0 7Z/ju+hFARS2qcxCxgoy4IjGRxp1m2jUp8N9uqBzemXcBl1xO7piIm/8g+uRLtV/5p5m kOIQC5zgj9o3xWGU8+ql5EoOg3asCTbSI713m77D9G0mNF4+IavCFuUyf8v8rlK3gLBv FEr3p7C1vp6G+ewVX4DqRbvhRvbXQordufSgLL/gU+20FHuvtfyYUTlc4t6Gd3Zj1emM bksB/RukplpXF3wva6Ox9mf0m86L40kgNSJcm52TjKcRzUisCRwP7KF3Mxf2nZrjudl2 j0KQ== X-Gm-Message-State: AOJu0Yyp25sRz1YSG5CiHticMcev9O6nBeytJmd/FZjhEPsSTzAh5md8 g9nFo+t95QJca9s2ynz5ICIltn9THUH9TcfSMzO/UPKpkISBAwt+Dql33C5s/XPCxAyvEvkhaPu D X-Google-Smtp-Source: AGHT+IH+MexrVQm53bi9vE+yz0yk9ZhkfNgoP0rj+56anG7hG6CB06HErI3x+E4eADvtPV+KpqMprA== X-Received: by 2002:a17:902:d491:b0:20c:c694:f6c6 with SMTP id d9443c01a7336-20d27f2763dmr8964315ad.49.1729007280181; Tue, 15 Oct 2024 08:48:00 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1807100asm13473155ad.304.2024.10.15.08.47.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:47:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 27/33] target/mips: Replace MO_TE by mo_endian() Date: Tue, 15 Oct 2024 12:44:36 -0300 Message-ID: <20241015154443.71763-28-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace compile-time MO_TE evaluation by runtime mo_endian() one, which expand target endianness from DisasContext. Mechanical change using: $ sed -i -e 's/MO_TE/mo_endian(ctx)/' \ $(git grep -l MO_TE target/mips) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-11-philmd@linaro.org> --- target/mips/tcg/mxu_translate.c | 10 +- target/mips/tcg/translate.c | 120 +++++++++++----------- target/mips/tcg/tx79_translate.c | 8 +- target/mips/tcg/micromips_translate.c.inc | 22 ++-- target/mips/tcg/mips16e_translate.c.inc | 12 +-- target/mips/tcg/nanomips_translate.c.inc | 37 ++++--- 6 files changed, 106 insertions(+), 103 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index dd512ce7a48..35ebb0397da 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -4803,19 +4803,19 @@ static void decode_opc_mxu__pool17(DisasContext *ctx) switch (opcode) { case OPC_MXU_LXW: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_UL); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UL); break; case OPC_MXU_LXB: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_SB); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SB); break; case OPC_MXU_LXH: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_SW); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SW); break; case OPC_MXU_LXBU: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_UB); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UB); break; case OPC_MXU_LXHU: - gen_mxu_lxx(ctx, strd2, MO_TE | MO_UW); + gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UW); break; default: MIPS_INVAL("decode_opc_mxu"); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6ba8371658c..c0b97539a29 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \ } #endif -OP_LD_ATOMIC(ll, MO_TE | MO_SL); +OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL); #if defined(TARGET_MIPS64) -OP_LD_ATOMIC(lld, MO_TE | MO_UQ); +OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ); #endif #undef OP_LD_ATOMIC @@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, switch (opc) { #if defined(TARGET_MIPS64) case OPC_LWU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; case OPC_LD: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LDL: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); + gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDR: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ); + gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t1, rt); break; case OPC_LDPC: t1 = tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t0, rt); break; #endif case OPC_LWPC: t1 = tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL); gen_store_gpr(t0, rt); break; case OPC_LWE: mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_LW: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_LH: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_LHU: - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW | + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWL: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL); + gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWR: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL); + gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_ext32s_tl(t1, t1); gen_store_gpr(t1, rt); break; @@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt, switch (opc) { #if defined(TARGET_MIPS64) case OPC_SD: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_SDL: @@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt, mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_SW: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; case OPC_SHE: mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_SH: - tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW | + tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_SBE: @@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, case OPC_LWC1: { TCGv_i32 fp0 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, ft); } @@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, ft); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); } break; case OPC_LDC1: { TCGv_i64 fp0 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, fp0, ft); } @@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, ft); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); } break; @@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, case R6_OPC_LWPC: offset = sextract32(ctx->opcode << 2, 0, 21); addr = addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL); + gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL); break; #if defined(TARGET_MIPS64) case OPC_LWUPC: check_mips_64(ctx); offset = sextract32(ctx->opcode << 2, 0, 21); addr = addr_add(ctx, pc, offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL); + gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL); break; #endif default: @@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, check_mips_64(ctx); offset = sextract32(ctx->opcode << 3, 0, 21); addr = addr_add(ctx, (pc & ~0x7), offset); - gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ); + gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ); break; #endif default: @@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, case OPC_GSLQ: t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rt); gen_store_gpr(t0, lsq_rt1); @@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, check_cp1_enabled(ctx); t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t0, lsq_rt1); @@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_gpr(t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; case OPC_GSSQC1: @@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, rs, lsq_offset); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); gen_load_fpr64(ctx, t1, lsq_rt1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_fpr32(ctx, fp0, rt); t1 = tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); + gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_fpr32(ctx, fp0, rt); t1 = tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL); + gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); break; @@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 = tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); + gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; case OPC_GSLDRC1: @@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 = tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ); + gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_fpr64(ctx, t1, rt); break; #endif @@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, gen_store_gpr(t0, rt); break; case OPC_GSLHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); break; @@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } fp0 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, rt); break; @@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); } - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t0, rt); break; @@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, case OPC_GSSHX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); break; case OPC_GSSWX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif case OPC_GSSWXC1: fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, rt); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; #if defined(TARGET_MIPS64) case OPC_GSSDXC1: t1 = tcg_temp_new(); gen_load_fpr64(ctx, t1, rt); - tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i32 fp0 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fd); } @@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, check_cp1_registers(ctx, fd); { TCGv_i64 fp0 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i64 fp0 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); - tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL); + tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); } break; case OPC_SDXC1: @@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); } break; case OPC_SUXC1: @@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); } break; } @@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd) gen_op_addr_add(ctx, t0, t1, t0); } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); gen_store_gpr(t1, rd); } @@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rd); break; case OPC_LHX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW); gen_store_gpr(t0, rd); break; case OPC_LWX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); gen_store_gpr(t0, rd); break; #if defined(TARGET_MIPS64) case OPC_LDX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t0, rd); break; #endif @@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) } break; case R6_OPC_SC: - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false); break; case R6_OPC_LL: gen_ld(ctx, op1, rt, rs, imm); @@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) #endif #if defined(TARGET_MIPS64) case R6_OPC_SCD: - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false); break; case R6_OPC_LLD: gen_ld(ctx, op1, rt, rs, imm); @@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) return; case OPC_SCE: check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, true); return; case OPC_CACHEE: check_eva(ctx); @@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false); break; case OPC_CACHE: check_cp0_enabled(ctx); @@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) check_insn_opc_user_only(ctx, INSN_R5900); } check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false); + gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ if (ctx->insn_flags & ISA_MIPS_R6) { diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index 1d290b86a98..ae3f5e19c43 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) tcg_gen_andi_tl(addr, addr, ~0xf); /* Lower half */ - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr(t0, a->rt); /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); - tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); gen_store_gpr_hi(t0, a->rt); return true; } @@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a) /* Lower half */ gen_load_gpr(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); /* Upper half */ tcg_gen_addi_i64(addr, addr, 8); gen_load_gpr_hi(t0, a->rt); - tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); return true; } diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 343d64a0e85..171508f7deb 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SWP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; #ifdef TARGET_MIPS64 @@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SDP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); break; #endif @@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, offset); break; case SC: - gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, false); break; #if defined(TARGET_MIPS64) case SCD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false); + gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_UQ, false); break; #endif case LD_EVA: @@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) mips32_op = OPC_SHE; goto do_st_lr; case SCE: - gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true); + gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, true); break; case SWE: mips32_op = OPC_SWE; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index f80d35225e8..ef7a0ec0d38 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0) tcg_gen_movi_tl(t2, -4); gen_op_addr_add(ctx, t0, t0, t2); gen_load_gpr(t1, regidx); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); } @@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx, case 4: gen_base_offset_addr(ctx, t0, 29, 12); gen_load_gpr(t1, 7); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 3: gen_base_offset_addr(ctx, t0, 29, 8); gen_load_gpr(t1, 6); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 2: gen_base_offset_addr(ctx, t0, 29, 4); gen_load_gpr(t1, 5); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); /* Fall through */ case 1: gen_base_offset_addr(ctx, t0, 29, 0); gen_load_gpr(t1, 4); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL | + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); } @@ -297,7 +297,7 @@ static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0) tcg_gen_movi_tl(t2, -4); gen_op_addr_add(ctx, t0, t0, t2); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, regidx); } diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 06204585f23..d462173348f 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, TCGv tmp2 = tcg_temp_new(); gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIGN); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, + mo_endian(ctx) | MO_UQ | MO_ALIGN); if (disas_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { @@ -1075,7 +1076,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count, gen_base_offset_addr(ctx, va, 29, this_offset); gen_load_gpr(t0, this_rt); tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx, - MO_TE | MO_UL | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); counter++; } @@ -1095,8 +1096,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f); int this_offset = u - ((counter + 1) << 2); gen_base_offset_addr(ctx, va, 29, this_offset); - tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL | - ctx->default_tcg_memop_mask); + tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, + mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, this_rt); counter++; @@ -2647,13 +2648,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) case NM_LHX: /*case NM_LHXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TE | MO_SW | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LWX: /*case NM_LWXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TE | MO_SL | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LBUX: @@ -2663,7 +2664,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) case NM_LHUX: /*case NM_LHUXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TE | MO_UW | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_SBX: @@ -2676,14 +2677,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TE | MO_UW | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask); break; case NM_SWX: /*case NM_SWXS:*/ check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TE | MO_UL | ctx->default_tcg_memop_mask); + mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); break; case NM_LWC1X: /*case NM_LWC1XS:*/ @@ -3737,7 +3738,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) tcg_gen_movi_tl(t0, addr); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, - MO_TE | MO_SL + mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); } break; @@ -3755,7 +3756,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TE | MO_UL + mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); } break; @@ -4135,13 +4136,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) switch (extract32(ctx->opcode, 11, 4)) { case NM_UALH: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TE | MO_SW | MO_UNALN); + mo_endian(ctx) | MO_SW | MO_UNALN); gen_store_gpr(t0, rt); break; case NM_UASH: gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TE | MO_UW | MO_UNALN); + mo_endian(ctx) | MO_UW | MO_UNALN); break; } } @@ -4163,7 +4164,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_P_SC: switch (ctx->opcode & 0x03) { case NM_SC: - gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false); + gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL, + false); break; case NM_SCWP: check_xnp(ctx); @@ -4276,7 +4278,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_xnp(ctx); check_eva(ctx); check_cp0_enabled(ctx); - gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true); + gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL, + true); break; case NM_SCWPE: check_xnp(ctx); @@ -4319,7 +4322,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) switch (extract32(ctx->opcode, 11, 1)) { case NM_LWM: tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx, - memop | MO_TE | MO_SL); + memop | mo_endian(ctx) | MO_SL); gen_store_gpr(t1, this_rt); if ((this_rt == rs) && (counter != (count - 1))) { @@ -4330,7 +4333,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) this_rt = (rt == 0) ? 0 : this_rt; gen_load_gpr(t1, this_rt); tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx, - memop | MO_TE | MO_UL); + memop | mo_endian(ctx) | MO_UL); break; } counter++; From patchwork Tue Oct 15 15:44:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9868CFC27C for ; Tue, 15 Oct 2024 15:50:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jmc-0001qC-5d; Tue, 15 Oct 2024 11:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jmN-0001R1-J8 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:12 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jmM-00014w-1q for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:11 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-71e4e481692so3061738b3a.1 for ; Tue, 15 Oct 2024 08:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007287; x=1729612087; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NP/jQdl3vCj51cE4P9kHFWkOQjoBpIwLQmMBNAGca+s=; b=P0xnVIykjJvmMwrw8e4CESzUI0BZYmTpBTxnF8SVOE05KQ4fHNUy+iilIyDz1M7z/S zTLdtnIyw0nu9DW64YKqviCTTTG0WdK/t51DPLq46EKxbcnmqzWJloeLrymJRBkXuYj+ IAa/8MxLiFN8c6cYoLFsVlvW8ZsjmvFV0Qjug/5q/GmgkBaeawZg7kJ6lE3sqlASBe8o SHIuGYh2sRWm7ZO03lKRnF1YWEwIsb27Gvf07lb3u5na5j/nNRLGHqHxYR+Kw/PhUTrD r0oL7HkH9LXElHPSluxOnZq9hXPFTclJHLC+6XV7pLmMymT0Ee7jDBlTDfw4ROIPifGL +C1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007287; x=1729612087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NP/jQdl3vCj51cE4P9kHFWkOQjoBpIwLQmMBNAGca+s=; b=lx+wiccTguFuUEO/glLSTbroiqcKRWWXceTIP4qd2qqwI10NaFp6gCcX7h2dJQMu5w FJQW8P5oatIrNGn/ESBhRQIEvvKeVgyE8NsVtRLVQv8Bjf7L34CA7C+fVnef3AwG9fo5 QjyTZnLUXIGnjVDm+MoZHmneHp5XBF/9DCe4zuLudObx3wKCHKCOGDdBG3VNeaeOIBS+ 7poDlZrz1YTBr5k68e+YshXM2zC3kxPyDTCN6bntFJP1Stin+Z6Xq+XI+8Gb4FG7uETw 1JHJTixpXUeIFzj6cggPnsqOXn+zR2yA+S0MjTb43bbQHWsRY9PE/BAsqnnIPX8Cwgak iXyg== X-Gm-Message-State: AOJu0YwKaurMYS77hIwcmHtm5/6wrBCyb6DW2XNaEmU4ojtAnYb7lFJO kG52erRD+yql5LFao6pglO3HfWUYkSHS+FtiO2wQItIoh4UqiFNlszqWTyoXBdFgfh3XmcSXwEZ 7 X-Google-Smtp-Source: AGHT+IEBflXUUGZlRXWI2uD3pydZPOG/qpmoJV/2xBKZ0+M4zImhndUoRc7zDY+Ad9LD9uqsvwBAyw== X-Received: by 2002:a05:6a00:10c3:b0:71d:f012:6de7 with SMTP id d2e1a72fcca58-71e4c1cfd6fmr19522313b3a.27.1729007287043; Tue, 15 Oct 2024 08:48:07 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e773a3c39sm1418099b3a.73.2024.10.15.08.48.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:48:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 28/33] target/mips: Have gen_addiupc() expand $pc during translation Date: Tue, 15 Oct 2024 12:44:37 -0300 Message-ID: <20241015154443.71763-29-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-12-philmd@linaro.org> --- target/mips/tcg/translate.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index c0b97539a29..0ccf32d185e 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -11428,20 +11428,18 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, void gen_addiupc(DisasContext *ctx, int rx, int imm, int is_64_bit, int extended) { - TCGv t0; + target_ulong npc; if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { gen_reserved_instruction(ctx); return; } - t0 = tcg_temp_new(); - - tcg_gen_movi_tl(t0, pc_relative_pc(ctx)); - tcg_gen_addi_tl(cpu_gpr[rx], t0, imm); + npc = pc_relative_pc(ctx) + imm; if (!is_64_bit) { - tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); + npc = (int32_t)npc; } + tcg_gen_movi_tl(cpu_gpr[rx], npc); } static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, From patchwork Tue Oct 15 15:44:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6958D1D87B for ; Tue, 15 Oct 2024 15:51:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jmc-0001rB-5l; Tue, 15 Oct 2024 11:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jmT-0001Yi-Ld for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:21 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jmR-00015U-No for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:17 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-20cb89a4e4cso24774645ad.3 for ; Tue, 15 Oct 2024 08:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007294; x=1729612094; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ggpFvPFEzmcakXrNsZshdbMpubg1VkOtzGZJPItwWGk=; b=Zw3IHMEh5IEHsAyVHG4xdxtOVmz+adXhxshAtUPitpnAjBIWfwNsZVyJrH64TFFq9u r99Lqfm997WwGcLPwc4Uz7kJbqX3IJhrct248U7sL0Qg+gMj4VSXdqZiGpff//BcGEqH 2tfG0bg24P21PXHKVw2PNLa19xwFr8EPPwbVg8PMbEc8nJeeMt3qVQKIJmzG8a3xbAza 9hCU/zl1BTmfHbUsN1FId11GfKKKdErTbS0Ipconhj3Zuif5e0sHKyreY61xMJo52Nww ikT0gM9pERj0cQlUJHmMmN5TioBBYvwYgA+syVi9JH1NUiuXMluonjMVPWgCK9Fz5DmO Qr+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007294; x=1729612094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ggpFvPFEzmcakXrNsZshdbMpubg1VkOtzGZJPItwWGk=; b=OBmWo/dSYWPQ2hAii79HV0YXXeMbxCBRK7aGfXEp2g6dvh6e7Doi0HeCQCffDEqGFP KM1Aa/iRrlyaOun7WwVCmy68CM38aGxFMd8tiJEQyWcw54aradjuio+SR0ISM2XRkxH9 R5j2t8c3CjaIyWLu9iGb3bpFz7fue6PxK7rVij6Vud6hUCL+eR7tt162rg8jK6v+HL3R j/BlsP67nUhP45pwK//4YugYxB12RLJe5FWAQwujllX5S4PYDysMLXrE12JNPswQ6Wx9 ywxGnYmYrLU2LKZ7zepxYxc5hMUw0Coid9rbbG3OEQx+cqsphx7Hsk/72IK83hs5gAVs sm0w== X-Gm-Message-State: AOJu0YyjBPoXhkrRFkAzMs6lgLwHblKV5gzUfbzZaRSKkCL6Ygre/PtV a608yvGySxXfw0n9MXowNbLuof0rB9Y215gxCd0etEXdQuUauAtQxVoJ2NFTQqJkY9vdowUfAXu g X-Google-Smtp-Source: AGHT+IEIVGLWbUplPYqX3sgC+vSP8FZ9SCuL2Qdg10EsnJd9uISXkDuL+SMjPgxhIThKMLkO5ZNh7g== X-Received: by 2002:a17:902:d50d:b0:20b:a6f5:2780 with SMTP id d9443c01a7336-20d27e8c3b5mr8980945ad.17.1729007293988; Tue, 15 Oct 2024 08:48:13 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d18036748sm13611745ad.166.2024.10.15.08.48.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:48:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 29/33] target/mips: Use gen_op_addr_addi() when possible Date: Tue, 15 Oct 2024 12:44:38 -0300 Message-ID: <20241015154443.71763-30-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single gen_op_addr_addi() call. gen_op_addr_addi() calls tcg_gen_addi_tl() which might optimize if the immediate is zero. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-13-philmd@linaro.org> --- target/mips/tcg/translate.h | 1 + target/mips/tcg/translate.c | 6 ++---- target/mips/tcg/micromips_translate.c.inc | 12 ++++-------- target/mips/tcg/mips16e_translate.c.inc | 15 ++++----------- target/mips/tcg/nanomips_translate.c.inc | 4 +--- 5 files changed, 12 insertions(+), 26 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 49ff6b8cd80..5d196e69ac4 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -176,6 +176,7 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm, * Address Computation and Large Constant Instructions */ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1); +void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs); bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 0ccf32d185e..53a0cbf92be 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1456,8 +1456,7 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) #endif } -static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, - target_long ofs) +void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs) { tcg_gen_addi_tl(ret, base, ofs); @@ -11265,10 +11264,9 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, } else { /* OPC_JIC, OPC_JIALC */ TCGv tbase = tcg_temp_new(); - TCGv toffset = tcg_constant_tl(offset); gen_load_gpr(tbase, rt); - gen_op_addr_add(ctx, btarget, tbase, toffset); + gen_op_addr_addi(ctx, btarget, tbase, offset); } break; default: diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 171508f7deb..3cbf53bf2b3 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -980,8 +980,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); - tcg_gen_movi_tl(t1, 4); - gen_op_addr_add(ctx, t0, t0, t1); + gen_op_addr_addi(ctx, t0, t0, 4); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); @@ -990,8 +989,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); - tcg_gen_movi_tl(t1, 4); - gen_op_addr_add(ctx, t0, t0, t1); + gen_op_addr_addi(ctx, t0, t0, 4); gen_load_gpr(t1, rd + 1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); @@ -1005,8 +1003,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); - tcg_gen_movi_tl(t1, 8); - gen_op_addr_add(ctx, t0, t0, t1); + gen_op_addr_addi(ctx, t0, t0, 8); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); @@ -1015,8 +1012,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); - tcg_gen_movi_tl(t1, 8); - gen_op_addr_add(ctx, t0, t0, t1); + gen_op_addr_addi(ctx, t0, t0, 8); gen_load_gpr(t1, rd + 1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | ctx->default_tcg_memop_mask); diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index ef7a0ec0d38..a9af8f1e74a 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -130,10 +130,8 @@ static int xlat(int r) static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0) { TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - tcg_gen_movi_tl(t2, -4); - gen_op_addr_add(ctx, t0, t0, t2); + gen_op_addr_addi(ctx, t0, t0, -4); gen_load_gpr(t1, regidx); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); @@ -146,7 +144,6 @@ static void gen_mips16_save(DisasContext *ctx, { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); int args, astatic; switch (aregs) { @@ -286,8 +283,7 @@ static void gen_mips16_save(DisasContext *ctx, } } - tcg_gen_movi_tl(t2, -framesize); - gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); + gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize); } static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0) @@ -309,10 +305,8 @@ static void gen_mips16_restore(DisasContext *ctx, { int astatic; TCGv t0 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - tcg_gen_movi_tl(t2, framesize); - gen_op_addr_add(ctx, t0, cpu_gpr[29], t2); + gen_op_addr_addi(ctx, t0, cpu_gpr[29], -framesize); if (do_ra) { decr_and_load(ctx, 31, t0); @@ -392,8 +386,7 @@ static void gen_mips16_restore(DisasContext *ctx, } } - tcg_gen_movi_tl(t2, framesize); - gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); + gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize); } #if defined(TARGET_MIPS64) diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index d462173348f..8e05a36b545 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -2470,11 +2470,9 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, } else { /* OPC_JIC, OPC_JIALC */ TCGv tbase = tcg_temp_new(); - TCGv toffset = tcg_temp_new(); gen_load_gpr(tbase, rt); - tcg_gen_movi_tl(toffset, offset); - gen_op_addr_add(ctx, btarget, tbase, toffset); + gen_op_addr_addi(ctx, btarget, tbase, offset); } break; default: From patchwork Tue Oct 15 15:44:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17224CFC27C for ; Tue, 15 Oct 2024 15:51:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jn2-0002Jc-6C; Tue, 15 Oct 2024 11:48:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jmb-0001ol-H4 for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:25 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jmY-000167-Sy for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:25 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-71e52582d0bso2350674b3a.3 for ; Tue, 15 Oct 2024 08:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007301; x=1729612101; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qYwNktTZHv8KqjRIkaVDg1GGkNJdQJLxA26N0R0p2/A=; b=JGQJUPasqB4KFBuwc2WkUUgQSEA63aQTC6DHZ+TuZfuZ8H0lNv4+lfVj3OCtH7njaX Mc7UlYUmRL3TcNj7Rh4sDlQPRqWp9Hkv/b+fKbMq9cG2n3dPe5vHe03hL30LRh4wQx/p tz+oEXXacimMvKHGM2F0st72XSDpvphxfr4dM6g+4ConbjM4l2eBIg5lGojCAYhYeVEg HSA65B8CpRnxqBB/+3njZxeeYK0QoiQ6+yecB8KDzV5hNwIXPWz6SW5eqC0yeL1Zf+oS L3Cn0P3cmYlZOoWLshVWqZ7Ke5ao5zIa0n5kT71j8IpX6LrjwQtu8OdomddcHG7tDRFL ExlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007301; x=1729612101; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qYwNktTZHv8KqjRIkaVDg1GGkNJdQJLxA26N0R0p2/A=; b=hnPOEy3y7LlgOtxubgzyeBuRb7AXZd8AV0TO+VjPSYXV+wyz33JPL+4wDn/+ElhcnI NAxkA3eSqgoB919/B11JmPy3+pWzknFEOFbLxlojf6oga1O8obiJ4sepcEHL3NgFh4Eq HUn264f3ZlR+TsMbkNXqvnBCiJnsGjsBzwp83+p5xcd8a84T6M/TAykg7rSl2TKrodRP og9Ow0FknM8QPOe1fr4i+ipKbCxbq84zPLFD/qI9BajtR03Y80xwVnKmlGlP4wvqLwgk hJKebiHCk5ELzpObkKG7dLaPNSowGxg/B+H+yqyhsOxY8cIFYfH1BdtfXSsrrckufuzk wMGQ== X-Gm-Message-State: AOJu0Yx0ng0yygoyHUClQ0nZopZ/mJ6Eaff1aYjBbxIGjYrnDmeb2+T0 7iOZwPxo5WwaKgbhZv8kmPJrBXw2DFJztE7eTdX8qo1fY9ZaipT1Qzc7dC9EOTr4dVL7qqpCBjl 2 X-Google-Smtp-Source: AGHT+IEDuif9gfwzdonR0c+XULx137TEUFxil7KRx4EKhzkrcOLYdEf4HvHh8IMiC1bQxLoljbUR6Q== X-Received: by 2002:a05:6a20:9f47:b0:1d4:fc75:8d48 with SMTP id adf61e73a8af0-1d8c9576f8emr18859424637.3.1729007300934; Tue, 15 Oct 2024 08:48:20 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e77371740sm1418859b3a.40.2024.10.15.08.48.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:48:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 30/33] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Date: Tue, 15 Oct 2024 12:44:39 -0300 Message-ID: <20241015154443.71763-31-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Directly use tcg_constant_tl() for constant integer, this save a call to tcg_gen_movi_tl(), often saving a temp register. Most of the places found using the following Coccinelle spatch script: @@ identifier tmp; constant val; @@ * TCGv tmp = tcg_temp_new(); ... * tcg_gen_movi_tl(tmp, val); @@ identifier tmp; int val; @@ * TCGv tmp = tcg_temp_new(); ... * tcg_gen_movi_i64(tmp, val); Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241004202621.4321-2-philmd@linaro.org> --- target/mips/tcg/translate.c | 49 ++++------ target/mips/tcg/nanomips_translate.c.inc | 111 +++++++++-------------- 2 files changed, 59 insertions(+), 101 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 53a0cbf92be..d92fc418edd 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -2252,8 +2252,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, /* compare the address against that of the preceding LL */ gen_base_offset_addr(ctx, addr, base, offset); tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); - tcg_gen_movi_tl(t0, 0); - gen_store_gpr(t0, rt); + gen_store_gpr(tcg_constant_tl(0), rt); tcg_gen_br(done); gen_set_label(l1); @@ -3059,8 +3058,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_and_tl(t2, t2, t3); tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); } @@ -3076,30 +3074,27 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_and_tl(t2, t2, t3); tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); } break; case R6_OPC_DIVU: { - TCGv t2 = tcg_constant_tl(0); - TCGv t3 = tcg_constant_tl(1); tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, + tcg_constant_tl(0), tcg_constant_tl(1), t1); tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); } break; case R6_OPC_MODU: { - TCGv t2 = tcg_constant_tl(0); - TCGv t3 = tcg_constant_tl(1); tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, + tcg_constant_tl(0), tcg_constant_tl(1), t1); tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); } @@ -3154,8 +3149,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_and_tl(t2, t2, t3); tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); } break; @@ -3168,24 +3162,21 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_and_tl(t2, t2, t3); tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); } break; case R6_OPC_DDIVU: { - TCGv t2 = tcg_constant_tl(0); - TCGv t3 = tcg_constant_tl(1); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, + tcg_constant_tl(0), tcg_constant_tl(1), t1); tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); } break; case R6_OPC_DMODU: { - TCGv t2 = tcg_constant_tl(0); - TCGv t3 = tcg_constant_tl(1); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, + tcg_constant_tl(0), tcg_constant_tl(1), t1); tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); } break; @@ -3238,8 +3229,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) tcg_gen_and_tl(t2, t2, t3); tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); tcg_gen_div_tl(cpu_LO[1], t0, t1); tcg_gen_rem_tl(cpu_HI[1], t0, t1); tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); @@ -3294,8 +3284,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_and_tl(t2, t2, t3); tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); tcg_gen_div_tl(cpu_LO[acc], t0, t1); tcg_gen_rem_tl(cpu_HI[acc], t0, t1); tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); @@ -3347,17 +3336,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_and_tl(t2, t2, t3); tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); tcg_gen_div_tl(cpu_LO[acc], t0, t1); tcg_gen_rem_tl(cpu_HI[acc], t0, t1); } break; case OPC_DDIVU: { - TCGv t2 = tcg_constant_tl(0); - TCGv t3 = tcg_constant_tl(1); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, + tcg_constant_tl(0), tcg_constant_tl(1), t1); tcg_gen_divu_i64(cpu_LO[acc], t0, t1); tcg_gen_remu_i64(cpu_HI[acc], t0, t1); } diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 8e05a36b545..1e274143bbd 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -1053,8 +1053,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, tcg_gen_movi_tl(cpu_gpr[reg1], 0); } gen_set_label(lab_done); - tcg_gen_movi_tl(lladdr, -1); - tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_st_tl(tcg_constant_tl(-1), tcg_env, offsetof(CPUMIPSState, lladdr)); } static void gen_adjust_sp(DisasContext *ctx, int u) @@ -1544,7 +1543,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, { int16_t imm; TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); TCGv v0_t = tcg_temp_new(); gen_load_gpr(v0_t, v1); @@ -1571,12 +1569,10 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, check_dsp(ctx); switch (extract32(ctx->opcode, 12, 2)) { case NM_MTHLIP: - tcg_gen_movi_tl(t0, v2 >> 3); - gen_helper_mthlip(t0, v0_t, tcg_env); + gen_helper_mthlip(tcg_constant_tl(v2 >> 3), v0_t, tcg_env); break; case NM_SHILOV: - tcg_gen_movi_tl(t0, v2 >> 3); - gen_helper_shilo(t0, v0_t, tcg_env); + gen_helper_shilo(tcg_constant_tl(v2 >> 3), v0_t, tcg_env); break; default: gen_reserved_instruction(ctx); @@ -1588,39 +1584,34 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, imm = extract32(ctx->opcode, 14, 7); switch (extract32(ctx->opcode, 12, 2)) { case NM_RDDSP: - tcg_gen_movi_tl(t0, imm); - gen_helper_rddsp(t0, t0, tcg_env); + gen_helper_rddsp(t0, tcg_constant_tl(imm), tcg_env); gen_store_gpr(t0, ret); break; case NM_WRDSP: gen_load_gpr(t0, ret); - tcg_gen_movi_tl(t1, imm); - gen_helper_wrdsp(t0, t1, tcg_env); + gen_helper_wrdsp(t0, tcg_constant_tl(imm), tcg_env); break; case NM_EXTP: - tcg_gen_movi_tl(t0, v2 >> 3); - tcg_gen_movi_tl(t1, v1); - gen_helper_extp(t0, t0, t1, tcg_env); + gen_helper_extp(t0, tcg_constant_tl(v2 >> 3), + tcg_constant_tl(v1), tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTPDP: - tcg_gen_movi_tl(t0, v2 >> 3); - tcg_gen_movi_tl(t1, v1); - gen_helper_extpdp(t0, t0, t1, tcg_env); + gen_helper_extpdp(t0, tcg_constant_tl(v2 >> 3), + tcg_constant_tl(v1), tcg_env); gen_store_gpr(t0, ret); break; } break; case NM_POOL32AXF_1_4: check_dsp(ctx); - tcg_gen_movi_tl(t0, v2 >> 2); switch (extract32(ctx->opcode, 12, 1)) { case NM_SHLL_QB: - gen_helper_shll_qb(t0, t0, v0_t, tcg_env); + gen_helper_shll_qb(t0, tcg_constant_tl(v2 >> 2), v0_t, tcg_env); gen_store_gpr(t0, ret); break; case NM_SHRL_QB: - gen_helper_shrl_qb(t0, t0, v0_t); + gen_helper_shrl_qb(t0, tcg_constant_tl(v2 >> 2), v0_t); gen_store_gpr(t0, ret); break; } @@ -1631,23 +1622,25 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, break; case NM_POOL32AXF_1_7: check_dsp(ctx); - tcg_gen_movi_tl(t0, v2 >> 3); - tcg_gen_movi_tl(t1, v1); switch (extract32(ctx->opcode, 12, 2)) { case NM_EXTR_W: - gen_helper_extr_w(t0, t0, t1, tcg_env); + gen_helper_extr_w(t0, tcg_constant_tl(v2 >> 3), + tcg_constant_tl(v1), tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTR_R_W: - gen_helper_extr_r_w(t0, t0, t1, tcg_env); + gen_helper_extr_r_w(t0, tcg_constant_tl(v2 >> 3), + tcg_constant_tl(v1), tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTR_RS_W: - gen_helper_extr_rs_w(t0, t0, t1, tcg_env); + gen_helper_extr_rs_w(t0, tcg_constant_tl(v2 >> 3), + tcg_constant_tl(v1), tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTR_S_H: - gen_helper_extr_s_h(t0, t0, t1, tcg_env); + gen_helper_extr_s_h(t0, tcg_constant_tl(v2 >> 3), + tcg_constant_tl(v1), tcg_env); gen_store_gpr(t0, ret); break; } @@ -1849,8 +1842,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, case NM_EXTRV_W: check_dsp(ctx); gen_load_gpr(v1_t, rs); - tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_w(t0, t0, v1_t, tcg_env); + gen_helper_extr_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env); gen_store_gpr(t0, ret); break; } @@ -1904,8 +1896,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, break; case NM_EXTRV_R_W: check_dsp(ctx); - tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_r_w(t0, t0, v1_t, tcg_env); + gen_helper_extr_r_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env); gen_store_gpr(t0, ret); break; default: @@ -1924,8 +1915,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, break; case NM_EXTPV: check_dsp(ctx); - tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extp(t0, t0, v1_t, tcg_env); + gen_helper_extp(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env); gen_store_gpr(t0, ret); break; case NM_MSUB: @@ -1948,8 +1938,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, break; case NM_EXTRV_RS_W: check_dsp(ctx); - tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env); + gen_helper_extr_rs_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env); gen_store_gpr(t0, ret); break; } @@ -1965,8 +1954,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, break; case NM_EXTPDPV: check_dsp(ctx); - tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extpdp(t0, t0, v1_t, tcg_env); + gen_helper_extpdp(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env); gen_store_gpr(t0, ret); break; case NM_MSUBU: @@ -1991,8 +1979,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, break; case NM_EXTRV_S_H: check_dsp(ctx); - tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_s_h(t0, t0, v1_t, tcg_env); + gen_helper_extr_s_h(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env); gen_store_gpr(t0, ret); break; } @@ -2150,24 +2137,22 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, switch (opc) { case NM_SHRA_R_QB: check_dsp_r2(ctx); - tcg_gen_movi_tl(t0, rd >> 2); switch (extract32(ctx->opcode, 12, 1)) { case 0: /* NM_SHRA_QB */ - gen_helper_shra_qb(t0, t0, rs_t); + gen_helper_shra_qb(t0, tcg_constant_tl(rd >> 2), rs_t); gen_store_gpr(t0, rt); break; case 1: /* NM_SHRA_R_QB */ - gen_helper_shra_r_qb(t0, t0, rs_t); + gen_helper_shra_r_qb(t0, tcg_constant_tl(rd >> 2), rs_t); gen_store_gpr(t0, rt); break; } break; case NM_SHRL_PH: check_dsp_r2(ctx); - tcg_gen_movi_tl(t0, rd >> 1); - gen_helper_shrl_ph(t0, t0, rs_t); + gen_helper_shrl_ph(t0, tcg_constant_tl(rd >> 1), rs_t); gen_store_gpr(t0, rt); break; case NM_REPL_QB: @@ -2181,8 +2166,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, (uint32_t)imm << 8 | (uint32_t)imm; result = (int32_t)result; - tcg_gen_movi_tl(t0, result); - gen_store_gpr(t0, rt); + gen_store_gpr(tcg_constant_tl(result), rt); } break; default: @@ -2303,10 +2287,9 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, { TCGCond cond = TCG_COND_ALWAYS; TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); + TCGv timm = tcg_constant_tl(imm); gen_load_gpr(t0, rt); - tcg_gen_movi_tl(t1, imm); ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); /* Load needed operands and calculate btarget */ @@ -2335,7 +2318,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, } else { tcg_gen_shri_tl(t0, t0, imm); tcg_gen_andi_tl(t0, t0, 1); - tcg_gen_movi_tl(t1, 0); + timm = tcg_constant_tl(0); if (opc == NM_BBEQZC) { cond = TCG_COND_EQ; } else { @@ -2390,7 +2373,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, /* Conditional compact branch */ TCGLabel *fs = gen_new_label(); - tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs); + tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, timm, fs); gen_goto_tb(ctx, 1, ctx->btarget); gen_set_label(fs); @@ -2404,7 +2387,6 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs, int rt) { TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); /* load rs */ gen_load_gpr(t0, rs); @@ -2416,8 +2398,7 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs, /* calculate btarget */ tcg_gen_shli_tl(t0, t0, 1); - tcg_gen_movi_tl(t1, ctx->base.pc_next + 4); - gen_op_addr_add(ctx, btarget, t1, t0); + gen_op_addr_add(ctx, btarget, tcg_constant_tl(ctx->base.pc_next + 4), t0); /* branch completion */ clear_branch_hflags(ctx); @@ -3444,13 +3425,10 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, case NM_SHILO: check_dsp(ctx); { - TCGv tv0 = tcg_temp_new(); - TCGv tv1 = tcg_temp_new(); int16_t imm = extract32(ctx->opcode, 16, 7); - tcg_gen_movi_tl(tv0, rd >> 3); - tcg_gen_movi_tl(tv1, imm); - gen_helper_shilo(tv0, tv1, tcg_env); + gen_helper_shilo(tcg_constant_tl(rd >> 3), + tcg_constant_tl(imm), tcg_env); } break; case NM_MULEQ_S_W_PHL: @@ -3505,8 +3483,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, break; case NM_SHRA_R_W: check_dsp(ctx); - tcg_gen_movi_tl(t0, rd); - gen_helper_shra_r_w(v1_t, t0, v1_t); + gen_helper_shra_r_w(v1_t, tcg_constant_tl(rd), v1_t); gen_store_gpr(v1_t, rt); break; case NM_SHRA_R_PH: @@ -3546,8 +3523,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, break; case NM_SHLL_S_W: check_dsp(ctx); - tcg_gen_movi_tl(t0, rd); - gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env); + gen_helper_shll_s_w(v1_t, tcg_constant_tl(rd), v1_t, tcg_env); gen_store_gpr(v1_t, rt); break; case NM_REPL_PH: @@ -3728,14 +3704,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_LWPC48: check_nms(ctx); if (rt != 0) { - TCGv t0; - t0 = tcg_temp_new(); - target_long addr = addr_add(ctx, ctx->base.pc_next + 6, addr_off); - tcg_gen_movi_tl(t0, addr); - tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, + tcg_gen_qemu_ld_tl(cpu_gpr[rt], tcg_constant_tl(addr), + ctx->mem_idx, mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask); } @@ -3743,17 +3716,15 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_SWPC48: check_nms(ctx); { - TCGv t0, t1; - t0 = tcg_temp_new(); + TCGv t1; t1 = tcg_temp_new(); target_long addr = addr_add(ctx, ctx->base.pc_next + 6, addr_off); - tcg_gen_movi_tl(t0, addr); gen_load_gpr(t1, rt); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + tcg_gen_qemu_st_tl(t1, tcg_constant_tl(addr), ctx->mem_idx, mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask); } From patchwork Tue Oct 15 15:44:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B21C2D1D87B for ; Tue, 15 Oct 2024 15:50:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jn2-0002Pl-9Q; Tue, 15 Oct 2024 11:48:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jmj-0001yT-4L for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:39 -0400 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jmg-00016i-6a for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:32 -0400 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-27d0e994ae3so2523203fac.3 for ; Tue, 15 Oct 2024 08:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007309; x=1729612109; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IoVdSPoH5wb0VwFY5mr81ie4+HpYnQomv3PX5To8Uyg=; b=U9inwYBuh3BxlUCyvdgmTFyULtYr9KoJb6nGA5kkZd6wX2VCH1q1Kc0LRILfFfx4cE 5PwgzIMtNiEIz8AqdB1SooG47SE7X6p/hmQTZMPW5VB5/goiSKoMcIE0DVkgiG3Bdtur YzMc7nbuXWZ3hJSOKGnRudwRnHjAwvgOXtklTuJ/IcM3b5A19DaRhGpn4zfRuElGdWPG s0cYp2J8F611XUrc9YtJZRvD3vb9vDHf2yjpAj4Bd542jbMYPujCCXfhFy6QH7fOqMun SZRG1pX2Gv+2813eNTgWenJz2KRqTspLCdL4v9O127iHlMQb+JUwb09+xXSXVLJa8Dx5 XLbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007309; x=1729612109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IoVdSPoH5wb0VwFY5mr81ie4+HpYnQomv3PX5To8Uyg=; b=NLOXajjCuk2Rjr3SZwew8eauNryd4L4KZNQyfYZs6PdI+wn5uYh/5h6zyuxmYcMpPk pcJ7BeknESHLIYw2pfNLtRZAsUHtc85Q0iUq21Lm1S+7pWs1Ucq77LQQM6tzBe9qRzwj ABG4F4PtxwBp7dyfRZ4J3EIBR/2X8yX1NuwoUY0uIEAovy18Rhxzo/yERDNah9fPrYJA KcliqBxiGyygF3gLLQCkjMf2DnqQTlZgW4BKsdU0LOVRZ6iEniXJ2BK0Jar/myV6YjrK l1qmySHTxrLnsC8zSpwI0KW1m3PLJPEsPF+vFNFkeJ+0OB3S9E+Y5LohPr+2A3ga9tZ0 VWfw== X-Gm-Message-State: AOJu0Yxp3GOuD7czlC6ei7An+BgyhOaRFudPpRMha/v6ERkNAowVRuDY MYaOIP34sSy4DWiRs6PO/q735Wm7zL/gjscPtAnPkxzY7CcC26eGpLbeFtkcHgCfj2ZiIwWbV5l G X-Google-Smtp-Source: AGHT+IE4LOFDsCrL8lQdbaITPtn2XREfDeXUVm4SGd1chR/o8mfosJiu7/B5FwALyX7LpnqwdFhrkg== X-Received: by 2002:a05:6870:d610:b0:24e:8987:6f34 with SMTP id 586e51a60fabf-288872ad8f9mr7429876fac.3.1729007308760; Tue, 15 Oct 2024 08:48:28 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e773e9ecfsm1418389b3a.89.2024.10.15.08.48.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:48:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 31/33] target/mips: Expose MIPSCPU::is_big_endian property Date: Tue, 15 Oct 2024 12:44:40 -0300 Message-ID: <20241015154443.71763-32-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=philmd@linaro.org; helo=mail-oa1-x2e.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-15-philmd@linaro.org> --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 12 ++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3e906a175a3..070e11fe0da 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,6 +1209,9 @@ struct ArchCPU { Clock *clock; Clock *count_div; /* Divider for CP0_Count clock */ + + /* Properties */ + bool is_big_endian; }; /** diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 89655b1900f..04bf4b11db2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -200,10 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; - env->CP0_Config0 = env->cpu_model->CP0_Config0; -#if TARGET_BIG_ENDIAN - env->CP0_Config0 |= (1 << CP0C0_BE); -#endif + env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, + CP0C0_BE, 1, cpu->is_big_endian); env->CP0_Config1 = env->cpu_model->CP0_Config1; env->CP0_Config2 = env->cpu_model->CP0_Config2; env->CP0_Config3 = env->cpu_model->CP0_Config3; @@ -541,6 +539,11 @@ static const struct SysemuCPUOps mips_sysemu_ops = { }; #endif +static Property mips_cpu_properties[] = { + DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -571,6 +574,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) DeviceClass *dc = DEVICE_CLASS(c); ResettableClass *rc = RESETTABLE_CLASS(c); + device_class_set_props(dc, mips_cpu_properties); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, From patchwork Tue Oct 15 15:44:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F1FCCFC27C for ; Tue, 15 Oct 2024 15:50:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jn3-0002UP-6E; Tue, 15 Oct 2024 11:48:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jmp-0001zv-5W for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:43 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jmn-000175-KH for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:38 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-20cb7088cbcso29470405ad.0 for ; Tue, 15 Oct 2024 08:48:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007316; x=1729612116; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lIjNYbY65EWra3DHlZPbrN2P0VlApyu/tC25IgqxIlY=; b=T716zglYJyZZKPqDckvRA/4hReFJucuSKI6lpgFoqRkhLosYEOLxK7u8j5QbREE8NF Yx7CRWvqSgkXnyC+uF9fl187Gap95Fze/yulAnQIm+bl1HYkIoN19ixUEGH+AXZiQ74R c5uCUhw/UdeOZkA5ktoIgR04CXkOHbYarGpr+1c/uiSyyW1zCxMe1ooBN+WfyeZF+WCP DphKSHx37JkOIyWbZGOhfN3oHJFZt133el57FSjqjsrO8dcIRwWkFnZ9cO0UUX6NZsY+ k4yOdZ4hLe4egIdlLMPQz/VIZZokbOIQ+QBvufIk9Ves7ftLAgz/F2LbT6NFvtKmi8XP JhjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007316; x=1729612116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lIjNYbY65EWra3DHlZPbrN2P0VlApyu/tC25IgqxIlY=; b=YOuEnwKls5geyj3ZSDIYvISi8pVLFt9GKhRrbqsdTSKrbTPUVc/Xcmaot4Otvbmvh1 pKHdIRkouLg0mIO0i+ISZxEmYJEroZtgE+lu7WPhYjexowiEce9s0NyOJVgfA/oB1CUO O4wQJHxFS8R6Y/B8hXBmYi5Oy7/Iijchef9mh7jZaiomdg47ss9Iqb4MxyksLLlFXObD pxXpdwNT1d/eoSdSvgz2VTkn8Aq+27dP3XBpFl9FBRL3qPyja6s//B8VUeudXXr1DUtp JS/mCkIyt9BvSSKPNzG2ohUDPV0b1HFcicvDW4slKlm6HZDW06XPirBuSBgqQ21SjC1f jdyw== X-Gm-Message-State: AOJu0YwZU/6VXN0V3stF8urnIFUC6ernNexmOoLk/iUJYN5EHdYMVcnV BCl5qhlKTr/RcnJXx3ffF4IGaFuW9UGpNiqgd8Xu8dBjVsy9o7HwxHYlBULYwc6KsaolQqqC9mi H X-Google-Smtp-Source: AGHT+IEOXaqepz3jwH8YHN8ydqeT5jfCL+YZmcveelWaX5fZmmdtgXf4zInBaWzutEgMkF7e7Kt8NA== X-Received: by 2002:a17:902:ec83:b0:20c:5404:ed69 with SMTP id d9443c01a7336-20ca167bbbbmr197904375ad.31.1729007315861; Tue, 15 Oct 2024 08:48:35 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1805ce61sm13497715ad.265.2024.10.15.08.48.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:48:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 32/33] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Date: Tue, 15 Oct 2024 12:44:41 -0300 Message-ID: <20241015154443.71763-33-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Have the CPS expose a 'cpu-big-endian' property so it can set it to the vCPUs it creates. Note, since the number of vCPUs created is dynamic, we can not use QOM aliases. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-16-philmd@linaro.org> --- include/hw/mips/cps.h | 1 + hw/mips/cps.c | 4 ++++ hw/mips/malta.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 04d636246ab..05ef9f76b74 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -38,6 +38,7 @@ struct MIPSCPSState { uint32_t num_vp; uint32_t num_irq; char *cpu_type; + bool cpu_is_bigendian; MemoryRegion container; MIPSGCRState gcr; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 07b73b0a1f4..13046628cd2 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -77,6 +77,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); CPUMIPSState *env = &cpu->env; + object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bigendian, + &error_abort); + /* All VPs are halted on reset. Leave powering up to CPC. */ object_property_set_bool(OBJECT(cpu), "start-powered-off", true, &error_abort); @@ -167,6 +170,7 @@ static Property mips_cps_properties[] = { DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), + DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, false), DEFINE_PROP_END_OF_LIST() }; diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 1df00c4bf99..964d3592da7 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1054,6 +1054,8 @@ static void create_cps(MachineState *ms, MaltaState *s, object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, &error_fatal); + object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian", + TARGET_BIG_ENDIAN, &error_abort); object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); From patchwork Tue Oct 15 15:44:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13836658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCEB0CFC27C for ; Tue, 15 Oct 2024 15:50:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t0jn8-0002xf-HR; Tue, 15 Oct 2024 11:48:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t0jmw-00025r-FJ for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:48 -0400 Received: from mail-oo1-xc32.google.com ([2607:f8b0:4864:20::c32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t0jmu-00017g-Ol for qemu-devel@nongnu.org; Tue, 15 Oct 2024 11:48:46 -0400 Received: by mail-oo1-xc32.google.com with SMTP id 006d021491bc7-5eb54257e5eso194527eaf.0 for ; Tue, 15 Oct 2024 08:48:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729007323; x=1729612123; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hIJ9Az3wLYpKYtaTDQQbceKa5J8Ss6VqLkd1zjwnLbI=; b=Dl0sV07MnpbFdj8vm2OAemLOT6gnAMbJxjDjNp5StN81k/4Pk1qwtDkOtU5/n9xj3x 2LdaOIE4+zYM0at/2DuDeEdB7SH8Bwk1BV9x3xD1eYg/79ESmn3zodifaN5I39gGLQHZ OFIa/tvtnUgwk9Fd+fl0jj44LmZjcVyO2X1arHitg9h5RtyFugPRaEWFqFSPj+JqwhhM TqGXdQE1i6Efv6HuXbqpm5odjLMUTR8adGDBGeq5E287JLhDpP0vwKAfJqpXAX4kNAYy shNTZCd93AjheqckeCOH6mQivzfWYJV+hXjaRCeV01TG+qrTIG6frLVEg7NqyN+N+zzx kELA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729007323; x=1729612123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hIJ9Az3wLYpKYtaTDQQbceKa5J8Ss6VqLkd1zjwnLbI=; b=tEhi230ihWLYcIAANKIBcgJilnsB99NLInwtT3e3Q+vloY2El+lp5oQDPG+cWmnLLN EtPBrW6+xAz1Z9pXTqDP3KtbLdXLr2NPzvcAOSiH09HREcFm5x0ppU7A7a9Sd0JquBiv n5uRxgVheDLKA7MrlFpm/jyXCFe9zYOfXo4MCfEnMl+Mv+rdd4+ZbERD3lVMmpUFY7iI i98JrPlya68tXITO0D3HxkzXaWyqfhZBFtYIBBNgyOUkZSS8YoL6pkmvMd3SlIrQySa/ Q/G7vncqJDPjZ+Y+tHlgkg1YCLXrRy+cda0Ml1l8MRSdCPtoOuS7JxfXYEVzqMXBvvF6 Q8cg== X-Gm-Message-State: AOJu0Yz+gyxSYS68PLtvW+YVrgliUR/EbY7s2HKYum5Mwjj1UcqXLmwc EzzDj0veZdtTCVqdKJ2MxRzI5ervIBmRvWw5PtdsS12x1phW4d9nJJpQHIlTSS8HGk3m6R7FopZ c X-Google-Smtp-Source: AGHT+IEfpWbm8xp6NkMeVg1ikdNGVjj9PshjLQusHYWC6O0n3kU2fMRJu4kJgQK/LCSVr3XcWCKPqw== X-Received: by 2002:a05:6358:60ce:b0:1be:bb29:95a0 with SMTP id e5c5f4694b2df-1c32bad6770mr810017855d.13.1729007322866; Tue, 15 Oct 2024 08:48:42 -0700 (PDT) Received: from localhost.localdomain ([45.176.88.167]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ea9c7068afsm1516866a12.57.2024.10.15.08.48.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Oct 2024 08:48:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson Subject: [PULL 33/33] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Date: Tue, 15 Oct 2024 12:44:42 -0300 Message-ID: <20241015154443.71763-34-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241015154443.71763-1-philmd@linaro.org> References: <20241015154443.71763-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c32; envelope-from=philmd@linaro.org; helo=mail-oo1-xc32.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU endianness requested by argument. Update the board call sites. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241010215015.44326-17-philmd@linaro.org> --- target/mips/cpu.h | 4 +++- hw/mips/fuloong2e.c | 2 +- hw/mips/jazz.c | 3 ++- hw/mips/loongson3_virt.c | 2 +- hw/mips/malta.c | 3 ++- hw/mips/mipssim.c | 3 ++- target/mips/cpu.c | 5 ++++- 7 files changed, 15 insertions(+), 7 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 070e11fe0da..a4a46ebbe98 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1376,12 +1376,14 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. * @cpu_refclk: this cpu input clock (an output clock of another device) + * @is_big_endian: whether this CPU is configured in big endianness * * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk, * then realizes the CPU. * * Returns: A #CPUState or %NULL if an error occurred. */ -MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); +MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, + bool is_big_endian); #endif /* MIPS_CPU_H */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 6e4303ba473..7fd8296ccb6 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -229,7 +229,7 @@ static void mips_fuloong2e_init(MachineState *machine) clock_set_hz(cpuclk, 533080000); /* ~533 MHz */ /* init CPUs */ - cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 33ce51fb09c..0e43c9f0bac 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -212,7 +212,8 @@ static void mips_jazz_init(MachineState *machine, * ext_clk[jazz_model].pll_mult); /* init CPUs */ - cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, + TARGET_BIG_ENDIAN); env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index a2db98665df..f3b6326cc59 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -567,7 +567,7 @@ static void mips_loongson3_virt_init(MachineState *machine) int ip; /* init CPUs */ - cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 964d3592da7..198da5ba3d4 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1034,7 +1034,8 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, int i; for (i = 0; i < ms->smp.cpus; i++) { - cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); + cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, + TARGET_BIG_ENDIAN); /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index a07732d3dc5..5f4835a38de 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -160,7 +160,8 @@ mips_mipssim_init(MachineState *machine) #endif /* Init CPUs. */ - cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, + TARGET_BIG_ENDIAN); env = &cpu->env; reset_info = g_new0(ResetData, 1); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 04bf4b11db2..9724e71a5e0 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -643,12 +643,15 @@ static void mips_cpu_register_types(void) type_init(mips_cpu_register_types) /* Could be used by generic CPU object */ -MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) +MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, + bool is_big_endian) { DeviceState *cpu; cpu = DEVICE(object_new(cpu_type)); qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); + object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian, + &error_abort); qdev_realize(cpu, NULL, &error_abort); return MIPS_CPU(cpu);