From patchwork Wed Oct 16 12:30:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838438 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D81D41F8189; Wed, 16 Oct 2024 12:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083230; cv=none; b=GUeLWRRoTrioGkNCfvdnKD1KjIj91Pw9rdvEx4oCO8FM11aa3RytWsSWCXBVoyYUykqyuCjslSayfqUtScTYOBPSatxpK8vbTjQrrrxsuTNmaTpCAjPUjCDNwL5C/YtcMBF0w9kDp/iji2OEZvhqLphmkp4okgrR2YvG7OQSq9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083230; c=relaxed/simple; bh=KOY+JBxUC1JBmDbxMSISPXRy6rIM65p1ZBlq9X5krHw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=ppihlzskZnXsLffccY5fh8rrJoiWUnNIrpwJaiQpmWpZvblntP0I0+BuPmMbXJx/R0NonPo8K7rL//qzuQTzM9N6ZVG6Vsdb2izckia+3j8oRCm5yen4ZYziXu43b91SQgkEVO+MVxJqXL1yK6RJPs/cFIY2/oRy2GwcV7j5hJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cjNz3hVY; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cjNz3hVY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729083230; x=1760619230; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=KOY+JBxUC1JBmDbxMSISPXRy6rIM65p1ZBlq9X5krHw=; b=cjNz3hVY9Gb9+IYXnfIcA21n+77andZTpXPtQs+OYEm4sywx6FhsgIp2 tNct3yn2balAmNid6ukWl7VmFTwbfLGHAUA2T9W9ZCxgkh9K3L+RF7nEB A3CxM0SZXj80vYL+RvyklEVOclhpUIqWioSQ4ckxVBNnXKK/l3wWf0YU6 IvUx/veXfk858/tR26c+eICDf3mOrCfqXJ/bXZbSUKCQwVCjotjK2jlj6 4uVVMwADLOOsAtn/sqb+5HZdYlT8RcY5iKc0gAJPJnciv45nOUpNM+nq/ /z6HF8wgJQkE+RjVgom5tiszLZmQMxoWdsQjuFfyMxJCQfeyycETeSJ9c Q==; X-CSE-ConnectionGUID: l1EnNMAoSaamdFf7tplg0Q== X-CSE-MsgGUID: iW0/bdKbRti3/8DpmWoe6w== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="32217432" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217432" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:53:46 -0700 X-CSE-ConnectionGUID: kk8iWaCaQWaPgmeokZ7vdQ== X-CSE-MsgGUID: 7Fq9b19GTei6O0qhbYH/RA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761573" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:53:43 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 01/10] x86/mce/dev-mcelog: Use xchg() to get and clear the flags Date: Wed, 16 Oct 2024 20:30:27 +0800 Message-Id: <20241016123036.21366-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Using xchg() to atomically get and clear the MCE log buffer flags, streamlines the code and reduces the text size by 20 bytes. $ size dev-mcelog.o.* text data bss dec hex filename 3013 360 160 3533 dcd dev-mcelog.o.old 2993 360 160 3513 db9 dev-mcelog.o.new No functional changes intended. Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/dev-mcelog.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/dev-mcelog.c b/arch/x86/kernel/cpu/mce/dev-mcelog.c index af44fd5dbd7c..8d023239ce18 100644 --- a/arch/x86/kernel/cpu/mce/dev-mcelog.c +++ b/arch/x86/kernel/cpu/mce/dev-mcelog.c @@ -264,15 +264,8 @@ static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, return put_user(sizeof(struct mce), p); case MCE_GET_LOG_LEN: return put_user(mcelog->len, p); - case MCE_GETCLEAR_FLAGS: { - unsigned flags; - - do { - flags = mcelog->flags; - } while (cmpxchg(&mcelog->flags, flags, 0) != flags); - - return put_user(flags, p); - } + case MCE_GETCLEAR_FLAGS: + return put_user(xchg(&mcelog->flags, 0), p); default: return -ENOTTY; } From patchwork Wed Oct 16 12:30:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838439 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40A76208D9B; Wed, 16 Oct 2024 12:53:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083234; cv=none; b=IhVXaaMfClenndkyuv1OIaC/u4EwiSwBfhwt8M64krPuiM1AJ0tAH6CjxMRVMSN5pxAGOEypPgbKkplSK6yKOmg0DUbGFEtSzePw4IuKUbl+iodk1Hp19wlSHBW5+0NJrg5wPDrri66+w/a7wd8O4t/NYctTZZlBPVQy0XpAe8E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083234; c=relaxed/simple; bh=STq49VgFTjC4bsmrekCYbkUCId2+j1NN0xhOE6YrKbU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=W+umLppO7i2ZFrnTYJ011OvGTsgDhDSMJ1MUfaTGa++fhimv8CjOAwJqxPs+8hsKnq6x2k+lo8mY1E3IkWWnXYM6tTubWPtIKud2G6pMSTBl0R4odMPnqqB/JdDu8s23bKFb3qenBy9ySTsfa6T0dgN0/V/IzmVQFzEG859XiA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gamnV1Rt; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gamnV1Rt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729083234; x=1760619234; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=STq49VgFTjC4bsmrekCYbkUCId2+j1NN0xhOE6YrKbU=; b=gamnV1Rtw6N7MjJcRPLVqwTir5XyLMLknC81wwt5ZjtFDQkUtBvBJxO2 ee7j/j6hPqmQZDhfB8ka6Yhx+CB2mzQV8+LnkJyo1QfmRqgp/ag1Z89Y1 VKLaxeAif8UivgrNYvp5P6A1BbMUjcqWFPqKgvzirSvS6wM6QuKMZjKmZ r7xHKGYVm/OYXvF5u2+0p7KgpdUpOfdsFiT4wT8lzGzStyFBJ4EvdvyBH 4eacYO+5ycg54jaJoRWc1hgJ4lcT/sIzEvCNQGzsLvcA3/1K8BUvGr9ja qQpkHWqQUAEAnqD/FQbHb+SnYYljUYnhU72vmZmaYLISlO61g0KIw8kjy w==; X-CSE-ConnectionGUID: Ox/PTSZwRI+u8wEvKLHdGg== X-CSE-MsgGUID: Ivhb6GYsSNm0sljAOWgarQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="32217455" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217455" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:53:54 -0700 X-CSE-ConnectionGUID: p2on59plT9C3dwkRvVzGAw== X-CSE-MsgGUID: ls2+J2bsQjWhJkWPQ8OB8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761596" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:53:50 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 02/10] x86/mce/intel: Use MCG_BANKCNT_MASK instead of 0xff Date: Wed, 16 Oct 2024 20:30:28 +0800 Message-Id: <20241016123036.21366-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Use the predefined MCG_BANKCNT_MASK macro instead of the hardcoded 0xff to mask the bank number bits. No functional changes intended. Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f6103e6bf69a..b3cd2c61b11d 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -94,7 +94,7 @@ static int cmci_supported(int *banks) if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0; rdmsrl(MSR_IA32_MCG_CAP, cap); - *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); + *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); } From patchwork Wed Oct 16 12:30:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838440 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31187208972; Wed, 16 Oct 2024 12:54:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083244; cv=none; b=UGpVl6s+otTfzYziQyOfJlg/pLOBTMp7MuvPFOi+vuBsnrkMMBZrHzrwoHSX8esMr/wHU0aLO4x5hniQlCZF75fiEcIYfW2U3biZ431x891/79ybrE7GcMhdJD+p7neBMjF43MhE7vsu0B8h9BHDwHWEAPsJ3EdbNvAXTdmjKEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083244; c=relaxed/simple; bh=baLCTu2I4/nxgTNGcbcjWclVx9FiepeCwl/VhbSl0vM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=WZ+sGLhnLaVKCW19ZqPZCqTJXqUjLujYhwCeWdAkCprYV46RYJuR4uS5JrfG29jPcY0zen+QOcIW/twVktIk1Ml7Vyh8zolz/G0qrSuQrLhxTQo0jIqvWhoK+H2CNbK6FHgPCNV8Yj9rVeDDKjcKyNHh4vDZTV9GMfbUns50bbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B6fjWgs4; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B6fjWgs4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729083244; x=1760619244; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=baLCTu2I4/nxgTNGcbcjWclVx9FiepeCwl/VhbSl0vM=; b=B6fjWgs4NGZUdxeI/U+qwBVTSFaPiqq+rIOkaiOGv87o48ftFyZIusFQ 29eahR1OPCRUZkDZ5UBe8OJOYEH31ejMqyQS4LEFSU+l8xzBT7YTIHwoZ 5cBWLi/5AHlvU4y/vPAC1tZ7ZBReIQ7+K62CQXRFp8R69S+HmRiEdpnUu dJ7WcNWIW/sruq0XZbDZje8LwK5m81x3IGmjQgsdwrc6nhLI7cDNyqt5l 8M00ZGd53expx8gvMtpx0l1fcQQA/P4BxlJ+CddiHc4wmrK0JmCDh9Loo UYZwSzscrFGfT6a+nbISVxvw9MVaE8jNayIwnD5oEG3Orz4jfPl7Z1FcW w==; X-CSE-ConnectionGUID: Lt4Mm8ybStucl8UZ35Almg== X-CSE-MsgGUID: xl5c98edTTGtcWcBDgXskQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="32217483" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217483" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:03 -0700 X-CSE-ConnectionGUID: SHAd4ewgTiCBYrsOrApMhw== X-CSE-MsgGUID: TgBZGl2yQiSX3y05GpeDNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761621" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:00 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 03/10] x86/mce: Make several functions return bool Date: Wed, 16 Oct 2024 20:30:29 +0800 Message-Id: <20241016123036.21366-4-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make several functions that return 0 or 1 return a boolean value for better readability. No functional changes are intended. Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/include/asm/mce.h | 4 ++-- arch/x86/kernel/cpu/mce/amd.c | 10 +++++----- arch/x86/kernel/cpu/mce/core.c | 22 +++++++++++----------- arch/x86/kernel/cpu/mce/intel.c | 9 +++++---- 4 files changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3b9970117a0f..7a01bb5b19d3 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -244,7 +244,7 @@ static inline void cmci_rediscover(void) {} static inline void cmci_recheck(void) {} #endif -int mce_available(struct cpuinfo_x86 *c); +bool mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); bool mce_usable_address(struct mce *m); @@ -264,7 +264,7 @@ enum mcp_flags { void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); -int mce_notify_irq(void); +bool mce_notify_irq(void); DECLARE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 14bf8c232e45..4dae9841ee38 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -381,7 +381,7 @@ static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) return msr_high_bits & BIT(28); } -static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) +static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; @@ -389,7 +389,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } if (apic != msr) { @@ -399,15 +399,15 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) * was set is reserved. Return early here: */ if (mce_flags.smca) - return 0; + return false; pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } - return 1; + return true; }; /* Reprogram MCx_MISC MSR behind this threshold bank. */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2a938f429c4d..725c1d6fb1e5 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -479,10 +479,10 @@ static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) } } -int mce_available(struct cpuinfo_x86 *c) +bool mce_available(struct cpuinfo_x86 *c) { if (mca_cfg.disabled) - return 0; + return false; return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); } @@ -1748,7 +1748,7 @@ static void mce_timer_delete_all(void) * Can be called from interrupt context, but not from machine check/NMI * context. */ -int mce_notify_irq(void) +bool mce_notify_irq(void) { /* Not more than two messages every minute */ static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); @@ -1759,9 +1759,9 @@ int mce_notify_irq(void) if (__ratelimit(&ratelimit)) pr_info(HW_ERR "Machine check events logged\n"); - return 1; + return true; } - return 0; + return false; } EXPORT_SYMBOL_GPL(mce_notify_irq); @@ -1985,25 +1985,25 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) return 0; } -static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) { if (c->x86 != 5) - return 0; + return false; switch (c->x86_vendor) { case X86_VENDOR_INTEL: intel_p5_mcheck_init(c); mce_flags.p5 = 1; - return 1; + return true; case X86_VENDOR_CENTAUR: winchip_mcheck_init(c); mce_flags.winchip = 1; - return 1; + return true; default: - return 0; + return false; } - return 0; + return false; } /* diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index b3cd2c61b11d..f863df0ff42c 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -75,12 +75,12 @@ static u16 cmci_threshold[MAX_NR_BANKS]; */ #define CMCI_STORM_THRESHOLD 32749 -static int cmci_supported(int *banks) +static bool cmci_supported(int *banks) { u64 cap; if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce) - return 0; + return false; /* * Vendor check is not strictly needed, but the initial @@ -89,10 +89,11 @@ static int cmci_supported(int *banks) */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) - return 0; + return false; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) - return 0; + return false; + rdmsrl(MSR_IA32_MCG_CAP, cap); *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); From patchwork Wed Oct 16 12:30:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838441 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 167D3208972; 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a="32217507" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217507" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:12 -0700 X-CSE-ConnectionGUID: z7He18iMS02ZPMB8kTHUNQ== X-CSE-MsgGUID: Tz0IwFCGQa2QONFSeTUyaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761701" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:09 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 04/10] x86/mce/threshold: Remove the redundant this_cpu_dec_return() Date: Wed, 16 Oct 2024 20:30:30 +0800 Message-Id: <20241016123036.21366-5-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The 'storm' variable points to this_cpu_ptr(&storm_desc). Access the 'stormy_bank_count' field through the 'storm' to avoid calling this_cpu_*() on the same per-CPU variable twice. This minor optimization reduces the text size by 16 bytes. $ size threshold.o.* text data bss dec hex filename 1395 1664 0 3059 bf3 threshold.o.old 1379 1664 0 3043 be3 threshold.o.new No functional changes intended. Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/threshold.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/threshold.c index 89e31e1e5c9c..f4a007616468 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -90,7 +90,7 @@ void cmci_storm_end(unsigned int bank) storm->banks[bank].in_storm_mode = false; /* If no banks left in storm mode, stop polling. */ - if (!this_cpu_dec_return(storm_desc.stormy_bank_count)) + if (!--storm->stormy_bank_count) mce_timer_kick(false); } From patchwork Wed Oct 16 12:30:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838442 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AE5420B20E; Wed, 16 Oct 2024 12:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083263; cv=none; b=XApu5N+8qxIp9gNKHUU21FeXxdmZ7za7wDZfHxiqEIKROevAdmpiOvePM1uOuzoEo5D43ChQfpqRv1wgibs0Tn9a/ggVG2TW6pJHXJzm/DYMbIpfDf72NdLGVDeHKMKgfTqyW3i0i0jjUf/b8k+KyWMlQ2bP7gJXlMj8HtLMDZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083263; c=relaxed/simple; bh=MbKH8dcNnkOxWPr1G1R/YGSLnrrcDN1t2+TEHYcZEW4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=SaKvSrL7dbJoy/8pgnaWr7gj196ohz29qHYEfrC6wGormr0sCbAlPH6ZTCDDlZ6WKhqzCGhOgke+oifWWztd/vT8WdIdYi6UYzEuCoBBV8r8rFdhM8tqXEXo8YRHFcMmXGPatLM1sl1hozlBD+m7P6LPnR42TZH/FPmKP8tE/f4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=c6zfK92L; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="c6zfK92L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729083262; x=1760619262; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=MbKH8dcNnkOxWPr1G1R/YGSLnrrcDN1t2+TEHYcZEW4=; b=c6zfK92L+JBuV0oh+lQZ0PbquR5/34AhhLdgPInVLw32v10LgYpBvFE+ SL3qpeLq74wRRuJmXjHSXVUBM9hgxH/4tVHsRgtbKnCzI/ycP85iziJJ+ k8zBy9N+F3Cvtqxq0Hdn9iYx7koJN/CNasr+OhDoHcoaDI9DtlSYDdHBB ldQ9mydiWshQHGrPZ5SB+OzXEdUbe3MrEqran3fGScqmGOZnctRUSDG8Q Oiw0DVueMsbOBy/1/C0cD5Ahn6DFljc3X4naV85q3Cgj5jsI1hCFOz4Cp YadqZ+gZyAGlbyIUrVHErXxIMXoUEMzRNVaecjyiXORtRS2Mn3m+ghLaT A==; X-CSE-ConnectionGUID: Cgue9l6eQXycdzhvjDCwWw== X-CSE-MsgGUID: ZcwSDOgQQ1GCA105waLu2w== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="32217530" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217530" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:19 -0700 X-CSE-ConnectionGUID: gutIEPBOQEmdkSUTdhJYuA== X-CSE-MsgGUID: 3iUoe84zR+G79qC3HrUwjQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761713" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:16 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 05/10] x86/mce/genpool: Make mce_gen_pool_create() return explicit error codes Date: Wed, 16 Oct 2024 20:30:31 +0800 Message-Id: <20241016123036.21366-6-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make mce_gen_pool_create() return explicit error codes for better readability. No functional changes intended. Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/genpool.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/genpool.c index 4284749ec803..ffa28769dea6 100644 --- a/arch/x86/kernel/cpu/mce/genpool.c +++ b/arch/x86/kernel/cpu/mce/genpool.c @@ -120,20 +120,20 @@ static int mce_gen_pool_create(void) { int mce_numrecords, mce_poolsz, order; struct gen_pool *gpool; - int ret = -ENOMEM; void *mce_pool; + int ret; order = order_base_2(sizeof(struct mce_evt_llist)); gpool = gen_pool_create(order, -1); if (!gpool) - return ret; + return -ENOMEM; mce_numrecords = max(MCE_MIN_ENTRIES, num_possible_cpus() * MCE_PER_CPU); mce_poolsz = mce_numrecords * (1 << order); mce_pool = kmalloc(mce_poolsz, GFP_KERNEL); if (!mce_pool) { gen_pool_destroy(gpool); - return ret; + return -ENOMEM; } ret = gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1); if (ret) { @@ -144,7 +144,7 @@ static int mce_gen_pool_create(void) mce_evt_pool = gpool; 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16 Oct 2024 05:54:23 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 06/10] x86/mce: Convert multiple if () statements into a switch() statement Date: Wed, 16 Oct 2024 20:30:32 +0800 Message-Id: <20241016123036.21366-7-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Convert the multiple if() statements used for vendor differentiation into a switch() statement for better readability. As a bonus, the size of new generated text is reduced by 16 bytes. $ size core.o.* text data bss dec hex filename 21364 4181 3776 29321 7289 core.o.old 21348 4181 3776 29305 7279 core.o.new No functional changes intended. Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 725c1d6fb1e5..40672fe0991a 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1892,7 +1892,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) } /* This should be disabled by the BIOS, but isn't always */ - if (c->x86_vendor == X86_VENDOR_AMD) { + switch (c->x86_vendor) { + case X86_VENDOR_AMD: if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { /* * disable GART TBL walk error reporting, which @@ -1925,9 +1926,9 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) if (c->x86 >= 0x17 && c->x86 <= 0x1A) mce_flags.zen_ifu_quirk = 1; - } + break; - if (c->x86_vendor == X86_VENDOR_INTEL) { + case X86_VENDOR_INTEL: /* * SDM documents that on family 6 bank 0 should not be written * because it aliases to another special BIOS controlled @@ -1964,9 +1965,10 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) */ if (c->x86_vfm == INTEL_SKYLAKE_X) mce_flags.skx_repmov_quirk = 1; - } - if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { + break; + + case X86_VENDOR_ZHAOXIN: /* * All newer Zhaoxin CPUs support MCE broadcasting. Enable * synchronization with a one second timeout. @@ -1975,6 +1977,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) if (cfg->monarch_timeout < 0) cfg->monarch_timeout = USEC_PER_SEC; } + + break; } if (cfg->monarch_timeout < 0) From patchwork Wed Oct 16 12:30:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838444 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6427C208D96; Wed, 16 Oct 2024 12:54:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083274; cv=none; b=QXj1SDWL5cRDkXqKJrB9EAiBgasCnfekjxx5OF0vdq6DEMl9UqBpOIJc5KEGvjqkwzJvgIVIIcYx1Kp+hygpjEc6AiBSHpOeO0aVdMTbJsvYgIQWulntfo3+Rp5N984QTfL3xwxvXdnayU3dSrx3MLph9Hc9O9qwZXw2COQ3Ac8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083274; c=relaxed/simple; bh=Lu2yXq/iVgwWk6JO6I4lyOArDv2F7LCVIqz5PYCiwv8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=n8up7aGPTNq9DJgfnLMpl6l3r7lSphy+td4il7IdClkdl2SR2XId4ClUW2gMlD44/hQjwnuej39PYGR+AK5q5bLJ1gTHUbk0dUjNVT+87Xn/2e82q/owtjUvCFJZm5EmHieTMNRWm6AzAPiOsVeAZqVmi2XZNg/w7+dcFfqebrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=grwNFr5n; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="grwNFr5n" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729083274; x=1760619274; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Lu2yXq/iVgwWk6JO6I4lyOArDv2F7LCVIqz5PYCiwv8=; b=grwNFr5n/1LPnuvKmZuL4jDSYN68RPP6FvRkTXmDQ6tO0bckn4wOlApz LImucOwxOwTuD3koqWw2jQEZpKkK9GKEB1FtzijrZJj+qyv6AeIuKDQw8 CGhank0Eqp54iQEjJNMfvfYNX9TPMYYeGbs6Ld37rX7gvk1A/TU7RO5hn lX1ppMPwNk4wjnQUYJmEsPpeR0fHKywNYodphH1UHOtBaTTFcp9MJmES1 c2J3fj4z7zOg0RBMJHPTM2O5STrLYTHXlhoqdXEx+NlbNEZcpTqCpEW+k WeXh39iW41K6othRNogoljiw7xzYGgigLrLUExAQkK6xuL8fzmO8w3rI9 g==; X-CSE-ConnectionGUID: HEbt3Ro8REmQdYLFtl6SsA== X-CSE-MsgGUID: fvVQr7p8REmrQsPr0T4aug== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="32217570" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217570" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:34 -0700 X-CSE-ConnectionGUID: qeNRCg39QKydcZZVRVQCWw== X-CSE-MsgGUID: FpEh9+IaQhSZ4qmPeZoEeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761733" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:30 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 07/10] x86/mce: Remove the unnecessary {} Date: Wed, 16 Oct 2024 20:30:33 +0800 Message-Id: <20241016123036.21366-8-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Remove the unnecessary {} from the case statement. Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 40672fe0991a..e718b9bbe8e5 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2073,10 +2073,9 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_intel_feature_init(c); break; - case X86_VENDOR_AMD: { + case X86_VENDOR_AMD: mce_amd_feature_init(c); break; - } case X86_VENDOR_HYGON: mce_hygon_feature_init(c); From patchwork Wed Oct 16 12:30:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838445 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D10420C49D; Wed, 16 Oct 2024 12:54:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083284; cv=none; b=PsogW3evZ7Ail59wIC8EYKesZC3fCxtDQ3WHfJ3QQrZynsHfSjEl0L+MM7YRlY49DLau/idRvfdYA8htztzRnSBjocIO4HzxhTX3ALPepAiTbIAzZAipm7NYH7wPiiDmKlJlvcuqEnJ1wg7e9xKN8AteDdvnYP4gxthQMi5VHXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083284; c=relaxed/simple; bh=2ls6pglQHV/bEvjP70YtkNvbmLntN02ye5RgwZfXdb0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=GOL6EKSVCmrhAxJrr6R2ESCNNfUoUBL3Fd1Qxrro+FlIgwkmMOuUFsCIztuMTtuve4+A5DnJEDf1MkRSYJS9uHgv96YKQsq4y9hfQFhdiEP+XCk2Tj4SOPbDlaoj16daSg+J0fvMGTLI7iFmXy7y9vVDgKbzTOlpuzP01LhDeQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XCpL7VMd; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XCpL7VMd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729083284; x=1760619284; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=2ls6pglQHV/bEvjP70YtkNvbmLntN02ye5RgwZfXdb0=; b=XCpL7VMdiy+VZM4nESksOKIkBv8J+ZvpZ/dpQV8k0I893YawPFjA51Ir tRL5Vdcng+gM/gPYq00Z2tTYaeD7Qs7X3yHroUKWmRtmCbmmbauvs5vKZ eUIm3xq8VnQtOmtH0T8xd86ZQ7BXDHxMTkDUENMKj3X1OpcXknu/Fj9lB DqEcms5SGeyz0rapr6CZJ9FBMXZ78MdQv7pLoM2ULLyQOXKLwu9bYyJlM T9bTjfpkqrdlgaZsWsOuRpdoYoUNkEL54sm125LSK2TodvDU77ENc93RO 6ENRN8/3XZLNPz5GxaEZjk+kioDJZVT7Zn7i6HjX45McVC42zyYOvYMpJ w==; X-CSE-ConnectionGUID: 2ZN8cLstTTWLX1l06CTIDA== X-CSE-MsgGUID: oXVqUbOJRaahlM8kfJwNFw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="32217603" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217603" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:43 -0700 X-CSE-ConnectionGUID: fXwKWwI8TzyXmVBle256IQ== X-CSE-MsgGUID: b2HARNm0SXig/YsOZkLNig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761741" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:40 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 08/10] x86/mce: Remove the redundant zeroing assignments Date: Wed, 16 Oct 2024 20:30:34 +0800 Message-Id: <20241016123036.21366-9-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: As the entire mce structure is initialized to zero using memset(0) within mce_gather_info(), remove the redundant zeroing assignments to mce->misc and mce->addr. This results in a reduction of 64 bytes in the text size. $ size core.o.* text data bss dec hex filename 21348 4181 3776 29305 7279 core.o.old 21284 4181 3776 29241 7239 core.o.new Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index e718b9bbe8e5..844a6f8d6f39 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -706,8 +706,6 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) if (!mce_banks[i].ctl || !test_bit(i, *b)) continue; - m.misc = 0; - m.addr = 0; m.bank = i; barrier(); @@ -1284,8 +1282,6 @@ __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, if (!mce_banks[i].ctl) continue; - m->misc = 0; - m->addr = 0; m->bank = i; m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); From patchwork Wed Oct 16 12:30:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13838446 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7BDE20C49D; Wed, 16 Oct 2024 12:54:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083291; cv=none; b=gSTohC2bpe8InTkI4cbp1OoYPeiiKa5SWG7+JJWAvHr65+r/bc9p0fnxa7zjW6zm9tPq4hEqCqe0dcTRr5ft2/zEyrKawS9PTgAxJakw+QZcm2PfyDTOA+lPmFDl8wT/mlOjjvcnaiVht1EGeOmmt5xW/BdB+HA8nmiFl8uV8x8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729083291; c=relaxed/simple; bh=sHQnHU4YJZwxBEj+lS+LwItMio6kPRE+zOl/Zicz/MU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=prIOaI8hUi5eNbnyHJRw/MuIfWXZs6ni3cSFvQu9i/eNcHeo21Zw4Tl5/XPiTRdF7X17LTy5TJW3UAWn76T020/tA1cKXeNCwjtb3KTphRX1nVt8gtYOSn8A4cms4GNkfIG8rpW5PcIlNNOcx6d++l/ml976mqiEiKLYKlYYbbE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FnYazaK2; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FnYazaK2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729083291; x=1760619291; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=sHQnHU4YJZwxBEj+lS+LwItMio6kPRE+zOl/Zicz/MU=; b=FnYazaK2ZlJ+bKBdrQWppN1xTnYkWEp4tyMlTnMpqm/WDk9g4D9adH4g 5gIXk1INup3yvYOumk2ym2acPaDvEo6wYI3Axuqs9fFDse3S5RY3Q5WxL PFTP/lIKedyUTHO69/MwlWxFyqMrM+nn/3MmCWnIn7XzZWPnU2rP+ohuz +UxKyqQjij3hlt4K3BV8UX6l8u6EpLPhMfgn/ntyE/HOHMKFgTEdf/m8P 66GjPZpiJyV6JaetwSNzJRNYIV3EE08Njk/Xkk0vpaeJStTwA+8C6pJJA J/RGdv8NoFKS06O+TRu5GZ294OS9w0Q95ppW7okwYYIAj4zIU0YGZI9oZ w==; X-CSE-ConnectionGUID: Hp9BPydvRbOTZWJmo17iMw== X-CSE-MsgGUID: 74yQ9ilLSg6yxKQryyD/cQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="32217630" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="32217630" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:50 -0700 X-CSE-ConnectionGUID: Oz93yXp+Qnal0A4VzcHQQw== X-CSE-MsgGUID: JVIzqzfgTmOmYFoqMxyZjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761762" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:47 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 09/10] x86/mce/amd: Remove unnecessary NULL pointer initializations Date: Wed, 16 Oct 2024 20:30:35 +0800 Message-Id: <20241016123036.21366-10-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: As the variables {pos, tmp, block, first_block} are all initialized prior to their use, remove the unnecessary NULL pointer initializations. Signed-off-by: Qiuxu Zhuo --- Changes in v2: - Update the commit message to add the left out variable names {block, first_block} that this patch also fixes. arch/x86/kernel/cpu/mce/amd.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 4dae9841ee38..aecea842dac2 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -917,8 +917,8 @@ static void log_and_reset_block(struct threshold_block *block) */ static void amd_threshold_interrupt(void) { - struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; struct threshold_bank **bp = this_cpu_read(threshold_banks); + struct threshold_block *first_block, *block, *tmp; unsigned int bank, cpu = smp_processor_id(); /* @@ -1197,8 +1197,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb static int __threshold_add_blocks(struct threshold_bank *b) { struct list_head *head = &b->blocks->miscj; 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d="scan'208";a="32217654" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:57 -0700 X-CSE-ConnectionGUID: zaX0CHllRP+E2NiHohI2Zg== X-CSE-MsgGUID: d54RCjMzRJ+vNid0sTGXig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="82761777" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 05:54:54 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v2 10/10] x86/mce: Fix typos in comments Date: Wed, 16 Oct 2024 20:30:36 +0800 Message-Id: <20241016123036.21366-11-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241016123036.21366-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> <20241016123036.21366-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Fix the following typos in comments: s/callin/calling/ s/TBL/TLB/ Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 844a6f8d6f39..19e6730e7c22 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1118,7 +1118,7 @@ static noinstr int mce_start(int *no_way_out) } else { /* * Subject: Now start the scanning loop one by one in - * the original callin order. + * the original calling order. * This way when there are any shared banks it will be * only seen by one CPU before cleared, avoiding duplicates. */ @@ -1892,7 +1892,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) case X86_VENDOR_AMD: if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { /* - * disable GART TBL walk error reporting, which + * disable GART TLB walk error reporting, which * trips off incorrectly with the IOMMU & 3ware * & Cerberus: */