From patchwork Wed Oct 16 13:23:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF592D1AD55 for ; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9132510E6F1; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lSYUn/x3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C80F10E097 for ; Wed, 16 Oct 2024 13:23:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729085039; x=1760621039; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=65ycK15O+/IKYXrFh2HNIMWwDNT+50/fGQV2iI4QzlM=; b=lSYUn/x3zkyp27jno0RJnUp9hBxXf0eb29SSLmSjErA88kt0Lr/aE6ex X7QozlFDc0zjqjsirAHJrzsAhtHdSkrogqYzRbihRSSlbS+hbzve1T2Yq V8UqFY/8/AZEnL2bFDtbajZUlSA4GRY2+GeHwlVdhO28FKpxmTF02a4fC EOm7OdNPlCwzyRPwmUhn2IziRxoS5TXtGBj5dXbXAn0GMDUKUUmBR88vc +4j5LQGGItUeHSvQrwR2w6z3JNBKtgOZMJLPfpN6LyaSj8lnd33ZboH5E qrZvsOMbgyDLorLQcJzj1CpWQHUM4FUWo/mHXVmPHVphXnPI5K+ZkLQUR g==; X-CSE-ConnectionGUID: s1D0EI6rRXiXuMwCLn+2Gg== X-CSE-MsgGUID: xHl2tZEHRzao5uUlJ03cNg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46005962" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005962" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:38 -0700 X-CSE-ConnectionGUID: RXkvetjcTdi9swFWRV/lEA== X-CSE-MsgGUID: mNit2CDQTL2PwxirzZuXpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384452" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:37 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 1/8] drm/i915/dp: Flush modeset commits during connector detection Date: Wed, 16 Oct 2024 16:23:58 +0300 Message-ID: <20241016132405.2231744-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make sure that a DP connector detection doesn't happen in parallel with an ongoing modeset on the connector. The reasons for this are: - Besides reading the capabilities, EDID etc. the detection may change the state of the sink (via the AUX bus), for instance by setting the LTTPR mode or the source OUI (the latter introduced by an upcoming patch). It's better to avoid such changes affecting an onging modeset in any way. - During a modeset's link training any access to DPCD registers, besides the registers used for link training should be avoided, at least in the LTTPR non-transparent and transparent link training modes. Such asynchronous accesses - besides connector detection - can also happen via the AUX device node for instance, for those a parallel modeset will have to be avoided in a similar way to the change in this patch. (A topic for a follow-up change.) - The source OUI written to an eDP sink is valid only while the panel power is enabled. A modeset on eDP will enable/disable the panel power synchronously; this should be prevented in the middle of the connector detection, to ensure a consistent sink state (which depends on the source OUI) for the whole duration of detection. The panel power could still get disabled during detection after an idle period (1 sec), this will be prevented by the next patch. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 28 ++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6b27fabd61c37..977ff2ce18eeb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5035,6 +5035,16 @@ bool intel_dp_has_connector(struct intel_dp *intel_dp, return false; } +static void wait_for_crtc_hw_done(struct drm_i915_private *i915, struct drm_crtc_commit *commit) +{ + if (!commit) + return; + + drm_WARN_ON(&i915->drm, + !wait_for_completion_timeout(&commit->hw_done, + msecs_to_jiffies(5000))); +} + int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) @@ -5071,10 +5081,7 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, if (!crtc_state->hw.active) continue; - if (conn_state->commit) - drm_WARN_ON(&i915->drm, - !wait_for_completion_timeout(&conn_state->commit->hw_done, - msecs_to_jiffies(5000))); + wait_for_crtc_hw_done(i915, conn_state->commit); *pipe_mask |= BIT(crtc->pipe); } @@ -5083,6 +5090,17 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, return ret; } +void intel_dp_flush_connector_commits(struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct drm_connector_state *conn_state = + connector->base.state; + + drm_modeset_lock_assert_held(&i915->drm.mode_config.connection_mutex); + + return wait_for_crtc_hw_done(i915, conn_state->commit); +} + static bool intel_dp_is_connected(struct intel_dp *intel_dp) { struct intel_connector *connector = intel_dp->attached_connector; @@ -5596,6 +5614,8 @@ intel_dp_detect(struct drm_connector *connector, if (!intel_display_driver_check_access(dev_priv)) return connector->status; + intel_dp_flush_connector_commits(intel_connector); + /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) status = edp_detect(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 60baf4072dc9d..4efb9605a50e0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -54,6 +54,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); +void intel_dp_flush_connector_commits(struct intel_connector *connector); void intel_dp_link_check(struct intel_encoder *encoder); void intel_dp_check_link_state(struct intel_dp *intel_dp); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1a2ff3e1cb68f..5bba078c00d89 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1573,6 +1573,8 @@ intel_dp_mst_detect(struct drm_connector *connector, if (!intel_display_driver_check_access(i915)) return connector->status; + intel_dp_flush_connector_commits(intel_connector); + return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr, intel_connector->port); } From patchwork Wed Oct 16 13:23:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D934D1AD56 for ; Wed, 16 Oct 2024 13:24:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD20110E097; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RfHbNV+q"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 131DB10E097 for ; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729085040; x=1760621040; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=nUHUswlhZeq/c1Kd/ZJXaP2AdBqFH4uV/FByCavLIlI=; b=RfHbNV+qnVL3wCnAOaA+dA9lXHss0yTwkyqPbIIHkPy5/AawDZRXuL3m 2mpB2Taks8bkcaESejvDCYqX7QszlUwKeuIk/pGCBmqQ82D4nPv8bO9WA TfCWYwNlmMPKCFoiYJ0C55Y/+2t0FsnHPxA4sebxDaHRiyT4L0MaqEzLX mD/xDQWHCX5uQNpMD7WF/AivQ3MO2hXShYqyfVgsoUSo63PraKYWVG9IF 5qPi7J3trWjp1IyR8x17M+G3OyfJDYU+nvAAvQvyBiKWypAUCs6yfpJKI WORD4D4mpCd5qSNPk2Q3vu1FiNup9BvH2y4jEr7+HwS1ZGG+a0IET8xml A==; X-CSE-ConnectionGUID: F8WDSVpSS0a1zFC/qLfS/Q== X-CSE-MsgGUID: eMkYL+Y3Sn+ZB24jJ9G49A== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46005967" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005967" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:39 -0700 X-CSE-ConnectionGUID: W1oK+7mVToOQXM0Fn1FvBQ== X-CSE-MsgGUID: tjnbPiyNQ2SZiBwcjGXgFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384454" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:38 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 2/8] drm/i915/dp: Ensure panel power remains enabled during connector detection Date: Wed, 16 Oct 2024 16:23:59 +0300 Message-ID: <20241016132405.2231744-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The sink's capabilities, like the DSC caps, depend on the source OUI written to the sink's DPCD registers and so this OUI value should be valid for the whole duration of the detection. An eDP sink will reset this OUI value when the panel power is disabled, so prevent the disabling - happening by default after a 1 sec idle period - for the whole duration of detection. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++----- drivers/gpu/drm/i915/display/intel_pps.c | 11 +++++++++++ drivers/gpu/drm/i915/display/intel_pps.h | 1 + 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 977ff2ce18eeb..3da06d25bc4ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5616,6 +5616,8 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_flush_connector_commits(intel_connector); + intel_pps_vdd_on(intel_dp); + /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) status = edp_detect(intel_dp); @@ -5646,12 +5648,15 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_tunnel_disconnect(intel_dp); - goto out; + goto out_unset_edid; } ret = intel_dp_tunnel_detect(intel_dp, ctx); - if (ret == -EDEADLK) - return ret; + if (ret == -EDEADLK) { + status = ret; + + goto out_vdd_off; + } if (ret == 1) intel_connector->base.epoch_counter++; @@ -5679,7 +5684,7 @@ intel_dp_detect(struct drm_connector *connector, * with EDID on it */ status = connector_status_disconnected; - goto out; + goto out_unset_edid; } /* @@ -5708,7 +5713,7 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_check_device_service_irq(intel_dp); -out: +out_unset_edid: if (status != connector_status_connected && !intel_dp->is_mst) intel_dp_unset_edid(intel_dp); @@ -5717,6 +5722,9 @@ intel_dp_detect(struct drm_connector *connector, status, intel_dp->dpcd, intel_dp->downstream_ports); +out_vdd_off: + intel_pps_vdd_off(intel_dp); + return status; } diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index ffeee9daa5689..64f1f7ea94993 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -950,6 +950,17 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync) edp_panel_vdd_schedule_off(intel_dp); } +void intel_pps_vdd_off(struct intel_dp *intel_dp) +{ + intel_wakeref_t wakeref; + + if (!intel_dp_is_edp(intel_dp)) + return; + + with_intel_pps_lock(intel_dp, wakeref) + intel_pps_vdd_off_unlocked(intel_dp, false); +} + void intel_pps_on_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h index bc5046d536264..c83007152f07d 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.h +++ b/drivers/gpu/drm/i915/display/intel_pps.h @@ -34,6 +34,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp); void intel_pps_check_power_unlocked(struct intel_dp *intel_dp); void intel_pps_vdd_on(struct intel_dp *intel_dp); +void intel_pps_vdd_off(struct intel_dp *intel_dp); void intel_pps_on(struct intel_dp *intel_dp); void intel_pps_off(struct intel_dp *intel_dp); void intel_pps_vdd_off_sync(struct intel_dp *intel_dp); From patchwork Wed Oct 16 13:24:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1F19D1AD56 for ; Wed, 16 Oct 2024 13:24:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D99C10E6FD; Wed, 16 Oct 2024 13:24:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kN1UldbT"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3665210E097 for ; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729085040; x=1760621040; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=snogfWKry1NK+xutXL5UIFaGlIhlrbu9xtQzAQEAtyo=; b=kN1UldbTouT1yl00tROwEg1xzxViSZXbJySkZqbvIhIJd1ZkHnaMTKmX UjXG2U/dJhcogGqsl3DRi7YkfD3rPwiwRHuk9KgYeNTzFwgKyPZJtteAn y1k2ahf1+savow/IFGVejAgH+IcvX06eBmUmkGxDQzPZddvUuzuAi4oq4 2kxynKhRm5KyDEp6XU0p45QrNUfuyzS52Dtb+H8WJHKrwsDhM/9oqzDrI eVUYkaix7x+Xs7kRW0REET1QUe326I33JGjuYRTQlIY4MMkymO18zCMzi IOgLocjMxpLgKg6lwGDAXsLAXbMhBx2eKF5IJBSm2q7j8ohIHkqy6w7iN w==; X-CSE-ConnectionGUID: rZAGUDNyRB+1+kZNyg5AVg== X-CSE-MsgGUID: nGZ9a++dTp6xVMIoey7dgw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46005970" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005970" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:40 -0700 X-CSE-ConnectionGUID: FOUB25nhRUKH5ObGLFL+9g== X-CSE-MsgGUID: i4DZhxFNQn2psI49uo+CEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384455" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:39 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 3/8] drm/i915/dp: Initialize the source OUI write timestamp always Date: Wed, 16 Oct 2024 16:24:00 +0300 Message-ID: <20241016132405.2231744-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If the source OUI DPCD register value matches the expected Intel OUI value, the write timestamp doesn't get updated leaving it at the 0 initial value if the OUI wasn't written before. This can lead to an incorrect wait duration in intel_dp_wait_source_oui(), since jiffies is not inited to 0 in general (on a 32 bit system INITIAL_JIFFIES is set to 5 minutes ahead of wrap-around). Fix this by intializing the write timestamp in the above case as well. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3da06d25bc4ef..0b9981f7f1a68 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3414,8 +3414,11 @@ intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) drm_err(&i915->drm, "Failed to read source OUI\n"); - if (memcmp(oui, buf, sizeof(oui)) == 0) + if (memcmp(oui, buf, sizeof(oui)) == 0) { + /* Assume the OUI was written now. */ + intel_dp->last_oui_write = jiffies; return; + } } if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) From patchwork Wed Oct 16 13:24:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2A1ED1AD55 for ; Wed, 16 Oct 2024 13:24:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94FBF10E6F9; Wed, 16 Oct 2024 13:24:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lyOZnUFC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D11E10E097 for ; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729085040; x=1760621040; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=BRGNtVHTV2R/+8+MlP/agImM6gJf9uLJ1HXyPeLr1+c=; b=lyOZnUFCVTaWnLWpAaxxjLXaeCO1rTdPokeaMMaUJay36Vb22plhRhe/ XwABCje0VyDVKEKjLlm7GXiM0R3IKJIIilSgQOUzlFAimsF7hvJe5pUs/ K44VXNF8Y1yVbdqacGvqViyOHiSwzes+iyVwYOWmxokt+YnZaGydGcR95 46+Cex8q3ZdyuwQijiLAPkKc87UbzWI2kYm/gL/KHUORatB8Js/r4OjGo 5DuWgzLymrAISqUpV3oENNeRK09e/yMfy76bhr/x2S0fuRRpMYsJZwhAo t89sDXrKaioRcrzfg5w/xc+oPm+iSZAu4UxVD4ISqPuMxaWZLIYNCuZek w==; X-CSE-ConnectionGUID: 0E8+AqYfT5a1oyFP52+1PA== X-CSE-MsgGUID: WCigZjdqRi6NQtHl1rIR8g== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46005975" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005975" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:41 -0700 X-CSE-ConnectionGUID: 1VRDkCdFTmO62zMt3u7Hog== X-CSE-MsgGUID: ysrBUuJYTJyEDRqKRtzqRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384456" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:40 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 4/8] drm/i915/dp: Track source OUI validity explicitly Date: Wed, 16 Oct 2024 16:24:01 +0300 Message-ID: <20241016132405.2231744-5-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" While updating the source OUI on the sink the driver should avoid writing the OUI if it's already up-to-date to prevent the sink from resetting itself in response to the update. On eDP - the only output type where the OUI was updated so far - the driver ensured this by comparing the current source OUI DPCD register values with the expected Intel OUI value, skipping the update in case of a match. On some non-eDP sinks - at least on Synaptics branch devices - this method doesn't work, since the source OUI DPCD registers read back as all 0, even after updating the registers. Handle the above kind of sinks by tracking when the OUI was updated and so should be valid, regardless of what the DPCD registers contain. eDP sinks reset the written source OUI value when the panel power is disabled, invalidate the OUI state accordingly. This is required by a follow-up patch updating the source OUI for non-eDP sink types as well. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 1 + .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 31 ++++++++++++++----- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_pps.c | 6 +++- 6 files changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 440fb3002f286..596e926ef0894 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -1251,6 +1251,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder) intel_dp->DP = intel_de_read(display, intel_dp->output_reg); intel_dp->reset_link_params = true; + intel_dp_invalidate_source_oui(intel_dp); if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) vlv_pps_pipe_reset(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index fe1ded6707f90..465f245a53c48 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4392,6 +4392,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder) struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); intel_dp->reset_link_params = true; + intel_dp_invalidate_source_oui(intel_dp); intel_pps_encoder_reset(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f1..9b46427806c6d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1765,6 +1765,7 @@ struct intel_dp { /* When we last wrote the OUI for eDP */ unsigned long last_oui_write; + bool oui_valid; bool colorimetry_support; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0b9981f7f1a68..9ed4e5f8d798a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3400,33 +3400,51 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, } static void -intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) +intel_dp_init_source_oui(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + bool oui_valid; u8 oui[] = { 0x00, 0xaa, 0x01 }; u8 buf[3] = {}; + if (!intel_dp_is_edp(intel_dp)) + return; + + oui_valid = READ_ONCE(intel_dp->oui_valid); + /* * During driver init, we want to be careful and avoid changing the source OUI if it's * already set to what we want, so as to avoid clearing any state by accident */ - if (careful) { + if (!oui_valid) { if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) drm_err(&i915->drm, "Failed to read source OUI\n"); if (memcmp(oui, buf, sizeof(oui)) == 0) { /* Assume the OUI was written now. */ intel_dp->last_oui_write = jiffies; - return; + oui_valid = true; } } - if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) + if (oui_valid) + return; + + WRITE_ONCE(intel_dp->oui_valid, true); + + if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { drm_err(&i915->drm, "Failed to write source OUI\n"); + WRITE_ONCE(intel_dp->oui_valid, false); + } intel_dp->last_oui_write = jiffies; } +void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) +{ + WRITE_ONCE(intel_dp->oui_valid, false); +} + void intel_dp_wait_source_oui(struct intel_dp *intel_dp) { struct intel_connector *connector = intel_dp->attached_connector; @@ -3462,8 +3480,7 @@ void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) lspcon_resume(dp_to_dig_port(intel_dp)); /* Write the source OUI as early as possible */ - if (intel_dp_is_edp(intel_dp)) - intel_edp_init_source_oui(intel_dp, false); + intel_dp_init_source_oui(intel_dp); /* * When turning on, we need to retry for 1ms to give the sink @@ -4184,7 +4201,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector * If needed, program our source OUI so we can make various Intel-specific AUX services * available (such as HDR backlight controls) */ - intel_edp_init_source_oui(intel_dp, true); + intel_dp_init_source_oui(intel_dp); return true; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 4efb9605a50e0..48f10876be656 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -189,6 +189,7 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp); void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); void intel_dp_wait_source_oui(struct intel_dp *intel_dp); int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 64f1f7ea94993..3d1f9b17034d0 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -861,8 +861,10 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) intel_de_read(display, pp_stat_reg), intel_de_read(display, pp_ctrl_reg)); - if ((pp & PANEL_POWER_ON) == 0) + if ((pp & PANEL_POWER_ON) == 0) { intel_dp->pps.panel_power_off_time = ktime_get_boottime(); + intel_dp_invalidate_source_oui(intel_dp); + } intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port), @@ -1074,6 +1076,8 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp) wait_panel_off(intel_dp); intel_dp->pps.panel_power_off_time = ktime_get_boottime(); + intel_dp_invalidate_source_oui(intel_dp); + /* We got a reference when we enabled the VDD. */ intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port), From patchwork Wed Oct 16 13:24:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7364FD1AD59 for ; Wed, 16 Oct 2024 13:24:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9045E10E701; Wed, 16 Oct 2024 13:24:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="46005981" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005981" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:42 -0700 X-CSE-ConnectionGUID: mm+VG4dNTra8KISvyntXZA== X-CSE-MsgGUID: pmoN0IUYQPirdPvAW1VdZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384457" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:41 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 5/8] drm/i915/dp: Reuse intel_dp_detect_dsc_caps() for eDP Date: Wed, 16 Oct 2024 16:24:02 +0300 Message-ID: <20241016132405.2231744-6-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reuse intel_dp_detect_dsc_caps() which already checks for the source's DSC cap and retrieves the DPCD version from the DPRX caps. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 38 ++++++++++++------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9ed4e5f8d798a..e2c37680caa91 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4018,6 +4018,23 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector * intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); } +static void +intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ + if (!HAS_DSC(i915)) + return; + + if (intel_dp_is_edp(intel_dp)) + intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], + connector); + else + intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], + connector); +} + static void intel_edp_mso_mode_fixup(struct intel_connector *connector, struct drm_display_mode *mode) { @@ -4193,9 +4210,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector intel_dp_set_max_sink_lane_count(intel_dp); /* Read the eDP DSC DPCD registers */ - if (HAS_DSC(dev_priv)) - intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - connector); + intel_dp_detect_dsc_caps(intel_dp, connector); /* * If needed, program our source OUI so we can make various Intel-specific AUX services @@ -5583,23 +5598,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) false); } -static void -intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ - if (!HAS_DSC(i915)) - return; - - if (intel_dp_is_edp(intel_dp)) - intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - connector); - else - intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], - connector); -} - static void intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) { From patchwork Wed Oct 16 13:24:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EAD6D1AD58 for ; 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X-CSE-ConnectionGUID: wuhMOklxSdmLwBgSMOHREA== X-CSE-MsgGUID: BE6l7UYUSiuR3HyMPRjmtg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46005984" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005984" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:43 -0700 X-CSE-ConnectionGUID: EttzlE2MS4mOZCP16IgCUw== X-CSE-MsgGUID: 2Gu0bDItSM2l6wRmVB9Vig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384458" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:42 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 6/8] drm/i915/dp: Write the source OUI for eDP before detecting sink capabilities Date: Wed, 16 Oct 2024 16:24:03 +0300 Message-ID: <20241016132405.2231744-7-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The eDP sink's capabilities, like DSC, may depend on the source OUI written to the sink, so ensure the OUI is written before reading out the capabilities. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e2c37680caa91..520cc6f50a126 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4200,6 +4200,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; } + /* + * If needed, program our source OUI so we can make various Intel-specific AUX services + * available (such as HDR backlight controls) + */ + intel_dp_init_source_oui(intel_dp); + /* * This has to be called after intel_dp->edp_dpcd is filled, PSR checks * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] @@ -4212,12 +4218,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector /* Read the eDP DSC DPCD registers */ intel_dp_detect_dsc_caps(intel_dp, connector); - /* - * If needed, program our source OUI so we can make various Intel-specific AUX services - * available (such as HDR backlight controls) - */ - intel_dp_init_source_oui(intel_dp); - return true; } From patchwork Wed Oct 16 13:24:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D227D1AD57 for ; Wed, 16 Oct 2024 13:24:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 910A610E6F0; Wed, 16 Oct 2024 13:24:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O3YLrwSx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3E9D10E6F0 for ; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729085040; x=1760621040; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ADGIvmCcT2ZRJLMLd5SutqHlepxDVEmcizqxDze7JMU=; b=O3YLrwSx1XI5RLqHdOLqqEM0iYmBYUsJ1J2PqXtUOftrRJ2jd+1gceVn 0wM/DBpRbJ0tAA+MSdbCO2No+px3VWsFJEOzgBu6RZywgypYEsMZmo8Bh 101f1/HwYvlfvPEUhLPwrFP+Wt0RRun5BVnRGYpTeBXtu4Fdns2emsFG9 2mYraLdGsB3nhHR6sA/AnOkyZAuSM29hAmFjtWjxOTBz/s+EAoMUfZIfN QYyKsltt8Af0aXUXlTzkIkoGp4O0oun4mER3jg5oFJRK/uZYTwZGxIywX stdmrWoDjiWqx8tHRdX4GsaRUQcVCOWp1FEdBwLpii8nNzq07NCjH4x5L Q==; X-CSE-ConnectionGUID: MMLfiTcyRwmM4zsRkzR0rw== X-CSE-MsgGUID: nZ6YTjkaToihOZ5MjmOAhA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46005985" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005985" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:44 -0700 X-CSE-ConnectionGUID: HXbQpv5sTmiS6NYl0uYMKg== X-CSE-MsgGUID: tEvNNTqmQlm1LMgprTf70A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384459" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:43 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 7/8] drm/i915/dp: Write the source OUI during connector detection Date: Wed, 16 Oct 2024 16:24:04 +0300 Message-ID: <20241016132405.2231744-8-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The DP sink's capabilities, like DSC, may depend on the source OUI written to the sink. On eDP this OUI value could have been reset before the detection started if the panel power on it got disabled. Make sure the OUI is re-written at the beginning of detection in this case, before the sink capabilities are read out. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 520cc6f50a126..063fe92d43786 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5669,6 +5669,8 @@ intel_dp_detect(struct drm_connector *connector, goto out_unset_edid; } + intel_dp_init_source_oui(intel_dp); + ret = intel_dp_tunnel_detect(intel_dp, ctx); if (ret == -EDEADLK) { status = ret; From patchwork Wed Oct 16 13:24:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13838480 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C856D1AD5A for ; Wed, 16 Oct 2024 13:24:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B61A110E702; Wed, 16 Oct 2024 13:24:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ww4CjGlx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F6AB10E6F0 for ; Wed, 16 Oct 2024 13:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729085040; x=1760621040; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=AulHWYoA1CFkAi67AfvEQ9WQYMuMQQ/4W1lU3EEs7ho=; b=Ww4CjGlxXF6++nlNM/sRM6zvgFsXr3V+JT12I2ILrhKROMkpL8DySKRr xwCd9p+g4BWthBVq8P0d81S2qVOmXofjfD9XI2LBjMItSTEe4gjY7Acjb PxZyv23NkHDgFq6WwvIxQbKsv89OxVl3GLzHeCfkPpgSs0dfzadV4AmqT fGtzHokzzDThTSa1BkTxI8VNvQ/zDJzCGNpD1UyHUuTudrpztDCZeUkfl 0kzFz3It+bFFM64dA8DLtahab5bu7+Wv/JJ5Xmd2YyXofX61q3C8OI0kX MeQ9IVAyrA2vOKeiVB8hZOdiku1FnX+Ddn1J28ucWZ1OHNyj5urVAkzKg Q==; X-CSE-ConnectionGUID: dH7A24z/QLmOg7LFbOt5Og== X-CSE-MsgGUID: 7HeWSyXfTlGd/CgsI14zxw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46005987" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46005987" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:45 -0700 X-CSE-ConnectionGUID: 3dSm1LrWRS2b7uMWkEJq+w== X-CSE-MsgGUID: iglNq0rJS2a/ZYoG4/whSw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,208,1725346800"; d="scan'208";a="78384460" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 06:23:44 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 8/8] drm/i915/dp: Write the source OUI for non-eDP sinks as well Date: Wed, 16 Oct 2024 16:24:05 +0300 Message-ID: <20241016132405.2231744-9-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241016132405.2231744-1-imre.deak@intel.com> References: <20241016132405.2231744-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" At least the i-tec USB-C Nano 2x Display Docking Station (containing a Synaptics MST branch device) requires the driver to update the source OUI DPCD registers to expose its DSC capability. Accordingly update the OUI for all sink types (besides eDP where this has been done already). Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11776 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 063fe92d43786..456c87a65ad8d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3407,9 +3407,6 @@ intel_dp_init_source_oui(struct intel_dp *intel_dp) u8 oui[] = { 0x00, 0xaa, 0x01 }; u8 buf[3] = {}; - if (!intel_dp_is_edp(intel_dp)) - return; - oui_valid = READ_ONCE(intel_dp->oui_valid); /* @@ -6138,6 +6135,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) if (long_hpd) { intel_dp->reset_link_params = true; + intel_dp_invalidate_source_oui(intel_dp); + return IRQ_NONE; }