From patchwork Thu Oct 17 09:28:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13839681 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 101BF1D90D9; Thu, 17 Oct 2024 09:28:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729157336; cv=none; b=groGnOpoy9bBbeYHDa6EC6mkFGt7IZYS3jjmFl+KOIkwx8FwNhysjHlk8OFwKkIHZ4Z9M3htff0Be/8qiuaxePgNmXML+Wybwmsb4tbw7av+jlCI8/53t+ua5nIEtUrRWjw/3lk03Tt/FlTiM5xOB4kS3QWfUspAWHX+Wayiv8E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729157336; c=relaxed/simple; bh=83cH9HJgjYFVsjIC3u9qtw9cDZHkMSXGwxmMITfT6Hg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=BWAjxyjFuwZR/N+xCkbHcrftLPPTpDG635/WJPoTPLbPzDJTcw2jb1ZYDYolKzZPpE8GXmwtYAJ/b5ZhS+knZmSFlCafXfg354ywP9/uvJeVQSQhZJqZEjNFs2NwZ9zomUYRQbDHbIAgCeDl8fOGT0eLub2bZcnh5kyCjDU7694= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Hdaw8qPD; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Hdaw8qPD" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49H7kldv007441; Thu, 17 Oct 2024 09:28:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= JE5+ih9zaWyyFOnZT7dIsaFRI1fg7+sYKmqRnQBgvNY=; b=Hdaw8qPDIi1L/RXW DX1ocAqZNUcvfh278s/scPkiPPnJKDqGIgaPWovwavQh1eS+UDPp8jCSwFLk+QPg w5U2sVTypKKTlBQHGAVWQJjWfZ6oq9QdyVr4uJv8JZxNsM6lXXef+LT+bKCuPdZK rjeJFZbNsQiasftJrd5dTzsPuCHYWNHWjZyKqN1l1fefDmcrMSAaAvNXzXo9dYFY vs31pKdhxRYg9f3DmlVGnbmuut63iVGmgwxKDUplaoM1prm4m7Y5HB53WlBjFyKD e/3yi7T3kyKTqSu3rs+6izpP/3JZj0UCaPY7ahcw5v0B4RiWR1mNVLG0x8o1kBOE g6bm8g== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 429mjy7mtq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 09:28:48 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49H9SlTt006560 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 09:28:47 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 02:28:43 -0700 From: Jagadeesh Kona Date: Thu, 17 Oct 2024 14:58:30 +0530 Subject: [PATCH 1/3] arm64: dts: qcom: sa8775p: Add support to scale DDR/L3 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-1-074e0fb80b33@quicinc.com> References: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> In-Reply-To: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Ajit Pandey , "Imran Shaik" , Taniya Das , "Satya Priya Kakitapalli" , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5dl_MOTuKDSef_8MzPAr_XIlZ91Zhtbw X-Proofpoint-ORIG-GUID: 5dl_MOTuKDSef_8MzPAr_XIlZ91Zhtbw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=818 phishscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 clxscore=1015 spamscore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170063 Add support to scale DDR and L3 based on CPU frequencies on SA8775P platform. Signed-off-by: Jagadeesh Kona --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 06bf2ba556b89b643da901857a9aa7cdc7ba90cc..d8b90bd4b1f05604185f015929a1f296799ad6a4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -47,6 +48,10 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -69,6 +74,10 @@ CPU1: cpu@100 { next-level-cache = <&L2_1>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -86,6 +95,10 @@ CPU2: cpu@200 { next-level-cache = <&L2_2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -103,6 +116,10 @@ CPU3: cpu@300 { next-level-cache = <&L2_3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -120,6 +137,10 @@ CPU4: cpu@10000 { next-level-cache = <&L2_4>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -143,6 +164,10 @@ CPU5: cpu@10100 { next-level-cache = <&L2_5>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -160,6 +185,10 @@ CPU6: cpu@10200 { next-level-cache = <&L2_6>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -177,6 +206,10 @@ CPU7: cpu@10300 { next-level-cache = <&L2_7>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_7: l2-cache { compatible = "cache"; cache-level = <2>; From patchwork Thu Oct 17 09:28:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13839682 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 530B71D90C5; Thu, 17 Oct 2024 09:28:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729157340; cv=none; b=VXJhva0/QHBAg8dRtVqrCYlt5H8FshQZd87v1IrvrZYXG4XjCgFuRHG2ASju/0G5AIbXo3ZAaaFjxhS9zBOetJTdMMMDyDhMeyCSg5Qet3pG9HQdi4QSMo1qaaH7gBYoPpcA8NOo/WqBq4sbXSfuK6iYsZ2uQRmb3SIWXmwqf6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729157340; c=relaxed/simple; bh=YVgiHPmTyzr7jdnMo8hfs8zskkamJ/8KlInnP+l4F8Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=oyPCnuS3OZiW3BpMT2KFFf2cUg7TW2mIBW8fpKVd3NaWfCqEazdgwSnmvxXzCDimLhGTC77PC2/LUQ+nShKojPF0HdHnYGnmyFs6Zw5MLgb+gpxz2PvSw/nTb3uuMlmbn9csKVjsmaiu7/5+3ghAv0PY+5VYRAaqX7fnO+9TfDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Q/kiugW3; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Q/kiugW3" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49H9IwnO011201; Thu, 17 Oct 2024 09:28:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lSB7EgkVjziLJvsXs8lcRCTOX946FL/93S5iwZwvDdU=; b=Q/kiugW3N2SpCULo 6iaY8rZ35LPjoJRbQdK6WtCQXG9DwQWNqKtjJ+8oWGaIs2Y0TnWk08y0K9k80+D1 dfb2PCgUuiX46lf+b9h8PLov/V5hpwWV1F1U8Ox39frjonbzmYoPLqQ9dJ5D3MjC HVEH55mk2++K0K9kXR2M/34NGCAUYXP4gaGw1o6V7RxcbknXnovaXhbOgOFyYfFj RXkxiMUjh5BXndBLstxOQjqw6BOBeWMvfc0s95rKhRxz2+NkUSCkbf4gPoFKbQhJ kr0tASXT704fOdd7TArDVaO1kANmp5g6yIBnsHMFOGllT5Gcyya4DU9uBN2Q0t3C ftIDBA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42abm5kgb0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 09:28:52 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49H9Spqr010687 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 09:28:51 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 02:28:47 -0700 From: Jagadeesh Kona Date: Thu, 17 Oct 2024 14:58:31 +0530 Subject: [PATCH 2/3] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-2-074e0fb80b33@quicinc.com> References: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> In-Reply-To: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Ajit Pandey , "Imran Shaik" , Taniya Das , "Satya Priya Kakitapalli" , Jagadeesh Kona , Shivnandan Kumar X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Yjmx31Bx9KRA0xG8vU9YgO9LtN6Qxy97 X-Proofpoint-GUID: Yjmx31Bx9KRA0xG8vU9YgO9LtN6Qxy97 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 spamscore=0 mlxlogscore=901 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170063 From: Shivnandan Kumar Add OPP tables required to scale DDR and L3 per freq-domain on SA8775P platform. Signed-off-by: Shivnandan Kumar Signed-off-by: Jagadeesh Kona --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 178 ++++++++++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index d8b90bd4b1f05604185f015929a1f296799ad6a4..47eca50b30ffa38a652706014d35ef9e833003ec 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -48,6 +48,7 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS @@ -74,6 +75,7 @@ CPU1: cpu@100 { next-level-cache = <&L2_1>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS @@ -95,6 +97,7 @@ CPU2: cpu@200 { next-level-cache = <&L2_2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS @@ -116,6 +119,7 @@ CPU3: cpu@300 { next-level-cache = <&L2_3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl0 MASTER_EPSS_L3_APPS @@ -137,6 +141,7 @@ CPU4: cpu@10000 { next-level-cache = <&L2_4>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS @@ -164,6 +169,7 @@ CPU5: cpu@10100 { next-level-cache = <&L2_5>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS @@ -185,6 +191,7 @@ CPU6: cpu@10200 { next-level-cache = <&L2_6>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS @@ -206,6 +213,7 @@ CPU7: cpu@10300 { next-level-cache = <&L2_7>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3_cl1 MASTER_EPSS_L3_APPS @@ -299,6 +307,176 @@ CLUSTER_SLEEP_APSS_RSC_PC: cluster-sleep-1 { }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_1267mhz: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1363mhz: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1459mhz: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1536mhz: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu0_opp_1632mhz: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1708mhz: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1785mhz: opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_1939mhz: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu0_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2188mhz: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2265mhz: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu0_opp_2361mhz: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu0_opp_2457mhz: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu0_opp_2553mhz: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <12787200 54681600>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp_1267mhz: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1363mhz: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1459mhz: opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1536mhz: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <6220800 29491200>; + }; + + cpu4_opp_1632mhz: opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1708mhz: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1785mhz: opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_1939mhz: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6835200 39321600>; + }; + + cpu4_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2188mhz: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2265mhz: opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <8371200 49766400>; + }; + + cpu4_opp_2361mhz: opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu4_opp_2457mhz: opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <12787200 51609600>; + }; + + cpu4_opp_2553mhz: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <12787200 54681600>; + }; + }; + dummy-sink { compatible = "arm,coresight-dummy-sink"; From patchwork Thu Oct 17 09:28:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13839683 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E49441D967B; Thu, 17 Oct 2024 09:29:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729157343; cv=none; b=kUwUE9aEpmarP+JyaRLl1U81zz82ECvkI++RdVWTromk0jghTQdjg5tJLGJ9Gu6Nj4dHJY8d0KNmoU+n7Ib51w0+SAprr8MZniRQ8KaY5TM6NR91uzCwBA/jkBmyYDXGVnHs5CGkGl/9CRsm492+EnmGoytZUX+yg1xfinEBh7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729157343; c=relaxed/simple; bh=LZ7arE2zENVRpiRV4fUDmnOpMnAZxOmOWTuuKFtwakw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Vqv5VI1Cw14gkgZtHRMsjQDj/KGSBCi3NgswjxVLl384503UWQl7A22/bJg87pEaNLuqCqdDaUcNQ5rZjzsiThD8jgo1lm2/zFAR8pabAVKWD+aD7lZpl7Yp6iW8yZyYUPRyKqIz0GV44bNuPbUfa0sHByv5ij7G9WCczxHWKZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NiT7yLqb; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NiT7yLqb" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49H8wEUZ011689; Thu, 17 Oct 2024 09:28:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= c4l8Iwd5n46ZVZkT7ENdNpERZrgT96FsQzKEmQh2Gfw=; b=NiT7yLqbO5J3bQRG 05o0S5GQ5euvTrCtSiiTkMjmpgF4JN7WdNWRqa4vuXKW92Gt+h7u+331+x1YFaCW HrwI5tKB826xgQv7WXKl7U65lfrV2bBstajWr8PQHZn3jpDVQNR6Xy2Bvb9vJcRt AOGNCVTd1Vs8bpzW9l0GlK8bYTmF5ZsoN6rvgfQ1PICrhLfXhmmi9ZnfHWhM92+5 vatRE2nuPAgl1BTjZFii5Apj/OOdmvOuDF8K/tLqsE3fSDazuTH4OF/NTGIu6UoP LNw9I6zeEoasSFpu5+49LsC/WG9tsI7YX7F57CFROVUVru+XvVhu+c8pDaDfuD/m vBfZFQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42abm5kgbd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 09:28:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49H9StpA015714 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 09:28:55 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 02:28:51 -0700 From: Jagadeesh Kona Date: Thu, 17 Oct 2024 14:58:32 +0530 Subject: [PATCH 3/3] arm64: dts: qcom: sa8775p: Add LMH interrupts support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-3-074e0fb80b33@quicinc.com> References: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> In-Reply-To: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Ajit Pandey , "Imran Shaik" , Taniya Das , "Satya Priya Kakitapalli" , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AjdT6Kx3PwsMfTVspd5zFxaj_J4uv3rr X-Proofpoint-GUID: AjdT6Kx3PwsMfTVspd5zFxaj_J4uv3rr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=2 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 spamscore=0 mlxlogscore=554 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170063 Add LMH interrupts support to indicate if there is any thermal throttle. Signed-off-by: Jagadeesh Kona --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 47eca50b30ffa38a652706014d35ef9e833003ec..bd86bc2cb6c304aa0b4000f3226639bef57a9b9a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4005,6 +4005,10 @@ cpufreq_hw: cpufreq@18591000 { <0x0 0x18593000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate";