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a=openpgp-sha256; l=6303; i=yasin.lee.x@gmail.com; h=from:subject:message-id; bh=N2euFngJxSATLtEd1gk9xVj5LrqAKqRPTsHiiP8bK4s=; b=owGbwMvMwCEYyfeRr6Zs90zG02pJDOkCL1kPbHLOEljXWZrw/9uG5mKZDfFtWmvX3m88s/Nr0 4nZ8lWnOkpZGAQ5GGTFFFnOvH7Dmq/6cE/wb9cMmDmsTCBDGLg4BWAicgUM/2NU5on13z1wIWCr u2/6v6T8gA1bTocLe8Yf7baU23ZYJ4aRYfO2ObmfUvQ/GrKkNHV3xer+zPxV+f59apWQmv3F2Yf lNwMA X-Developer-Key: i=yasin.lee.x@gmail.com; a=openpgp; fpr=CCEBEC056F25E1BC53FB4568590EF10E7C76BB99 When hardware design introduces significant sensor data noise, performance can be improved by adjusting register settings. Signed-off-by: Yasin Lee --- .../bindings/iio/proximity/tyhx,hx9023s.yaml | 195 +++++++++++++++++++++ 1 file changed, 195 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml b/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml index 64ce8bc8bd36..af419a3335eb 100644 --- a/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml @@ -28,6 +28,189 @@ properties: vdd-supply: true + tyhx,dither: + description: Enable spread spectrum function. + type: boolean + + tyhx,chop: + description: Enable chop function. + type: boolean + + tyhx,odr: + description: | + Defines the sensor scanning period. The values range from 0x00 to 0x1F, + corresponding to the following periods. + Val: Period + 0x00: Min (no idle time) + 0x01: 2 ms + 0x02: 4 ms + 0x03: 6 ms + 0x04: 8 ms + 0x05: 10 ms + 0x06: 14 ms + 0x07: 18 ms + 0x08: 22 ms + 0x09: 26 ms + 0x0A: 30 ms + 0x0B: 34 ms + 0x0C: 38 ms + 0x0D: 42 ms + 0x0E: 46 ms + 0x0F: 50 ms + 0x10: 56 ms + 0x11: 62 ms + 0x12: 68 ms + 0x13: 74 ms + 0x14: 80 ms + 0x15: 90 ms + 0x16: 100 ms + 0x17: 200 ms + 0x18: 300 ms + 0x19: 400 ms + 0x1A: 600 ms + 0x1B: 800 ms + 0x1C: 1000 ms + 0x1D: 2000 ms + 0x1E: 3000 ms + 0x1F: 4000 ms + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x00 + maximum: 0x1F + + tyhx,range: + description: | + Defines the full-scale range for each channel. + The values correspond to the following full-scale ranges. + Val: Full Scale + 0x0: 1.25pF + 0x1: 2.5pF + 0x2: 3.75pF + 0x3: 5pF + 0x4: 0.625pF + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + + tyhx,avg: + description: | + Defines the ADC averaging value for each channel. + The values correspond to the following averages. + Val: Avg Number + 0x0: 1 + 0x1: 2 + 0x2: 4 + 0x3: 8 + 0x4: 16 + 0x5: 32 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + + tyhx,osr: + description: | + Defines the ADC oversampling rate (OSR) for each channel. + The values correspond to the following OSR. + Val: OSR + 0x0: 16 + 0x1: 32 + 0x2: 64 + 0x3: 128 + 0x4: 256 + 0x5: 512 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + + tyhx,sample-num: + description: | + Defines the ADC sample frequency. + The sample frequency can be calculated with the following formula: + Fsample = 1.0 / ( sample_num * 200ns ), + where `sample_num` is the value in the register in decimal. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x00 + maximum: 0xFF + + tyhx,integration-num: + description: The integration number should be the same as the `sample-num` above. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x00 + maximum: 0xFF + + tyhx,lp-alpha: + description: | + Defines the coefficient for the first-order low pass filter for each channel. + The values correspond to the following coefficients. + Val: Coefficient + 0x0: 1 + 0x1: 1/2 + 0x2: 1/4 + 0x3: 1/8 + 0x4: 1/16 + 0x5: 1/32 + 0x6: 1/64 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + + tyhx,bl-up-alpha: + description: | + Defines the up coefficient of the first-order low pass filter for each channel. + The values correspond to the following coefficients. + Val: Coefficient + 0x0: 0 + 0x1: 1 + 0x2: 1/2 + 0x3: 1/4 + 0x4: 1/8 + 0x5: 1/16 + 0x6: 1/32 + 0x7: 1/64 + 0x8: 1/128 + 0x9: 1/256 + 0xA: 1/512 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + + tyhx,bl-down-alpha: + description: | + Defines the down coefficient of the first-order low pass filter for each channel. + The values correspond to the following coefficients. + Val: Coefficient + 0x0: 0 + 0x1: 1 + 0x2: 1/2 + 0x3: 1/4 + 0x4: 1/8 + 0x5: 1/16 + 0x6: 1/32 + 0x7: 1/64 + 0x8: 1/128 + 0x9: 1/256 + 0xA: 1/512 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + + tyhx,drdy-interrupt: + description: Enable the interrupt function of each channel when the conversion is ready. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x00 + maximum: 0x1F + + tyhx,int-high-num: + description: Defines the Proximity persistency number (Near). + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x1 + maximum: 0xF + + tyhx,int-low-num: + description: Defines the Proximity persistency number (Far). + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x1 + maximum: 0xF + "#address-cells": const: 1 @@ -65,6 +248,18 @@ examples: interrupt-parent = <&pio>; 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Thu, 17 Oct 2024 03:38:12 -0700 (PDT) Received: from [127.0.1.1] ([45.32.86.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d17f9d51esm41899025ad.104.2024.10.17.03.38.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2024 03:38:11 -0700 (PDT) From: Yasin Lee Date: Thu, 17 Oct 2024 18:36:45 +0800 Subject: [PATCH v3 2/2] iio: proximity: hx9023s: Add performance tuning function Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241017-add-performance-tuning-configuration-v3-2-e7289791f523@gmail.com> References: <20241017-add-performance-tuning-configuration-v3-0-e7289791f523@gmail.com> In-Reply-To: <20241017-add-performance-tuning-configuration-v3-0-e7289791f523@gmail.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , yasin.lee.x@outlook.com Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yasin Lee X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10193; i=yasin.lee.x@gmail.com; h=from:subject:message-id; bh=E+GnRkyTSIOyO92KPoBLDhVtU+ZCAKCKHoc2KE53rpQ=; b=owGbwMvMwCEYyfeRr6Zs90zG02pJDOkCL1knJOSycp4ut4hd2T1dqn1xwZSwc4yMftYCuik/c vVzpyV2lLIwCHIwyIopspx5/YY1X/XhnuDfrhkwc1iZQIYwcHEKwEQu/mdk2BG6N231uryEzlnX gv/MEsxZWfTnxeewqJtnt/BaeNusfMvIMFv4MEfNfuNJCx60XXle1GjmwiUWsfm/Uunh20UXiy4 s1wUA X-Developer-Key: i=yasin.lee.x@gmail.com; a=openpgp; fpr=CCEBEC056F25E1BC53FB4568590EF10E7C76BB99 When hardware design introduces significant sensor data noise, performance can be improved by adjusting register settings. Signed-off-by: Yasin Lee --- drivers/iio/proximity/hx9023s.c | 234 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/drivers/iio/proximity/hx9023s.c b/drivers/iio/proximity/hx9023s.c index 8b9f84400e00..5d0338588616 100644 --- a/drivers/iio/proximity/hx9023s.c +++ b/drivers/iio/proximity/hx9023s.c @@ -61,6 +61,7 @@ #define HX9023S_OFFSET_DAC4_9_8 0x1E #define HX9023S_SAMPLE_NUM_7_0 0x1F #define HX9023S_INTEGRATION_NUM_7_0 0x21 +#define HX9023S_GLOBAL_CTRL2 0x23 #define HX9023S_CH_NUM_CFG 0x24 #define HX9023S_LP_ALP_4_CFG 0x29 #define HX9023S_LP_ALP_1_0_CFG 0x2A @@ -623,6 +624,235 @@ static int hx9023s_property_get(struct hx9023s_data *data) return 0; } +static int hx9023s_performance_tuning(struct hx9023s_data *data) +{ + struct device *dev = regmap_get_device(data->regmap); + int ret; + bool dither; + bool chop; + u32 odr; + u32 range[HX9023S_CH_NUM]; + u32 avg[HX9023S_CH_NUM]; + u32 osr[HX9023S_CH_NUM]; + u32 sample_time; + u32 integration_time; + u32 lp_alpha[HX9023S_CH_NUM]; + u32 bl_up_alpha[HX9023S_CH_NUM]; + u32 bl_down_alpha[HX9023S_CH_NUM]; + u32 drdy_interrput; + u32 int_high_num; + u32 int_low_num; + u32 temp; + + /* dither */ + dither = device_property_read_bool(dev, "tyhx,dither"); + if (dither) + ret = regmap_update_bits(data->regmap, HX9023S_GLOBAL_CTRL0, BIT(6), BIT(6)); + else + ret = regmap_update_bits(data->regmap, HX9023S_GLOBAL_CTRL0, BIT(6), 0); + + /* chop */ + chop = device_property_read_bool(dev, "tyhx,chop"); + if (chop) + ret = regmap_update_bits(data->regmap, HX9023S_GLOBAL_CTRL2, GENMASK(4, 0), + GENMASK(4, 0)); + else + ret = regmap_update_bits(data->regmap, HX9023S_GLOBAL_CTRL2, GENMASK(4, 0), 0); + + /* odr */ + ret = device_property_read_u32(dev, "tyhx,odr", &odr); + if (!ret) { + ret = regmap_update_bits(data->regmap, HX9023S_PRF_CFG, GENMASK(4, 0), + FIELD_PREP(GENMASK(4, 0), odr)); + if (ret) + return dev_err_probe(dev, ret, "Failed to update odr\n"); + } + + /* range */ + ret = device_property_read_u32_array(dev, "tyhx,range", range, ARRAY_SIZE(range)); + if (!ret) { + temp = FIELD_PREP(GENMASK(2, 0), range[0]) | FIELD_PREP(GENMASK(6, 4), range[1]); + ret = regmap_update_bits(data->regmap, HX9023S_RANGE_7_0, GENMASK(6, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update range for ch0 and ch1\n"); + + temp = FIELD_PREP(GENMASK(2, 0), range[2]) | FIELD_PREP(GENMASK(6, 4), range[3]); + ret = regmap_update_bits(data->regmap, HX9023S_RANGE_9_8, GENMASK(6, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update range for ch2 and ch3\n"); + + temp = FIELD_PREP(GENMASK(2, 0), range[4]); + ret = regmap_update_bits(data->regmap, HX9023S_RANGE_18_16, GENMASK(2, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update range for ch4\n"); + } + + /* avg */ + ret = device_property_read_u32_array(dev, "tyhx,avg", avg, ARRAY_SIZE(avg)); + if (!ret) { + temp = FIELD_PREP(GENMASK(7, 5), avg[0]); + ret = regmap_update_bits(data->regmap, HX9023S_AVG0_NOSR0_CFG, GENMASK(7, 5), + temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update avg for ch0\n"); + + temp = FIELD_PREP(GENMASK(6, 4), avg[2]) | FIELD_PREP(GENMASK(2, 0), avg[1]); + ret = regmap_update_bits(data->regmap, HX9023S_AVG12_CFG, GENMASK(6, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update avg for ch1 and ch2\n"); + + temp = FIELD_PREP(GENMASK(6, 4), avg[4]) | FIELD_PREP(GENMASK(2, 0), avg[3]); + ret = regmap_update_bits(data->regmap, HX9023S_AVG34_CFG, GENMASK(6, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update avg for ch3 and ch4\n"); + } + + /* osr */ + ret = device_property_read_u32_array(dev, "tyhx,osr", osr, ARRAY_SIZE(osr)); + if (!ret) { + temp = FIELD_PREP(GENMASK(4, 2), osr[0]); + ret = regmap_update_bits(data->regmap, HX9023S_AVG0_NOSR0_CFG, GENMASK(4, 2), + temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update osr for ch0\n"); + + temp = FIELD_PREP(GENMASK(6, 4), osr[2]) | FIELD_PREP(GENMASK(2, 0), osr[1]); + ret = regmap_update_bits(data->regmap, HX9023S_NOSR12_CFG, GENMASK(6, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update osr for ch1 and ch2\n"); + + temp = FIELD_PREP(GENMASK(6, 4), osr[4]) | FIELD_PREP(GENMASK(2, 0), osr[3]); + ret = regmap_update_bits(data->regmap, HX9023S_NOSR34_CFG, GENMASK(6, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update osr for ch3 and ch4\n"); + } + + /* sample time */ + ret = device_property_read_u32(dev, "tyhx,sample-time", &sample_time); + if (!ret) { + ret = regmap_write(data->regmap, HX9023S_SAMPLE_NUM_7_0, sample_time); + if (ret) + return dev_err_probe(dev, ret, "Failed to update sample_time\n"); + } + + /* integration time */ + ret = device_property_read_u32(dev, "tyhx,integration-time", &integration_time); + if (!ret) { + ret = regmap_write(data->regmap, HX9023S_INTEGRATION_NUM_7_0, integration_time); + if (ret) + return dev_err_probe(dev, ret, "Failed to update integration_time\n"); + } + + /* lp-alpha */ + ret = device_property_read_u32_array(dev, "tyhx,lp-alpha", lp_alpha, ARRAY_SIZE(lp_alpha)); + if (!ret) { + temp = FIELD_PREP(GENMASK(6, 4), lp_alpha[1]) + | FIELD_PREP(GENMASK(2, 0), lp_alpha[0]); + ret = regmap_write(data->regmap, HX9023S_LP_ALP_1_0_CFG, temp); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update lp-alpha for ch0 and ch1\n"); + + temp = FIELD_PREP(GENMASK(6, 4), lp_alpha[3]) + | FIELD_PREP(GENMASK(2, 0), lp_alpha[2]); + ret = regmap_write(data->regmap, HX9023S_LP_ALP_3_2_CFG, temp); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update lp-alpha for ch2 and ch3\n"); + + temp = FIELD_PREP(GENMASK(2, 0), lp_alpha[4]); + ret = regmap_update_bits(data->regmap, HX9023S_LP_ALP_4_CFG, GENMASK(2, 0), temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update lp-alpha for ch4\n"); + } + + /* bl-up-alpha */ + ret = device_property_read_u32_array(dev, "tyhx,bl-up-alpha", + bl_up_alpha, ARRAY_SIZE(bl_up_alpha)); + if (!ret) { + temp = FIELD_PREP(GENMASK(7, 4), bl_up_alpha[1]) + | FIELD_PREP(GENMASK(3, 0), bl_up_alpha[0]); + ret = regmap_write(data->regmap, HX9023S_UP_ALP_1_0_CFG, temp); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update bl-up-alpha for ch0 and ch1\n"); + + temp = FIELD_PREP(GENMASK(7, 4), bl_up_alpha[3]) + | FIELD_PREP(GENMASK(3, 0), bl_up_alpha[2]); + ret = regmap_write(data->regmap, HX9023S_UP_ALP_3_2_CFG, temp); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update bl-up-alpha for ch2 and ch3\n"); + + temp = FIELD_PREP(GENMASK(3, 0), bl_up_alpha[4]); + ret = regmap_update_bits(data->regmap, HX9023S_DN_UP_ALP_0_4_CFG, GENMASK(3, 0), + temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update bl-up-alpha for ch4\n"); + } + + /* bl-down-alpha */ + ret = device_property_read_u32_array(dev, "tyhx,bl-down-alpha", + bl_down_alpha, ARRAY_SIZE(bl_down_alpha)); + if (!ret) { + temp = FIELD_PREP(GENMASK(7, 4), bl_down_alpha[0]); + ret = regmap_update_bits(data->regmap, HX9023S_DN_UP_ALP_0_4_CFG, GENMASK(7, 4), + temp); + if (ret) + return dev_err_probe(dev, ret, "Failed to update bl-dn-alpha for ch0\n"); + + temp = FIELD_PREP(GENMASK(7, 4), bl_down_alpha[2]) + | FIELD_PREP(GENMASK(3, 0), bl_down_alpha[1]); + ret = regmap_write(data->regmap, HX9023S_DN_ALP_2_1_CFG, temp); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update bl-dn-alpha for ch1 and ch2\n"); + + temp = FIELD_PREP(GENMASK(7, 4), bl_down_alpha[4]) + | FIELD_PREP(GENMASK(3, 0), bl_down_alpha[3]); + ret = regmap_write(data->regmap, HX9023S_DN_ALP_4_3_CFG, temp); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update bl-dn-alpha for ch3 and ch4\n"); + } + + /* dydy-interrupt */ + ret = device_property_read_u32(dev, "tyhx,drdy-interrupt", &drdy_interrput); + if (!ret) { + ret = regmap_update_bits(data->regmap, HX9023S_CALI_DIFF_CFG, GENMASK(7, 4), + FIELD_PREP(GENMASK(7, 4), drdy_interrput)); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update drdy-interrput for ch0~ch3\n"); + + ret = regmap_update_bits(data->regmap, HX9023S_DITHER_CFG, BIT(7), + FIELD_PREP(BIT(7), drdy_interrput >> 4)); + if (ret) + return dev_err_probe(dev, ret, + "Failed to update drdy-interrput for ch4\n"); + } + + /* int-high-num */ + ret = device_property_read_u32(dev, "tyhx,int-high-num", &int_high_num); + if (!ret) { + ret = regmap_update_bits(data->regmap, HX9023S_PROX_INT_HIGH_CFG, GENMASK(3, 0), + FIELD_PREP(GENMASK(3, 0), int_high_num)); + if (ret) + return dev_err_probe(dev, ret, "Failed to update int-high-num\n"); + } + + /* int-low-num */ + ret = device_property_read_u32(dev, "tyhx,int-low-num", &int_low_num); + if (!ret) { + ret = regmap_update_bits(data->regmap, HX9023S_PROX_INT_LOW_CFG, GENMASK(3, 0), + FIELD_PREP(GENMASK(3, 0), int_low_num)); + if (ret) + return dev_err_probe(dev, ret, "Failed to update int-low-num\n"); + } + + return 0; +} + static int hx9023s_update_chan_en(struct hx9023s_data *data, unsigned long chan_read, unsigned long chan_event) @@ -1045,6 +1275,10 @@ static int hx9023s_probe(struct i2c_client *client) if (ret) return dev_err_probe(dev, ret, "channel config failed\n"); + ret = hx9023s_performance_tuning(data); + if (ret) + return dev_err_probe(dev, ret, "performance tuning failed\n"); + ret = regcache_sync(data->regmap); if (ret) return dev_err_probe(dev, ret, "regcache sync failed\n");