From patchwork Thu Oct 17 11:40:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uttkarsh Aggarwal X-Patchwork-Id: 13839909 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADF5B1DD523; Thu, 17 Oct 2024 11:41:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729165288; cv=none; b=HraZ/h8A7z9SLjMTeYqryt0/gFZdER6c6JvPu45Wvil6eJT8Nn01EaH8knrvfYY4jpHK54SkvO9Vh8a61fZtweMg6I5JAPAVV+UlDUMynMm22q2/HBsTX9ycUduKuQl9VtbLqngtcjfr0EAq13XAqt4uTP/TfrNF5/zjZu7JiFw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729165288; c=relaxed/simple; bh=gTB/I1yIrmxfrwS4Lmr9UCzhBZN1hbqmQdeYRMvAFOk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lWupIVjFwyBuV8jpM6PlUWx/KMapjgjpGsIkmvIgdeBLdbLyL40OgXTYEXqkOBnanDu9c0wz3fmcxjQ++eNDHw5wPVNUqGWv/u9l3DYRNXK2k+l2tXP2d8MtU977k9TRdLFjuatXB0AvLgJzCj634IJmGwnhiXZx93uDlS6kvxk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=SI6hFtvn; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="SI6hFtvn" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49H8vt7s011199; Thu, 17 Oct 2024 11:41:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=KKTgqoSqQSfHGYkfrHbSB/+T 55XsMPAz2RMALrOtQy8=; b=SI6hFtvnTHJmZrW+bKoEu6v/a9yw+ovYAT/ycDo0 EAj3dQSyjpfEq+W7WmxQ6LVzn4vUwA0PNooPX0u0GoaDk7o9tl68PCM8PCSosqZO NyXQu3XaoK2bdcv9yeF2AoaQWWz6yOza4eKge1qLQXMWKDQiOn8guIyqZmRjLw5k iY02onpxrS95ZaZ4rtqek1fp5NQLsyq8X/iPWhKR0hIVtyazt2+ezaxDxkeFcZ/0 1MI5sxUt1gvPvU9pqEWEvAFgVIUhAPk/YDn0xS4ezS/fwQEcBDF4YrTO9gi69LaN lVlLHtqM0J2JZeYWVyo2uG4SYkG+/dgs+T0iAqfIOxVm2Q== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42abm5kvcd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 11:41:17 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49HBfGiV027898 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 11:41:16 GMT Received: from hu-uaggarwa-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 04:41:13 -0700 From: Uttkarsh Aggarwal To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Greg Kroah-Hartman , Felipe Balbi , Thinh Nguyen CC: , , , , , Uttkarsh Aggarwal Subject: [PATCH v2 1/2] dt-bindings: usb: snps,dwc3: Add snps,filter-se0-fsls-eop quirk Date: Thu, 17 Oct 2024 17:10:54 +0530 Message-ID: <20241017114055.13971-2-quic_uaggarwa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241017114055.13971-1-quic_uaggarwa@quicinc.com> References: <20241017114055.13971-1-quic_uaggarwa@quicinc.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xKCJljY5cY7qM0L65KI_Ii2buniblwQw X-Proofpoint-GUID: xKCJljY5cY7qM0L65KI_Ii2buniblwQw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 spamscore=0 mlxlogscore=732 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170079 Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the linestate during transmission. Only two or more SE0 is considered as valid EOP on FS/LS port. This bit is applicable only in FS in device mode and FS/LS mode of operation in host mode. Signed-off-by: Uttkarsh Aggarwal --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 1cd0ca90127d..d9e813bbcd80 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -180,6 +180,12 @@ properties: description: When set core will set Tx de-emphasis value type: boolean + snps,filter-se0-fsls-eop-quirk: + description: + When set controller will ignore single SE0 glitch on the linestate during transmit + Only two or more SE0 is considered as a valid EOP on FS/LS port. + type: boolean + snps,tx_de_emphasis: description: The value driven to the PHY is controlled by the LTSSM during USB3 From patchwork Thu Oct 17 11:40:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uttkarsh Aggarwal X-Patchwork-Id: 13839910 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 928281DDA20; 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Thu, 17 Oct 2024 11:41:24 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49HBfMGs007278 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 11:41:22 GMT Received: from hu-uaggarwa-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 04:41:19 -0700 From: Uttkarsh Aggarwal To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Greg Kroah-Hartman , Felipe Balbi , Thinh Nguyen CC: , , , , , Uttkarsh Aggarwal Subject: [PATCH v2 2/2] usb: dwc3: core: Add support to ignore single SE0 glitches Date: Thu, 17 Oct 2024 17:10:55 +0530 Message-ID: <20241017114055.13971-3-quic_uaggarwa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241017114055.13971-1-quic_uaggarwa@quicinc.com> References: <20241017114055.13971-1-quic_uaggarwa@quicinc.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 25b_0Cl65OBiCRbmF0CouGyXAeWJuac- X-Proofpoint-ORIG-GUID: 25b_0Cl65OBiCRbmF0CouGyXAeWJuac- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxlogscore=984 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170079 Currently in few of Qualcomm chips USB (Low speed) mouse not detected showing following errors: usb 1-1: Device not responding to setup address. usb 1-1: device not accepting address 2, error -71 usb 1-1: new low-speed USB device number 3 using xhci-hcd usb 1-1: Device not responding to setup address. usb 1-1: Device not responding to setup address. usb 1-1: device not accepting address 3, error -71 usb usb1-port1: attempt power cycle Based on the Logic analyzer waveforms, It has been identified that there is skew of about 8nS b/w DP & DM linestate signals (o/p of PHY & i/p to controller) at the UTMI interface, Due to this controller is seeing SE0 glitch condition, this is causing controller to pre-maturely assume that PHY has sent all the data & is initiating next packet much early, though in reality PHY is still busy sending previous packets. Enabling the GUCTL1.FILTER_SE0_FSLS_EOP bit29 allows the controller to ignore single SE0 glitches on the linestate during transmission. Only two or more SE0 signals are recognized as a valid EOP. When this feature is activated, SE0 signals on the linestate are validated over two consecutive UTMI/ULPI clock edges for EOP detection. Device mode (FS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then for device LPM handshake, the controller ignores single SE0 glitch on the linestate during transmit. Only two or more SE0 is considered as a valid EOP on FS port. Host mode (FS/LS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then the controller ignores single SE0 glitch on the linestate during transmit. Signed-off-by: Uttkarsh Aggarwal --- drivers/usb/dwc3/core.c | 13 +++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 86b37881aab4..4edd32c44e73 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -222,6 +222,17 @@ static void __dwc3_set_mode(struct work_struct *work) switch (desired_dr_role) { case DWC3_GCTL_PRTCAP_HOST: + /* + * Setting GUCTL1 bit 29 so that controller + * will ignore single SE0 glitch on the linestate + * during transmit. + */ + if (dwc->filter_se0_fsls_eop_quirk) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); + reg |= DWC3_GUCTL1_FILTER_SE0_FSLS_EOP; + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + } + ret = dwc3_host_init(dwc); if (ret) { dev_err(dwc->dev, "failed to initialize host\n"); @@ -1788,6 +1799,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, "snps,tx_de_emphasis_quirk"); + dwc->filter_se0_fsls_eop_quirk = device_property_read_bool(dev, + "snps,filter-se0-fsls-eop-quirk"); device_property_read_u8(dev, "snps,tx_de_emphasis", &tx_de_emphasis); device_property_read_string(dev, "snps,hsphy_interface", diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index cc3f32acfaf5..33d53a436fd7 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -276,6 +276,7 @@ /* Global User Control 1 Register */ #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) +#define DWC3_GUCTL1_FILTER_SE0_FSLS_EOP BIT(29) #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) @@ -1140,6 +1141,8 @@ struct dwc3_scratchpad_array { * @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter * running based on ref_clk * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk + * @filter_se0_fsls_eop_quirk: set to ignores single + * SE0 glitch on the linestate during transmit. * @tx_de_emphasis: Tx de-emphasis value * 0 - -6dB de-emphasis * 1 - -3.5dB de-emphasis @@ -1373,6 +1376,7 @@ struct dwc3 { unsigned gfladj_refclk_lpm_sel:1; unsigned tx_de_emphasis_quirk:1; + unsigned filter_se0_fsls_eop_quirk:1; unsigned tx_de_emphasis:2; unsigned dis_metastability_quirk:1;