From patchwork Thu Oct 17 13:20:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13840023 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 666251D414F for ; Thu, 17 Oct 2024 13:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729171268; cv=none; b=tgdJWDu8eN7CDG86+Dmpd6zAlRc5RudMYVrTXxLbOzzRrXHyoVykyI7xwmP4es4jJWFp3syHpwxVLHLEorMwrly6rlhx6SE2YUp56jN14l715mTXaScCfduFNoCmh4muAhAwBCpFqU0Lz/DK5VlzoPdNM9EbD3P3L6r5BNXASwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729171268; c=relaxed/simple; bh=P1ZmGdvNRNOCVcnRImmu9iHgcJfCp5HtG3O6go/+hAQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PkJl2+/N1n0Trdl1eblbYNb0fmT/hSfpY6TckJdpLpGopyV8Wd/trt0IQ804hgitiQ6x/pXRa9Pl6IFUnMySGg7jgMs8A1yiSSa3pxX3mnPUn1tdiWWQOe5zzVlXGEI5lOF02cVmdrMeqNnbOsUL7zSU3DILsOW+hsuC3DQ9ses= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kiOaIIMX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kiOaIIMX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D65DDC4CEC5; Thu, 17 Oct 2024 13:21:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729171267; bh=P1ZmGdvNRNOCVcnRImmu9iHgcJfCp5HtG3O6go/+hAQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kiOaIIMX+C0lkvU6c1Al/VYuHHPoiNhS8e7NRy4gG18c7wc+sM2N2v03X1KU5RHNr ZV/lkTBhs3l8TwoBNnN3NhEmzgaj31G9O14njrkzmgn6W2393tmhoBjxa8YPg37mEP S76V5u1eSnxWeW1Jqwb9SVFoKMZQD9WURKBh0supxR/mj85958HhTrr0Wm4a71jSUm c0ldYIvoKqnEbytu9/KnTp5uhrpzbNnN0s+x6Ii3FWps1aCDz3H1t2LUtu1prYQR0V bg7YQwbyZNFgNh/JxCtKH28sboTqB2yPJH6aCCzHH0M8mLVu8I1yJIELK17eVnvEWu Ao7WITksSWIeg== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH 1/2] PCI: dwc: ep: Fix dw_pcie_ep_align_addr() Date: Thu, 17 Oct 2024 15:20:54 +0200 Message-ID: <20241017132052.4014605-5-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241017132052.4014605-4-cassel@kernel.org> References: <20241017132052.4014605-4-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1510; i=cassel@kernel.org; h=from:subject; bh=P1ZmGdvNRNOCVcnRImmu9iHgcJfCp5HtG3O6go/+hAQ=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIF+U0mn9jG+pjB/f7RCea+6xMdo7ac7Gy6sTh5UvvMZ 6uyexes7ihlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEbhkzMszkivTs1WPS6Di7 9P3/TawrJmsYKf7UsPj3aV97g8OmkOMMv9m3c2Y1zuFMmPZePzf7fcfvIt3pZ9dUr5K6eKrvtbi VCj8A X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA ep->page_size is defined by the EPC drivers. Some drivers e.g. pci-imx6.c defines this to 4K for imx95. dw_pcie_ep_init() will call pci_epc_mem_init() with ep->page_size. pci_epc_mem_init() will call pci_epc_multi_mem_init(). pci_epc_multi_mem_init() will initialize mem->window.page_size. If the provided page_size (ep->page_size) is smaller than PAGE_SIZE, it will initialize mem->window.page_size to PAGE_SIZE rather than ep->page_size. Thus, mem->window.page_size can be larger than ep->page_size, e.g. for a platform built with PAGE_SIZE == 64K, while using a EPC driver that defines ep->page_size to 4k. Therefore, modify dw_pcie_ep_align_addr() to use epc->mem->window.page_size rather than ep->page_size. Signed-off-by: Niklas Cassel Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 2d0e7bf17919..20f67fd85e83 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -276,7 +276,7 @@ static u64 dw_pcie_ep_align_addr(struct pci_epc *epc, u64 pci_addr, u64 mask = pci->region_align - 1; size_t ofst = pci_addr & mask; - *pci_size = ALIGN(ofst + *pci_size, ep->page_size); + *pci_size = ALIGN(ofst + *pci_size, epc->mem->window.page_size); *offset = ofst; return pci_addr & ~mask; From patchwork Thu Oct 17 13:20:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13840024 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D3341DDC23 for ; Thu, 17 Oct 2024 13:21:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729171271; cv=none; b=E8KmZ9xxLtD4ZcMy/hQijMpoP2svFeg/L67Sks/Kw7ojuyOKWegisRt5ht12azn/dHrryUFHnS7Cv/bxlUoxJso7fWo7vzJDxwoRGDusDZsZB80D/zl3PlSdq4zD78oL5BM9KVn1L6RCrDDzR+707+uDQEHPBlxXbL/h/ezce3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729171271; c=relaxed/simple; bh=yWslHkUx6l1i6GOuEAQUNChrg7orIrbupz2/AEvguxU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bhPi7G+KBiSYyb74whFQNiJOKStWKJ/wJLOmVuZ+I9gA+GpoVjCmfoD3WTpeFpGbz5wxer3Nt7edyiGV/cD5zJkE3RD8pDWxSohmsgYf10qs9JB0iLy3kGFbImIcCa8hnmy6vwFN2slzPve+EqQdpOe2oK8xJwZJCMDuqozY0Io= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=r70xhdwp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="r70xhdwp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9FED3C4CECD; Thu, 17 Oct 2024 13:21:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729171270; bh=yWslHkUx6l1i6GOuEAQUNChrg7orIrbupz2/AEvguxU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r70xhdwpXMlu5UTFGKuApLEI5Yqifx+Qxa91qMzHKLxmrcLMH5iIbod/l5Vc+PLgT CMIwsRi+lBQUSXRRbAmAPzpwlk8IVs7w4JDAijFCkLgbokT1XsnKp88y8xquPGzAqm oZHhc7alcGimp0bUt1VgLAhhffvYeBi3uUgb4rzGc7lh2AOQ4PnfgBDw2xhmcm7cLf Tv/8+xx58lA5N1Bpqb1FARlXm4zz2TANj1Tpshsb2siV6wifRf/IUVfpYMP1dM76KJ M/Cuv319O69lITlmuWwghi68VeCG5RIbmPceqlqDYDmlkCnlYZvhZwWOC5fUXlTwv+ /sq5b3ycxNtQw== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH 2/2] PCI: dwc: ep: Use align addr function for dw_pcie_ep_raise_{msi,msix}_irq() Date: Thu, 17 Oct 2024 15:20:55 +0200 Message-ID: <20241017132052.4014605-6-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241017132052.4014605-4-cassel@kernel.org> References: <20241017132052.4014605-4-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2693; i=cassel@kernel.org; h=from:subject; bh=yWslHkUx6l1i6GOuEAQUNChrg7orIrbupz2/AEvguxU=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIF+U3N9VR2GWceYbor2NbYs1mxrHf/si//fmSk7P18p zDsf4NKRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACaS6sbIsNPsp+R08f4+yZa9 ixkW2NhMNhByfDTt+soqx44uRd+fMYwMeycr3n2kxrApbQI7sxHXnIuMkvO+pzUn2bqJmLOI8no zAwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Use the dw_pcie_ep_align_addr() function to calculate the alignment in dw_pcie_ep_raise_{msi,msix}_irq() instead of open coding the same. Signed-off-by: Niklas Cassel Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- .../pci/controller/dwc/pcie-designware-ep.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 20f67fd85e83..9bafa62bed1d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -503,7 +503,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u32 msg_addr_lower, msg_addr_upper, reg; struct dw_pcie_ep_func *ep_func; struct pci_epc *epc = ep->epc; - unsigned int aligned_offset; + size_t msi_mem_size = epc->mem->window.page_size; + size_t offset; u16 msg_ctrl, msg_data; bool has_upper; u64 msg_addr; @@ -531,14 +532,13 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, } msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower; - aligned_offset = msg_addr & (epc->mem->window.page_size - 1); - msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); + msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &msi_mem_size, &offset); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, - epc->mem->window.page_size); + msi_mem_size); if (ret) return ret; - writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); + writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset); dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys); @@ -589,8 +589,9 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, struct pci_epf_msix_tbl *msix_tbl; struct dw_pcie_ep_func *ep_func; struct pci_epc *epc = ep->epc; + size_t msi_mem_size = epc->mem->window.page_size; + size_t offset; u32 reg, msg_data, vec_ctrl; - unsigned int aligned_offset; u32 tbl_offset; u64 msg_addr; int ret; @@ -615,14 +616,13 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, return -EPERM; } - aligned_offset = msg_addr & (epc->mem->window.page_size - 1); - msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); + msg_addr = dw_pcie_ep_align_addr(epc, msg_addr, &msi_mem_size, &offset); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret) return ret; - writel(msg_data, ep->msi_mem + aligned_offset); + writel(msg_data, ep->msi_mem + offset); dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);