From patchwork Fri Oct 18 18:22:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13842193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38F52D3DEA4 for ; Fri, 18 Oct 2024 18:26:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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AJvYcCWYOdovZ3bC7ZOznC/JieAWfdqza/oKmY5mMt/ezT3xqe2pOteB8wVAhYhZ9x7/xheV0N/TxN5XChgp2T1LiTxp@lists.infradead.org X-Gm-Message-State: AOJu0YyFjTluzyLi3c8+51WzQV9M0p6uBLN9l5W8WfMCB63fb+0r6Epi LP39w+dcX0ZVYKCKAQlWUzGlIFq6je9Vdpz6kqjryGlN549PmpKAKNsG8PVCrA== X-Google-Smtp-Source: AGHT+IGcpmdltCUQTW2s4jU6bQRrXu/0O4LNqJ9bfrIVMrCKcLJUAx2oJIDi0KGExJyBGL3g8cHHNQ== X-Received: by 2002:a05:6830:3988:b0:718:4e3:1b27 with SMTP id 46e09a7af769-7181a6ed3ccmr2995907a34.8.1729275772249; Fri, 18 Oct 2024 11:22:52 -0700 (PDT) Received: from stbsrv-and-02.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cde114d782sm9307616d6.46.2024.10.18.11.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 11:22:51 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/1] RFC: dt bindings: Add property "brcm,gen3-eq-presets" Date: Fri, 18 Oct 2024 14:22:45 -0400 Message-ID: <20241018182247.41130-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241018182247.41130-1-james.quinlan@broadcom.com> References: <20241018182247.41130-1-james.quinlan@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241018_112254_505872_82D545C9 X-CRM114-Status: GOOD ( 11.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support configuration of the GEN3 preset equalization settings, aka the Lane Equalization Control Register(s) of the Secondary PCI Express Extended Capability. These registers are of type HwInit/RsvdP and typically set by FW. In our case they are set by our RC host bridge driver using internal registers. Signed-off-by: Jim Quinlan --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 0925c520195a..f965ad57f32f 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -104,6 +104,18 @@ properties: minItems: 1 maxItems: 3 + brcm,gen3-eq-presets: + description: | + A u16 array giving the GEN3 equilization presets, one for each lane. + These values are destined for the 16bit registers known as the + Lane Equalization Control Register(s) of the Secondary PCI Express + Extended Capability. In the array, lane 0 is first term, lane 1 next, + etc. The contents of the entries reflect what is necessary for + the current board and SoC, and the details of each preset are + described in Section 7.27.4 of the PCI base spec, Revision 3.0. + + $ref: /schemas/types.yaml#/definitions/uint16-array + required: - compatible - reg