From patchwork Mon Oct 21 09:55:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Federico Serafini X-Patchwork-Id: 13843779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50C70D0E6D8 for ; Mon, 21 Oct 2024 09:55:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.823277.1237242 (Exim 4.92) (envelope-from ) id 1t2p8F-00040V-36; Mon, 21 Oct 2024 09:55:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 823277.1237242; Mon, 21 Oct 2024 09:55:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t2p8F-00040O-0U; Mon, 21 Oct 2024 09:55:23 +0000 Received: by outflank-mailman (input) for mailman id 823277; Mon, 21 Oct 2024 09:55:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t2p8C-00040H-AC for xen-devel@lists.xenproject.org; Mon, 21 Oct 2024 09:55:21 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 944a1479-8f92-11ef-a0be-8be0dac302b0; Mon, 21 Oct 2024 11:55:19 +0200 (CEST) Received: from truciolo.bugseng.com (unknown [37.163.179.18]) by support.bugseng.com (Postfix) with ESMTPSA id 822BB4EE0737; Mon, 21 Oct 2024 11:55:17 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 944a1479-8f92-11ef-a0be-8be0dac302b0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=bugseng.com; s=mail; t=1729504518; bh=Y+u7e5DLnPPoRwdo2M0VVHEj6Bi+ttyz8sg120Qh7JY=; h=From:To:Cc:Subject:Date:From; b=TaaTuVdqpMqxbAZfRhQG9tcmp9/aoWN7PHgZ4qL7Yxg27pP1hu1TXhagbhteYXpCe YXBbX6txRlGRwwE+lDtu8nQSZWgARxaLcPH8/f6YBAm8GrDt8esGAhUNiJBQnzE4IO lQRhsYuJ+fNbOypaILQ8Vxh0CxVRlJM8jNBJ6ripaG05TUHaBiT3hBF6XyEzw9ZHDv 8HU6InnMh19qpt4xp7cDBLbOxsqiUMXLmF57eY2ZCCwz7O7N9DbHE4LoN+6PCSc98A PiCc8TBCmPpXwtmifkdOL66mY4QiPC8JdugGn8lP5NpTMBIMsTu6tjL6F1Y+y6Go2e rYJhp3/3vfHgw== From: Federico Serafini To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Federico Serafini , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v3] x86/emul: address violations of MISRA C Rule 16.3 Date: Mon, 21 Oct 2024 11:55:10 +0200 Message-ID: <63d51d39995c8dbab6f02d74982287a238ee5353.1729500464.git.federico.serafini@bugseng.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Add missing break statements to address violations of MISRA C:2012 Rule 16.3 (An unconditional `break' statement shall terminate every switch-clause). Make explicit unreachability of a program point with ASSERT_UNREACHABLE() and add defensive code. No functional change. Signed-off-by: Federico Serafini Acked-by: Andrew Cooper --- Changes in v3: - return error code from the ureachable path. Changes in v2: - unreachability made explicit. --- xen/arch/x86/x86_emulate/fpu.c | 5 +++++ xen/arch/x86/x86_emulate/x86_emulate.c | 1 + 2 files changed, 6 insertions(+) diff --git a/xen/arch/x86/x86_emulate/fpu.c b/xen/arch/x86/x86_emulate/fpu.c index 480d879657..54c8621421 100644 --- a/xen/arch/x86/x86_emulate/fpu.c +++ b/xen/arch/x86/x86_emulate/fpu.c @@ -218,6 +218,7 @@ int x86emul_fpu(struct x86_emulate_state *s, */ if ( dst->type == OP_MEM && !s->fpu_ctrl && !fpu_check_write() ) dst->type = OP_NONE; + break; } break; @@ -296,6 +297,7 @@ int x86emul_fpu(struct x86_emulate_state *s, default: generate_exception(X86_EXC_UD); } + break; } break; @@ -386,6 +388,7 @@ int x86emul_fpu(struct x86_emulate_state *s, */ if ( dst->type == OP_MEM && !s->fpu_ctrl && !fpu_check_write() ) dst->type = OP_NONE; + break; } break; @@ -457,6 +460,8 @@ int x86emul_fpu(struct x86_emulate_state *s, case 7: /* fistp m64i */ goto fpu_memdst64; } + ASSERT_UNREACHABLE(); + return X86EMUL_UNHANDLEABLE; } break; diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c index 6b6b8c8fe4..30674ec301 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -8310,6 +8310,7 @@ x86_emulate( } if ( rc != 0 ) goto done; + break; default: break; }