From patchwork Mon Oct 21 12:33:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52C94D15D89 for ; Mon, 21 Oct 2024 12:32:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D61D910E4C2; Mon, 21 Oct 2024 12:32:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Vv4Ak5Ry"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id B5E9F10E4C0; Mon, 21 Oct 2024 12:32:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513921; x=1761049921; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=16YGV2AfVAnjcnpXbJt/1vBRhQyK2Gph/TthHGprQMw=; b=Vv4Ak5RymEwvpNifZXr1k0Uo7U1gaQ4evucPea+ETuXRX7ELvp8dTOgF HcYijd2KBjX6lhsazTMGlCVh1k0ONZZ5I1biakfhDeJammMiF2lg4RumD YPUR5lylhS8Nt0gsRiO+Jud3qV3Rh8scpIw06aGfYWE98mIUD7DHtQNLN qHpB6PFCfzDQNu8xKwq7G62C/tdcTB6phxKK1qUpHzTM94YznrKpmydl4 VC+OwCH+BWZ5+oWiPDRqC3YQfenvXWl0SVHfvG/vp7KIZ3vI6UBr8DWWJ 2kpvEHpmkfN3UGMeEmledHXdgaAOnASbPiM36hGRco0byMphYPGvGELDQ A==; X-CSE-ConnectionGUID: lxC+tvSuRVidNgjoB/s6Ew== X-CSE-MsgGUID: uhl6uCZnR9q3c9jAxUQfOA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459623" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459623" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:01 -0700 X-CSE-ConnectionGUID: 5jLKqSALTWWX3w2oqbQtSg== X-CSE-MsgGUID: 2rW0wDnUScSmfW5BOD9gBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866038" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:00 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices per Line Date: Mon, 21 Oct 2024 18:03:59 +0530 Message-ID: <20241021123414.3993899-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For some platforms, the maximum slices per DSC engine is 4, while for others it is 2. Update the comment to reflect this and clarify that the 'valid_dsc_slicecount' list represents the valid number of slices per pipe. Currently, we are working with 1, and 2 slices per DSC engine, which works for all platforms. With this the number of slices per pipe can be 1,2 or 4 with different slice & DSC engine configuration. Add a #TODO for adding support for 4 slices per DSC engine where supported. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7e04913bc2ff..286b272aa98c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -108,8 +108,14 @@ /* Constants for DP DSC configurations */ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; -/* With Single pipe configuration, HW is capable of supporting maximum - * of 4 slices per line. +/* + * With Single pipe configuration, HW is capable of supporting maximum of: + * 2 slices per line for ICL, BMG + * 4 slices per line for other platforms. + * For now consider a max of 2 slices per line, which works for all platforms. + * With this we can have max of 4 DSC Slices per pipe. + * + * #TODO Split this better to use 4 slices/dsc engine where supported. */ static const u8 valid_dsc_slicecount[] = {1, 2, 4}; From patchwork Mon Oct 21 12:34:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A78DED15D8C for ; Mon, 21 Oct 2024 12:32:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D22110E4C5; Mon, 21 Oct 2024 12:32:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IvafJwuz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 495B010E4C4; Mon, 21 Oct 2024 12:32:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513923; x=1761049923; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/lb9CWrQF+avW+fScSJyBbgZBo0l+AGYO5yXkCen0zY=; b=IvafJwuzY0Es2bwSg08tlTHjxor2HJq8uPMSZphrdwnm+gEEVWRea6uY avGaeV57+p1RAO0HSEKjG1K68BE+b+B3sonvmz7dwhipgkLhFy3wgXK+8 ASA+gwy5OIuoBC15D3PoMi9SA7fbMD22nWdYNas1Of6SVS/Peqyy9bfJw 7At/jUs7UCPWh6+khdj/YfB1xvCW22N5IGEEBZKyBehHnqHmUM/0Je9ek 4IASMoS3+HqytifwEMDp4oTuQAhLy9zoK4r0y0SCs7VD1BFLNwYzJfBow yQigXIw8XHeH2O6EXoEZOY3gmBA1fzVzJXfJYfkOoFWHTzk6X9cDVAG82 w==; X-CSE-ConnectionGUID: t5Hl92INRDWhKGffv3I65A== X-CSE-MsgGUID: wHjjdS6zSXSWqp0AHRwhAQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459625" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459625" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:03 -0700 X-CSE-ConnectionGUID: Nu6eAKXCTS6UwMNqdskDFQ== X-CSE-MsgGUID: qOXeJROLQuy+48e64ik+yA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866044" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:02 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter Date: Mon, 21 Oct 2024 18:04:00 +0530 Message-ID: <20241021123414.3993899-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" At the moment dsc_split represents that dsc splitter is used or not. With 3 DSC engines, the splitter can split into two streams or three streams. Make the member dsc_split as int and set that to 2 when dsc splitter splits to 2 stream. v2: Avoid new enum for dsc split. (Suraj) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 20 ++++++++++++++----- 5 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 87a27d91d15d..553e75cf118c 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1595,7 +1595,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, /* FIXME: split only when necessary */ if (crtc_state->dsc.slice_count > 1) - crtc_state->dsc.dsc_split = true; + crtc_state->dsc.dsc_split = 2; /* FIXME: initialize from VBT */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef1436146325..9e2f0fd0558f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); PIPE_CONF_CHECK_BOOL(dsc.compression_enable); - PIPE_CONF_CHECK_BOOL(dsc.dsc_split); + PIPE_CONF_CHECK_I(dsc.dsc_split); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); PIPE_CONF_CHECK_BOOL(splitter.enable); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f..58f510909f4d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1235,7 +1235,7 @@ struct intel_crtc_state { /* Display Stream compression state */ struct { bool compression_enable; - bool dsc_split; + int dsc_split; /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; u8 slice_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 286b272aa98c..c1867c883b73 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2409,7 +2409,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * then we need to use 2 VDSC instances. */ if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) - pipe_config->dsc.dsc_split = true; + pipe_config->dsc.dsc_split = 2; ret = intel_dp_dsc_compute_params(connector, pipe_config); if (ret < 0) { diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 40525f5c4c42..3bce13c21756 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -379,7 +379,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) { - return crtc_state->dsc.dsc_split ? 2 : 1; + switch (crtc_state->dsc.dsc_split) { + case 2: + return 2; + case 0: + default: + break; + } + return 1; } int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) @@ -976,8 +983,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) if (!crtc_state->dsc.compression_enable) goto out; - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && - (dss_ctl1 & JOINER_ENABLE); + if ((dss_ctl1 & JOINER_ENABLE) && + (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE)) + crtc_state->dsc.dsc_split = 2; + else + crtc_state->dsc.dsc_split = 0; intel_dsc_get_pps_config(crtc_state); out: @@ -988,10 +998,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state) { drm_printf_indent(p, indent, - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n", + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n", FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), crtc_state->dsc.slice_count, - str_yes_no(crtc_state->dsc.dsc_split)); + crtc_state->dsc.dsc_split); } void intel_vdsc_state_dump(struct drm_printer *p, int indent, From patchwork Mon Oct 21 12:34:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07DAED15D88 for ; Mon, 21 Oct 2024 12:32:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 972BE10E4C6; Mon, 21 Oct 2024 12:32:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Y1RZar5y"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA14810E4C9; Mon, 21 Oct 2024 12:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513924; x=1761049924; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=45Jo4JD1pRmWm0ln4iUp/JE7O+O23vcHkHp8S8vZono=; b=Y1RZar5yOCa3wDH4vkNn0kJKpDkzE1vtX5xO9BD9dnN6pg0ygeEUC4t0 GPArTYygMQbB2aoTJ2CFeP0kbZjUzANS2EPThF+v/fzfeAxH4RJQjdy2Q DLSU/OdgF8f326eIqsjfNYjjHsDVZGIPFvoDHiaaeuYczxEFqEM3bBG0P p397xYcXJBIuFimmSnlG23Q6Gv86hh3ush/Pz0V8O+Jo/nYyTCqAD7BTx F/wqh86sEeMh2wty2kG425EvARHKnlSGZE+7zeBl9776m+Eog0JUBH/I7 pL2tX82LRUibCT9ycWw40UnNDlkRBFhWJEz7C2/p5b6YsGc1Wrya+F7J8 g==; X-CSE-ConnectionGUID: 30tUjesYR0q9kKXL72xNyw== X-CSE-MsgGUID: 0LnDGRJTTTecABW/qXuDZA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459627" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459627" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:04 -0700 X-CSE-ConnectionGUID: MruH7uBmQTiavXCdCQ+cTA== X-CSE-MsgGUID: 645pO+KzRY2K0RNypEU1PA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866050" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:03 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 03/16] drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Date: Mon, 21 Oct 2024 18:04:01 +0530 Message-ID: <20241021123414.3993899-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead. While at it, use REG_BIT macro for the bits. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 3bce13c21756..198446738662 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -777,9 +777,9 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) intel_dsc_pps_configure(crtc_state); - dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; + dss_ctl2_val |= VDSC0_ENABLE; if (vdsc_instances_per_pipe > 1) { - dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; + dss_ctl2_val |= VDSC1_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } if (crtc_state->joiner_pipes) { @@ -979,12 +979,12 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); - crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; + crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; if (!crtc_state->dsc.compression_enable) goto out; if ((dss_ctl1 & JOINER_ENABLE) && - (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE)) + (dss_ctl2 & VDSC1_ENABLE)) crtc_state->dsc.dsc_split = 2; else crtc_state->dsc.dsc_split = 0; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index bf32a3b46fb1..d7a72b95ee7e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -21,8 +21,8 @@ #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 #define DSS_CTL2 _MMIO(0x67404) -#define LEFT_BRANCH_VDSC_ENABLE (1 << 31) -#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) +#define VDSC0_ENABLE REG_BIT(31) +#define VDSC1_ENABLE REG_BIT(15) #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) From patchwork Mon Oct 21 12:34:02 2024 Content-Type: text/plain; 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d="scan'208";a="79866058" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:05 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 Date: Mon, 21 Oct 2024 18:04:02 +0530 Message-ID: <20241021123414.3993899-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduce the register bits to enable the 3rd DSC engine VDSC2. Add support to read/write these bits. v2: Only introduce bits that are used and update the subject and commit message. (Suraj) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 20 +++++++++++++++---- .../gpu/drm/i915/display/intel_vdsc_regs.h | 2 ++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 198446738662..70b75de921de 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -380,6 +380,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) { switch (crtc_state->dsc.dsc_split) { + case 3: + return 3; case 2: return 2; case 0: @@ -782,6 +784,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) dss_ctl2_val |= VDSC1_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } + + if (vdsc_instances_per_pipe > 2) { + dss_ctl2_val |= VDSC2_ENABLE; + dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES; + } + if (crtc_state->joiner_pipes) { if (intel_crtc_ultrajoiner_enable_needed(crtc_state)) dss_ctl1_val |= ULTRA_JOINER_ENABLE; @@ -983,11 +991,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) if (!crtc_state->dsc.compression_enable) goto out; - if ((dss_ctl1 & JOINER_ENABLE) && - (dss_ctl2 & VDSC1_ENABLE)) - crtc_state->dsc.dsc_split = 2; - else + if (dss_ctl1 & JOINER_ENABLE) { + if (dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES)) + crtc_state->dsc.dsc_split = 3; + + else if (dss_ctl2 & VDSC1_ENABLE) + crtc_state->dsc.dsc_split = 2; + } else { crtc_state->dsc.dsc_split = 0; + } intel_dsc_get_pps_config(crtc_state); out: diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index d7a72b95ee7e..474a7f9f3881 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -22,6 +22,8 @@ #define DSS_CTL2 _MMIO(0x67404) #define VDSC0_ENABLE REG_BIT(31) +#define VDSC2_ENABLE REG_BIT(30) +#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) #define VDSC1_ENABLE REG_BIT(15) #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) From patchwork Mon Oct 21 12:34:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D84DD15D8B for ; Mon, 21 Oct 2024 12:32:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D4EB10E4C1; Mon, 21 Oct 2024 12:32:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WsH7Wu2s"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCDAB10E4C9; Mon, 21 Oct 2024 12:32:07 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="79866063" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:06 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 05/16] drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine Date: Mon, 21 Oct 2024 18:04:03 +0530 Message-ID: <20241021123414.3993899-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS registers for the 3rd DSC engine Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +++++--- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 6 ++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 70b75de921de..777a287210f9 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -411,8 +411,10 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); - if (dsc_reg_num >= 3) + if (dsc_reg_num >= 4) MISSING_CASE(dsc_reg_num); + if (dsc_reg_num >= 3) + dsc_reg[2] = BMG_DSC2_PPS(pipe, pps); if (dsc_reg_num >= 2) dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps); if (dsc_reg_num >= 1) @@ -424,7 +426,7 @@ static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - i915_reg_t dsc_reg[2]; + i915_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); @@ -824,7 +826,7 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - i915_reg_t dsc_reg[2]; + i915_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; u32 val; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 474a7f9f3881..2d478a84b07c 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -59,8 +59,10 @@ #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 +#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB 0x78970 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 +#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC 0x78A70 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) @@ -73,8 +75,12 @@ #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) +#define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB, \ + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC) #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) +#define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4)) /* PPS 0 */ #define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23) From patchwork Mon Oct 21 12:34:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9337ED15D88 for ; Mon, 21 Oct 2024 12:32:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 19F3510E4D3; Mon, 21 Oct 2024 12:32:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Aq36DFIX"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 69C9D10E4CD; Mon, 21 Oct 2024 12:32:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513929; x=1761049929; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=znCaLqnPy/7IV0Bh2ni48f1o+vTltB1VMgWZvXZ65DQ=; b=Aq36DFIXch313JMM/1jINK61qGYhKe18YHk+62TZhyVQbe0pM/rq/1Cc F5z+mvskoXFGgAYm7aP441AmJ4H1uYoCDq8lBxx2MRIIQYRksrdj7uTCU LMoxzKygnQouijv3vVQ+xPGhyJMOSQW4zo+eNgErvn1ydycyA196ycgTK 0n+5KB9XLAaFzNSXd02jarwOYtS/QSFEheGiRdt9DgCLTQ4kyKpoGE7BG 2jA7qK+TPKbLTKAXA4gEcfZO5hwakWc3eujncpCDklZAW3bO//xmkas7N bqvkzwjbtkrgDqDn7jOvIqIVs0H3rvuihiyEsgv38QVFMM5msskgLQp1B g==; X-CSE-ConnectionGUID: dsB4suDjTNCLmyC+vAL+5w== X-CSE-MsgGUID: pCX81wg9TNyRFi6aqhdpBA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459634" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459634" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:09 -0700 X-CSE-ConnectionGUID: 0ktPJf5QRSWGTpB6tivIMQ== X-CSE-MsgGUID: jA657nCYTg+ShQ+DjhT0JA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866070" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:08 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count Date: Mon, 21 Oct 2024 18:04:04 +0530 Message-ID: <20241021123414.3993899-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to the DSC spec, the slice width should be chosen such that the picture width (hactive) is evenly divisible by the slice width. If not, extra pixels (padding) must be added to the last slice to ensure all slices have the same width. Currently, we do not support handling these extra pixels. Therefore, select a slice count that evenly divides the hactive (slice_width = hactive / slice_count). This check is already implemented for DSI, where the slice count is selected from the BIOS. For DP, currently with 1, 2, 4 slices per pipe it is unlikely to have slice count not being able to divide hactive, but with 3 DSC engines and 3 slices, we can have such cases. Adding this check prepares for future scenarios where such configurations might be used. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c1867c883b73..0607ea4ee321 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1037,6 +1037,9 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) continue; + if (mode_hdisplay % test_slice_count) + continue; + if (min_slice_count <= test_slice_count) return test_slice_count; } From patchwork Mon Oct 21 12:34:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01457D15D87 for ; Mon, 21 Oct 2024 12:32:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F18C10E4CC; Mon, 21 Oct 2024 12:32:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LHzm4PNF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id EFB0D10E4CD; Mon, 21 Oct 2024 12:32:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513931; x=1761049931; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F9+fx4zy4nPeJawpBwIARnw1h1SvPfHF7yaMKklr2pk=; b=LHzm4PNFPf3H8d7tgpe57euhj2BubmYbzL7V81tYJexejDfMJzFGR4K5 FVjMVww2dA41U9Aql1UeBmeKB6vYj7y13AgCuk75K5mcQxeWE0qyteSkb OU1ZBCgQgCQQQZ8gIscW8FAwLbi7KAJNL8khPOkESCIFBoUjCnz4uXF4P J9+b71KIhUj4Pa4Oa2mYJeqYEASqIoNe2KHbLw34ZsHy/iF47xXhRxSYJ RzJrhgiqbvBZaxa40hVwT10tphhtCQd55b3A8a/QAoolZDFjg5ogkg2c5 XKLJlWDZADNwaxUZ5kIe0VKfm0govQkZdIusxNmBJsj/Yv29HgE6kR1IK Q==; X-CSE-ConnectionGUID: eSqShx4fQBu2IqaUZcoWRg== X-CSE-MsgGUID: ntgPupnFRaSLOV+1Z61uvw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459636" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459636" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:10 -0700 X-CSE-ConnectionGUID: jeVsDfb6Ssusfc1o0XHuyg== X-CSE-MsgGUID: DmdaSx1SRKaZEk7+Mrs7yw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866075" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:09 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 07/16] drm/i915/dp: Enable 3 DSC engines for 12 slices Date: Mon, 21 Oct 2024 18:04:05 +0530 Message-ID: <20241021123414.3993899-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Certain resolutions require 12 DSC slices support along with ultrajoiner. For such cases, the third DSC Engine per Pipe is enabled. Each DSC Engine processes 1 Slice, resulting in a total of 12 VDSC slices (4 Pipes * 3 DSC Instances per Pipe). Add support for 12 DSC slices and 3 DSC engines for such modes. v2: Add missing check for 3 slices support only with 4 joined pipes. (Suraj) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0607ea4ee321..53a437caacac 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,9 +115,12 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; * For now consider a max of 2 slices per line, which works for all platforms. * With this we can have max of 4 DSC Slices per pipe. * + * For higher resolutions where 12 slice support is required with + * ultrajoiner, only then each pipe can support 3 slices. + * * #TODO Split this better to use 4 slices/dsc engine where supported. */ -static const u8 valid_dsc_slicecount[] = {1, 2, 4}; +static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; /** * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) @@ -1025,6 +1028,13 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; + /* + * 3 DSC Slices per pipe need 3 DSC engines, + * which is supported only with Ultrajoiner. + */ + if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4) + continue; + if (test_slice_count > drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) break; @@ -2410,8 +2420,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. + * In case of Ultrajoiner along with 12 slices we need to use 3 + * VDSC instances. */ - if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) + if (pipe_config->joiner_pipes && num_joined_pipes == 4 && + pipe_config->dsc.slice_count == 12) + pipe_config->dsc.dsc_split = 3; + else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) pipe_config->dsc.dsc_split = 2; ret = intel_dp_dsc_compute_params(connector, pipe_config); From patchwork Mon Oct 21 12:34:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B986ED15D8C for ; Mon, 21 Oct 2024 12:32:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F74C10E4D2; Mon, 21 Oct 2024 12:32:13 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NPJAfhnM"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C51A10E4CC; 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21 Oct 2024 05:32:12 -0700 X-CSE-ConnectionGUID: WB6Pn9oQQSax2OKfMP0UGw== X-CSE-MsgGUID: RrVCs4Z3QMew+kEsFVh/cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866081" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:11 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION Date: Mon, 21 Oct 2024 18:04:06 +0530 Message-ID: <20241021123414.3993899-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add macro for Pixel replication support with DSC. Bspec: 49259, 68912. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 071a36b51f79..a21b910879df 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -149,6 +149,9 @@ enum intel_display_subplatform { #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) +#define HAS_PIXEL_REPLICATION(i915) (HAS_DSC(i915) && \ + (DISPLAY_VER(i915) >= 20 || \ + DISPLAY_VER_FULL(i915) == IP_VER(14, 1))) #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) From patchwork Mon Oct 21 12:34:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B239D15D8A for ; Mon, 21 Oct 2024 12:32:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CBF3210E4C3; Mon, 21 Oct 2024 12:32:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KmHHOug8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F7BB10E4CC; Mon, 21 Oct 2024 12:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513934; x=1761049934; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OBfGZua7aq4y0UKazEUposZIJ/geY85i19WZCqaFJko=; b=KmHHOug8QbyBCtYqwBwnQ+YQe+JEqz6SZDJlJE4eWn59tOL4ZItOCVvp ywC5/bwEMYjuCSP3Hd9bePSB8evx9Q4sgWOTzEsmnaTcWe42pLBEOZhmB H0l4RfCZohIrEO05raIQcs+9YRyTbvBw8MerqHxs8FGkCJn6l68yWkfyZ P+aRxA7UQAW5YuSlgXho29I3vEGW0Iu3Wh+EsBSLhTstvZ3J8Kl45s/jw 9NTfpcHeHRCvttW1LtbfZ8TlPQCWws4w2Sulf/e7YWtTdbNG+U9SbBbrw rO62K1S4w4QsQ6Hs+4iWzhl1nXJ9Tdten3kkgZ+/ajJabvaRgw/VFCehA A==; X-CSE-ConnectionGUID: Dqe0+iXRRqODmj+lTY7FQA== X-CSE-MsgGUID: 8rnBomg9SE69Mb+40s2OlA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459642" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459642" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:13 -0700 X-CSE-ConnectionGUID: YfAhERo0Rn2+WiVx6LAp7w== X-CSE-MsgGUID: uyc5CGVRRwCOVOVp/yROLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866084" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:12 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 09/16] drm/i915/display: Add support for DSC pixel replication Date: Mon, 21 Oct 2024 18:04:07 +0530 Message-ID: <20241021123414.3993899-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With 3 VDSC engines and Ultrajoiner, we may encounter a situation where hactive is not a multiple of slice count. In this case we need to add extra pixels to the last slice to distribute pixels evenly across slices. Add member to store DSC pixel replication when hactive is not divisible by slice count. Fill DSS_CTL3 register with the replicated pixel count. Also add this in dsc state dump. v2: Use macro REG_FIELD_PREP and HAS_PIXEL_REPLICATION. (Suraj) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 25 +++++++++++++++++-- .../gpu/drm/i915/display/intel_vdsc_regs.h | 8 ++++++ 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9e2f0fd0558f..1b772f58998e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5743,6 +5743,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(dsc.compression_enable); PIPE_CONF_CHECK_I(dsc.dsc_split); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); + PIPE_CONF_CHECK_I(dsc.replicated_pixels); PIPE_CONF_CHECK_BOOL(splitter.enable); PIPE_CONF_CHECK_I(splitter.link_count); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 58f510909f4d..17554f52611c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1239,6 +1239,7 @@ struct intel_crtc_state { /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; u8 slice_count; + int replicated_pixels; struct drm_dsc_config config; } dsc; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 777a287210f9..14cc1ef3641e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -774,6 +774,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; u32 dss_ctl2_val = 0; + u32 dss_ctl3_val = 0; int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); if (!crtc_state->dsc.compression_enable) @@ -804,8 +805,16 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) if (intel_crtc_is_bigjoiner_primary(crtc_state)) dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } + + if (crtc_state->dsc.replicated_pixels) + dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.replicated_pixels); + intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); + + if (HAS_PIXEL_REPLICATION(dev_priv) && dss_ctl3_val) + intel_de_write(dev_priv, + BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder), dss_ctl3_val); } void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) @@ -818,6 +827,10 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) old_crtc_state->joiner_pipes) { intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); + + if (HAS_PIXEL_REPLICATION(dev_priv)) + intel_de_write(dev_priv, + BMG_PIPE_DSS_CTL3(old_crtc_state->cpu_transcoder), 0); } } @@ -975,7 +988,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; - u32 dss_ctl1, dss_ctl2; + u32 dss_ctl1, dss_ctl2, dss_ctl3 = 0; if (!intel_dsc_source_support(crtc_state)) return; @@ -989,6 +1002,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); + if (HAS_PIXEL_REPLICATION(dev_priv)) + dss_ctl3 = intel_de_read(dev_priv, BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder)); + crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; if (!crtc_state->dsc.compression_enable) goto out; @@ -1003,6 +1019,10 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.dsc_split = 0; } + if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) + crtc_state->dsc.replicated_pixels = + dss_ctl3 & DSC_PIXEL_REPLICATION_MASK; + intel_dsc_get_pps_config(crtc_state); out: intel_display_power_put(dev_priv, power_domain, wakeref); @@ -1012,9 +1032,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state) { drm_printf_indent(p, indent, - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %d\n", + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, replicated pixels: %d split: %d\n", FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), crtc_state->dsc.slice_count, + crtc_state->dsc.replicated_pixels, crtc_state->dsc.dsc_split); } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 2d478a84b07c..f07fad6239bc 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -50,6 +50,14 @@ _ICL_PIPE_DSS_CTL2_PB, \ _ICL_PIPE_DSS_CTL2_PC) +#define _BMG_PIPE_DSS_CTL3_PB 0x782f0 +#define _BMG_PIPE_DSS_CTL3_PC 0x784f0 +#define BMG_PIPE_DSS_CTL3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _BMG_PIPE_DSS_CTL3_PB, \ + _BMG_PIPE_DSS_CTL3_PC) +#define DSC_PIXEL_REPLICATION_MASK REG_GENMASK(15, 0) +#define DSC_PIXEL_REPLICATION(count) (REG_FIELD_PREP(DSC_PIXEL_REPLICATION_MASK, (count))) + /* Icelake Display Stream Compression Registers */ #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) From patchwork Mon Oct 21 12:34:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F2E8D15D87 for ; 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X-CSE-ConnectionGUID: 7S99iHikR3SujsKGgB2Y2A== X-CSE-MsgGUID: ofPwEoN7TKKEgWzqx3mJuA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459644" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459644" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:15 -0700 X-CSE-ConnectionGUID: iR+QyiGCRIytcV+m4pEWSA== X-CSE-MsgGUID: QE08/gukToGml3C6lx7wnw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866092" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:14 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 10/16] drm/i915/dp_mst: Account for pixel replication for MST overhead with DSC Date: Mon, 21 Oct 2024 18:04:08 +0530 Message-ID: <20241021123414.3993899-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the extra pixels to the hactive while computing overhead with DSC. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +++++++++++++-- drivers/gpu/drm/i915/display/intel_vdsc.c | 23 +++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.h | 6 ++++++ 4 files changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 60baf4072dc9..e90a9dc1a8f5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -20,6 +20,7 @@ struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; struct intel_digital_port; +struct intel_display; struct intel_dp; struct intel_encoder; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1a2ff3e1cb68..72130c7748dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -92,20 +92,33 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, bool ssc, int dsc_slice_count, int bpp_x16) { + struct intel_display *display = to_intel_display(crtc_state); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; unsigned long flags = DRM_DP_BW_OVERHEAD_MST; int overhead; + int replicated_pixels = 0; flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0; flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; - if (dsc_slice_count) + if (dsc_slice_count) { flags |= DRM_DP_BW_OVERHEAD_DSC; + /* + * When hdisplay is not divisible by dsc_slice_count, extra pixels + * are added to last slice. Need to account for the extra overhead due + * to these extra pixels. + */ + replicated_pixels = + intel_dsc_get_replicated_pixels(display, + adjusted_mode->hdisplay, + dsc_slice_count, + crtc_state->output_format); + } overhead = drm_dp_bw_overhead(crtc_state->lane_count, - adjusted_mode->hdisplay, + adjusted_mode->hdisplay + replicated_pixels, dsc_slice_count, bpp_x16, flags); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 14cc1ef3641e..c3c6a4a4dafd 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1048,3 +1048,26 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, intel_vdsc_dump_state(p, indent, crtc_state); drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); } + +int intel_dsc_get_replicated_pixels(struct intel_display *display, + int mode_hdisplay, + int slice_count, + enum intel_output_format output_format) +{ + int replicated_pixels; + int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count); + + if (!HAS_PIXEL_REPLICATION(display)) + return 0; + + if (mode_hdisplay % slice_count == 0) + return 0; + + /* Odd slice width is not supported by YCbCr420 format */ + if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return 0; + + replicated_pixels = (slice_width * slice_count) - mode_hdisplay; + + return replicated_pixels; +} diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 290b2e9b3482..41b8b5c5866e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -10,9 +10,11 @@ struct drm_printer; +enum intel_output_format; enum transcoder; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_encoder; bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state); @@ -31,5 +33,9 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); +int intel_dsc_get_replicated_pixels(struct intel_display *display, + int mode_hdisplay, + int slice_count, + enum intel_output_format output_format); #endif /* __INTEL_VDSC_H__ */ From patchwork Mon Oct 21 12:34:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A133AD15D87 for ; Mon, 21 Oct 2024 12:32:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39D1B10E4D8; Mon, 21 Oct 2024 12:32:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="46459645" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459645" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:17 -0700 X-CSE-ConnectionGUID: NaTYrRLgRFSGHDkv5Xq4sQ== X-CSE-MsgGUID: 04kI5qczQ6qWly+R8w0+OQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866097" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:16 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 11/16] drm/i915/dp: Account for pixel replication for BW computation with DSC Date: Mon, 21 Oct 2024 18:04:09 +0530 Message-ID: <20241021123414.3993899-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Include the extra pixels added while computing bandwidth with DSC. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 53a437caacac..f35d6fc376c8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1940,6 +1940,23 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_cloc return available_bw > required_bw; } +static +u32 adjust_clock_for_extra_pixels(const struct drm_display_mode *adjusted_mode, + int extra_pixels) +{ + u32 clock = adjusted_mode->clock; + u16 htotal = adjusted_mode->htotal; + + if (!extra_pixels) + return clock; + /* + * clock = (htotal) * (vtotal) * refresh_rate + * adjusted_clock = (htotal + extra_pixels) * (vtotal) * refresh_rate + * = clock + (clock * extra_pixels / htotal) + */ + return clock + extra_pixels * (clock / htotal); +} + static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, @@ -1948,8 +1965,12 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, { const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int link_rate, lane_count; + u32 adjusted_clock; int i; + adjusted_clock = adjust_clock_for_extra_pixels(adjusted_mode, + pipe_config->dsc.replicated_pixels); + for (i = 0; i < intel_dp->num_common_rates; i++) { link_rate = intel_dp_common_rate(intel_dp, i); if (link_rate < limits->min_rate || link_rate > limits->max_rate) @@ -1959,7 +1980,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, lane_count <= limits->max_lane_count; lane_count <<= 1) { if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, - lane_count, adjusted_mode->clock, + lane_count, adjusted_clock, pipe_config->output_format, timeslots)) continue; From patchwork Mon Oct 21 12:34:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81AE2D15D88 for ; Mon, 21 Oct 2024 12:32:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B05810E4CF; Mon, 21 Oct 2024 12:32:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iWCjJLlW"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 464A410E4C8; Mon, 21 Oct 2024 12:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513939; x=1761049939; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZbPJcOveEqMemRpcqFimp/L0w96Wd3SN5h1DqKlOJf4=; b=iWCjJLlWVksXdTKDR7gx19AWUGychiK9UB2QgnEX7opOIehCF5J95ZjX INutjznz/EwrP4fXSWh1Saw9PsSGbtsPwAAIdwyBUnTIt8MDQiy0BWyqb AaMspoZ3ToIU6HfdteU2Rdx26Hw660e+v+NMev0WMMOaVArPpFuCzaBfd SIqSGrwSxCWOXl/Qffcu4qsA9oROXO37tb1+ogqY8oKXntOz+sNbA5zes jtjuzoQXuSGW2UPaSJLnRUPVwGh0OLMyuwxm29eVEUXWpCcoPuvoBICVA 6GT9WyT+R/3FZQKelTGZZE1QzE5aM77sUbtQFuIUIjb2AwLPl9HSp6aW2 Q==; X-CSE-ConnectionGUID: p+mfPnBYTRuzIxp0x6+4RQ== X-CSE-MsgGUID: JhEgeaKKTPiNnr5BibAJZA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459646" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459646" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:19 -0700 X-CSE-ConnectionGUID: 5e5+TdtqSkGJjhAS5VzcCA== X-CSE-MsgGUID: 1WQYr4QVS5ijKtgb5/VblA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866102" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:17 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 12/16] drm/i915/display: Account for pixel replication in pipe_src Date: Mon, 21 Oct 2024 18:04:10 +0530 Message-ID: <20241021123414.3993899-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With DSC pixel replication, extra pixels are added in the last slice of the last pipe. Due to this the total hactive gets increased by few pixels. Adjust the computation for pipe source width to account for pixel replication. These extra pixels will be take care by the Splitter logic in hardware. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1b772f58998e..de682fec45cd 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2514,6 +2514,22 @@ void intel_encoder_get_config(struct intel_encoder *encoder, intel_crtc_readout_derived_state(crtc_state); } +static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels) +{ + /* Account for Pixel replication: + * Pixel replication is required due to the rounding of slice_width (Hactive / slice_count). + * + * Splitter HW takes care of these by removing replicated pixels from the last pipe. + */ + + if (!replicated_pixels) + return width; + + width += replicated_pixels; + + return width; +} + static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) { int num_pipes = intel_crtc_num_joined_pipes(crtc_state); @@ -2522,7 +2538,9 @@ static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) if (num_pipes == 1) return; - width = drm_rect_width(&crtc_state->pipe_src); + width = intel_splitter_adjust_pipe_width(drm_rect_width(&crtc_state->pipe_src), + crtc_state->dsc.replicated_pixels); + height = drm_rect_height(&crtc_state->pipe_src); drm_rect_init(&crtc_state->pipe_src, 0, 0, From patchwork Mon Oct 21 12:34:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70B34D15D8B for ; Mon, 21 Oct 2024 12:32:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E625710E4DB; Mon, 21 Oct 2024 12:32:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WkeqnWMD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id D29A610E4D7; Mon, 21 Oct 2024 12:32:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513940; x=1761049940; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZsmxNmDbpDvQV2KaXYlDJAU2OycL3GGlOhKZk/LCFYg=; b=WkeqnWMD114aP+72NdO0x750QN3+mJqpcQXLj1D9CVWiRyXPkJJ7GDRQ /tFpLT/HiT+H8YsWM+clJlVvfZfCmKELBWcpP7E2yqQE2wbvjP8QbkM9G vD4RR6VOxJkjt0QybDeyy0wqfpvazFMlRCUJ4bHyYdcySXLHnG+99xzsi wq2i4QjxNfdnzdhOy+dFp3/bNc6GFnwqm6s96FzxQSTXU6oHS9Ml8bJr/ AP0qaBOWFryB8fu2kT6Ac2S4QzTH6EiKt6gYIV3uqzJETmdldCv8nw54g a8U+l1m6ihe1AvqJ30iz9Omx6jEOrri7MyBcdqwCHX0URxhp9PVhpQpVo Q==; X-CSE-ConnectionGUID: 7THw+o8oQxK40HlFAs1RdA== X-CSE-MsgGUID: oOBPNJz3QHCaE9iTy78Pcg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459647" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459647" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:20 -0700 X-CSE-ConnectionGUID: ROJr1j7hRuWbwq+mmvaYCA== X-CSE-MsgGUID: LcpmRYjeQKi/Y0m4PIjJ5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866108" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:19 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 13/16] drm/i915/dp: Enable DSC pixel replication Date: Mon, 21 Oct 2024 18:04:11 +0530 Message-ID: <20241021123414.3993899-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Allow DSC slice count that do not divide the hactive evenly by adding extra pixels (replicated pixels). Check if the pixel replication is supported and store the no. of replicated pixel count in crtc_state. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ drivers/gpu/drm/i915/display/intel_vdsc.c | 28 +++++++++++++++------ drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++ 5 files changed, 44 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f35d6fc376c8..433a629c2bae 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -992,9 +992,11 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, + enum intel_output_format output_format, int num_joined_pipes) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); + struct drm_i915_private *i915 = to_i915(display->drm); u8 min_slice_count, i; int max_slice_width; @@ -1047,7 +1049,11 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) continue; - if (mode_hdisplay % test_slice_count) + if (mode_hdisplay % test_slice_count && + !intel_dsc_can_use_pixel_replication(display, + mode_hdisplay, + test_slice_count, + output_format)) continue; if (min_slice_count <= test_slice_count) @@ -1474,6 +1480,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, intel_dp_dsc_get_slice_count(connector, target_clock, mode->hdisplay, + output_format, num_joined_pipes); } @@ -2366,6 +2373,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, int timeslots, bool compute_pipe_bpp) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct intel_connector *connector = @@ -2428,6 +2436,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, intel_dp_dsc_get_slice_count(connector, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, + pipe_config->output_format, num_joined_pipes); if (!dsc_dp_slice_count) { drm_dbg_kms(&dev_priv->drm, @@ -2437,6 +2446,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->dsc.slice_count = dsc_dp_slice_count; } + + pipe_config->dsc.replicated_pixels = + intel_dsc_get_replicated_pixels(display, + adjusted_mode->crtc_hdisplay, + pipe_config->dsc.slice_count, + pipe_config->output_format); + /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index e90a9dc1a8f5..7460675c16f6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -150,6 +150,7 @@ int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector int bpc); u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, + enum intel_output_format output_format, int num_joined_pipes); int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, struct intel_connector *connector, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 72130c7748dd..b5c72628d445 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -171,6 +171,7 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec return intel_dp_dsc_get_slice_count(connector, adjusted_mode->clock, adjusted_mode->hdisplay, + crtc_state->output_format, num_joined_pipes); } @@ -1537,6 +1538,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, intel_dp_dsc_get_slice_count(intel_connector, target_clock, mode->hdisplay, + INTEL_OUTPUT_FORMAT_RGB, num_joined_pipes); } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index c3c6a4a4dafd..c279f59fdda8 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1049,6 +1049,22 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); } +bool intel_dsc_can_use_pixel_replication(struct intel_display *display, + int mode_hdisplay, u8 slice_count, + enum intel_output_format output_format) +{ + int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count); + + if (!HAS_PIXEL_REPLICATION(display)) + return false; + + /* Odd slice width is not supported by YCbCr420 format */ + if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return false; + + return true; +} + int intel_dsc_get_replicated_pixels(struct intel_display *display, int mode_hdisplay, int slice_count, @@ -1057,14 +1073,10 @@ int intel_dsc_get_replicated_pixels(struct intel_display *display, int replicated_pixels; int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count); - if (!HAS_PIXEL_REPLICATION(display)) - return 0; - - if (mode_hdisplay % slice_count == 0) - return 0; - - /* Odd slice width is not supported by YCbCr420 format */ - if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + if (!intel_dsc_can_use_pixel_replication(display, + mode_hdisplay, + slice_count, + output_format)) return 0; replicated_pixels = (slice_width * slice_count) - mode_hdisplay; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 41b8b5c5866e..3611fc53840d 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -33,6 +33,9 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); +bool intel_dsc_can_use_pixel_replication(struct intel_display *display, + int mode_hdisplay, u8 slice_count, + enum intel_output_format output_format); int intel_dsc_get_replicated_pixels(struct intel_display *display, int mode_hdisplay, int slice_count, From patchwork Mon Oct 21 12:34:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20E7CD15D8D for ; Mon, 21 Oct 2024 12:32:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 437EE10E4D4; Mon, 21 Oct 2024 12:32:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="asdK0UPs"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6055710E4C8; Mon, 21 Oct 2024 12:32:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513942; x=1761049942; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FVFf5WVf9WLYyR0bGP5755zR/GpK/07AQJOOMrnRsYI=; b=asdK0UPs3orzGLaYXp+F7HldMF13DmRRL2YRYRu/X0SAqQbxRkcei25c 485v7OF7eGel7b1s0lFhOoISi7iUxmzn5R6li2F15wwmRr3rUWjCNDv3A TZJZRqFqNu5eukWTrXlDvc4fUm3jLcP3gOY1Z309Hf7P2oEAGlV7nitkl 3Bjd6HwNbPlWpmspiqKKh+dCQMXgtowOyiUWqAShfcnmyhj8RoqnYoDth H+uvN+J9r6Sssb1+cuMfRnQxOJ7R53xfA58RTyEk9GUgE5oISBvdgBSwa TMU5nJHelK4gJVabjDsgDeGYW/bdLwZD5UhBQkO1YK3VvNH3I9k5eaYv2 A==; X-CSE-ConnectionGUID: r/RFVT+RRRShGYtrjoN48w== X-CSE-MsgGUID: zFW8DDzJTNWeBFNYYQPZFw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459650" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459650" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:22 -0700 X-CSE-ConnectionGUID: PINBdPs4S8CNimkBoNDR1g== X-CSE-MsgGUID: RaXrAEG0Rdaz00H4ggJ26g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866112" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:21 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 14/16] drm/i915/dsc: Introduce odd pixel removal Date: Mon, 21 Oct 2024 18:04:12 +0530 Message-ID: <20241021123414.3993899-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With 3 DSC engines we can support 12 slices. With ultra joiner usecase while dividing the width into 12 slices, we might end up having odd number of pixels per pipe. As per Bspec, pipe src size should be even, so an extra pixel is added in each pipe. For Pipe A and C the odd pixel is added at the end of pipe and for Pipe B and D it is added at the beginning of the pipe. This extra pixel needs to be dropped in Splitter hardware. Introduce bits to account for odd pixel removal while programming DSS CTL. Add a new member in crtc state to track if we need to account for the odd pixel. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 9 +++++++++ drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 2 ++ 4 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index de682fec45cd..ac4a5809efd6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5762,6 +5762,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(dsc.dsc_split); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); PIPE_CONF_CHECK_I(dsc.replicated_pixels); + PIPE_CONF_CHECK_BOOL(dsc.has_odd_pixel); PIPE_CONF_CHECK_BOOL(splitter.enable); PIPE_CONF_CHECK_I(splitter.link_count); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 17554f52611c..92c362b9f63c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1235,6 +1235,7 @@ struct intel_crtc_state { /* Display Stream compression state */ struct { bool compression_enable; + bool has_odd_pixel; int dsc_split; /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index c279f59fdda8..d3d36cb9859c 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -806,6 +806,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } + if (crtc_state->dsc.has_odd_pixel) { + dss_ctl2_val |= ODD_PIXEL_REMOVAL; + if (crtc->pipe == PIPE_A || crtc->pipe == PIPE_C) + dss_ctl2_val |= ODD_PIXEL_REMOVAL_CONFIG_EOL; + } + if (crtc_state->dsc.replicated_pixels) dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.replicated_pixels); @@ -1019,6 +1025,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.dsc_split = 0; } + if (dss_ctl2 & ODD_PIXEL_REMOVAL) + crtc_state->dsc.has_odd_pixel = true; + if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) crtc_state->dsc.replicated_pixels = dss_ctl3 & DSC_PIXEL_REPLICATION_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index f07fad6239bc..9c4cf80c2064 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -24,6 +24,8 @@ #define VDSC0_ENABLE REG_BIT(31) #define VDSC2_ENABLE REG_BIT(30) #define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) +#define ODD_PIXEL_REMOVAL REG_BIT(18) +#define ODD_PIXEL_REMOVAL_CONFIG_EOL REG_BIT(17) #define VDSC1_ENABLE REG_BIT(15) #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) From patchwork Mon Oct 21 12:34:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5150D15D89 for ; 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X-CSE-ConnectionGUID: G2J3fYlMTUevkUl3RC36SQ== X-CSE-MsgGUID: zuhhP8qaRiSP+kkJhp79vA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459655" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459655" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:23 -0700 X-CSE-ConnectionGUID: ujE7TWmWTMmw47pbmyHVmw== X-CSE-MsgGUID: uJhS6RScQJiBFynbrXebWw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866118" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:22 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 15/16] drm/i915/display: Adjust Pipe SRC Width for Odd Pixels Date: Mon, 21 Oct 2024 18:04:13 +0530 Message-ID: <20241021123414.3993899-16-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enhance the `intel_splitter_adjust_pipe_width` helper to account for both pixel replication and odd pixels. When the display width is divided among multiple pipes, extra pixels can make the pipe source width odd. Since hardware expects an even width, an extra pixel is added to each pipe to ensure even width. The splitter hardware will remove these extra pixels. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ac4a5809efd6..5fe96c53d525 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2514,12 +2514,18 @@ void intel_encoder_get_config(struct intel_encoder *encoder, intel_crtc_readout_derived_state(crtc_state); } -static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels) +static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels, + bool has_odd_pixel, int num_pipes) { - /* Account for Pixel replication: + /* Account for Pixel replication + Odd pixel: * Pixel replication is required due to the rounding of slice_width (Hactive / slice_count). * - * Splitter HW takes care of these by removing replicated pixels from the last pipe. + * These extra pixels when added to the pipe source width, can make the pipe source width + * odd. Since HW expects the pipe source width to be even, therefore one extra pixel needs + * to be added to the pipe source width to make it even. + * + * Splitter HW takes care of these by removing odd pixel from each pipe and + * replicated pixels from the last pipe. */ if (!replicated_pixels) @@ -2527,7 +2533,11 @@ static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels) width += replicated_pixels; - return width; + if (!has_odd_pixel) + return width; + + /* Account for one extra pixel for each pipe */ + return width + num_pipes; } static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) @@ -2539,7 +2549,9 @@ static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) return; width = intel_splitter_adjust_pipe_width(drm_rect_width(&crtc_state->pipe_src), - crtc_state->dsc.replicated_pixels); + crtc_state->dsc.replicated_pixels, + crtc_state->dsc.has_odd_pixel, + num_pipes); height = drm_rect_height(&crtc_state->pipe_src); From patchwork Mon Oct 21 12:34:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13844053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52A79D15D8A for ; Mon, 21 Oct 2024 12:32:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C1FDB10E4DA; Mon, 21 Oct 2024 12:32:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NrZpJZ/h"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7269210E4DD; Mon, 21 Oct 2024 12:32:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729513945; x=1761049945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3C62c2Jg30kJUc0SGSmKmo0GDvceiNoxX9rFpBg5Lf0=; b=NrZpJZ/hzNSAv6b/D2QW0ZDjuPzRbQolozBhVg2FJ/Q0sun2YstiZw3z VbSO4unSskbVDFn8wdWCbEF6foU8G0zhQj6UNltrilfXP4yYV0OZyjZSH XF0NsZcXA0TBGMvD8WJrcNzDkl/gEdK8BqntyTCHq5VXTUFdGSon3kkXv gTSXRsbKZ6tOBmx6pdR6wlUR2d/NnRp/Pkg6pjukzeIbm8TRNAvyuhIdk Wo0XDf7mHmcKRPs3Xk/cl17rASHYLpc3peLHM6pw0EfwWGVkpU6XuKWik uQRfwuQqENWsL8j3HsJZSI0Cgvq5uKGrmUKnydkhK5QHilSciLvuTXMY/ w==; X-CSE-ConnectionGUID: d7FXaq6VSJmygPKqyW9Q8w== X-CSE-MsgGUID: ZAgm/t3dRFWn7kGartplaQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="46459657" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="46459657" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:25 -0700 X-CSE-ConnectionGUID: BzzPHuVQR56MTOApLKiuRA== X-CSE-MsgGUID: Jm1AWrebQXmlINmMJrS7ZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,220,1725346800"; d="scan'208";a="79866123" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 05:32:24 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 16/16] drm/i915/dp: Add Check for Odd Pixel Requirement Date: Mon, 21 Oct 2024 18:04:14 +0530 Message-ID: <20241021123414.3993899-17-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> References: <20241021123414.3993899-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Check if Odd pixel is required during DSC compute config and update the crtc_state to track the presence of odd pixels. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 433a629c2bae..44e7069c4d27 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2366,6 +2366,14 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, return 0; } +static bool intel_dp_dsc_needs_odd_pixel(int hdisplay, int replicated_pixels, int num_pipes) +{ + if (!replicated_pixels || num_pipes == 1) + return false; + + return ((hdisplay + replicated_pixels) / num_pipes) % 2; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -2452,6 +2460,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_hdisplay, pipe_config->dsc.slice_count, pipe_config->output_format); + pipe_config->dsc.has_odd_pixel = + intel_dp_dsc_needs_odd_pixel(adjusted_mode->crtc_hdisplay, + pipe_config->dsc.replicated_pixels, + num_joined_pipes); /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate