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^ kvm-unit-tests/lib/asm/processor.h:162:14: note: use constraint modifier "w" "rdvl %0, #8" ^~ %w0 1 error generated. Fixes: d47d370c8f ("arm: Add test for FPU/SIMD context save/restore") Signed-off-by: Raghavendra Rao Ananta --- lib/arm64/asm/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h index b28d41fd..e261e74d 100644 --- a/lib/arm64/asm/processor.h +++ b/lib/arm64/asm/processor.h @@ -159,7 +159,7 @@ static inline int sve_vl(void) int vl; asm volatile(".arch_extension sve\n" - "rdvl %0, #8" + "rdvl %w0, #8" : "=r" (vl)); return vl; From patchwork Tue Oct 22 00:47:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 13844934 Received: from mail-io1-f73.google.com (mail-io1-f73.google.com [209.85.166.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C5083CD6 for ; Tue, 22 Oct 2024 00:47:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 21 Oct 2024 17:47:18 -0700 (PDT) Date: Tue, 22 Oct 2024 00:47:09 +0000 In-Reply-To: <20241022004710.1888067-1-rananta@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241022004710.1888067-1-rananta@google.com> X-Mailer: git-send-email 2.47.0.105.g07ac214952-goog Message-ID: <20241022004710.1888067-3-rananta@google.com> Subject: [kvm-unit-tests PATCH 2/3] arm: fpu: Convert 'q' registers to 'v' to satisfy clang From: Raghavendra Rao Ananta To: Subhasish Ghosh , Joey Gouly , Andrew Jones Cc: Oliver Upton , Marc Zyngier , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Clang doesn't seem to support 'q' register notation in the clobbered list, and hence throws the following error: arm/fpu.c:235:3: error: unknown register name 'q0' in asm fpu_reg_read(outdata); ^ arm/fpu.c:59:10: note: expanded from macro 'fpu_reg_read' : "q0", "q1", "q2", "q3", \ ^ arm/fpu.c:281:3: error: unknown register name 'q0' in asm fpu_reg_write(*indata); ^ arm/fpu.c:92:10: note: expanded from macro 'fpu_reg_write' : "q0", "q1", "q2", "q3", \ ^ 2 errors generated. Hence, replace 'q' with 'v' registers for the clobbered list. Fixes: d47d370c8f ("arm: Add test for FPU/SIMD context save/restore") Signed-off-by: Raghavendra Rao Ananta --- arm/fpu.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arm/fpu.c b/arm/fpu.c index edbd9a94..587b6ea3 100644 --- a/arm/fpu.c +++ b/arm/fpu.c @@ -56,16 +56,16 @@ static inline bool arch_collect_entropy(uint64_t *random) "stp q30, q31, [%0], #32\n\t" \ : "=r" (__val) \ : \ - : "q0", "q1", "q2", "q3", \ - "q4", "q5", "q6", "q7", \ - "q8", "q9", "q10", "q11", \ - "q12", "q13", "q14", \ - "q15", "q16", "q17", \ - "q18", "q19", "q20", \ - "q21", "q22", "q23", \ - "q24", "q25", "q26", \ - "q27", "q28", "q29", \ - "q30", "q31", "memory"); \ + : "v0", "v1", "v2", "v3", \ + "v4", "v5", "v6", "v7", \ + "v8", "v9", "v10", "v11", \ + "v12", "v13", "v14", \ + "v15", "v16", "v17", \ + "v18", "v19", "v20", \ + "v21", "v22", "v23", \ + "v24", "v25", "v26", \ + "v27", "v28", "v29", \ + "v30", "v31", "memory"); \ }) #define fpu_reg_write(val) \ @@ -89,16 +89,16 @@ do { \ "ldp q30, q31, [%0], #32\n\t" \ : \ : "r" (__val) \ - : "q0", "q1", "q2", "q3", \ - "q4", "q5", "q6", "q7", \ - "q8", "q9", "q10", "q11", \ - "q12", "q13", "q14", \ - "q15", "q16", "q17", \ - "q18", "q19", "q20", \ - "q21", "q22", "q23", \ - "q24", "q25", "q26", \ - "q27", "q28", "q29", \ - "q30", "q31", "memory"); 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AJvYcCW+j/G7TUOpNcKmWhEP1+0qe3t3UbF3pft9fdrHqNr+tj0KjY0vXkp9gghOhXxGTItgCAg=@vger.kernel.org X-Gm-Message-State: AOJu0Yydt32HS7MXfS1nXN8IqZul84Ay9tFbCtI53DojByqu/jI2F8P8 9vOHOfdvNTfJtdNlfPfYKzGeL18SUFDYQOLh5jC+e4DjrvaF/OKeItdYFbgOtxaNuqsN0FHQ5fw wuvgYqw== X-Google-Smtp-Source: AGHT+IFiyt/4iIInAWKLwhqunyPq9QHonJj64kutF9hny1NRpAVPZ5zeWGMGBu5qDtED4tv1AgjC9hWx+3+e X-Received: from rananta-linux.c.googlers.com ([fda3:e722:ac3:cc00:11b:3898:ac11:fac1]) (user=rananta job=sendgmr) by 2002:a05:690c:3582:b0:6e3:2f0b:b595 with SMTP id 00721157ae682-6e5bfd58c16mr738297b3.5.1729558039164; Mon, 21 Oct 2024 17:47:19 -0700 (PDT) Date: Tue, 22 Oct 2024 00:47:10 +0000 In-Reply-To: <20241022004710.1888067-1-rananta@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241022004710.1888067-1-rananta@google.com> X-Mailer: git-send-email 2.47.0.105.g07ac214952-goog Message-ID: <20241022004710.1888067-4-rananta@google.com> Subject: [kvm-unit-tests PATCH 3/3] arm: fpu: Fix the input/output args for inline asm in fpu.c From: Raghavendra Rao Ananta To: Subhasish Ghosh , Joey Gouly , Andrew Jones Cc: Oliver Upton , Marc Zyngier , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org The macros fpu_reg_{read,write} post-increment the '__val' pointer register as a part of 'stp' and 'ldp' instructions. As a result, mark it with "+r" for the compiler to treat it as read-write operand. On the contrary, sve_reg_read() never updates the value of the pointer/register. Hence, mark this as "r" for the compiler to treat it as read-only operand. Without these adjustments, the compiler can potentially perform optimizations over the registers holding the pointers that could lead to data aborts. Fixes: d47d370c8f ("arm: Add test for FPU/SIMD context save/restore") Signed-off-by: Raghavendra Rao Ananta --- arm/fpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arm/fpu.c b/arm/fpu.c index 587b6ea3..6b0411d3 100644 --- a/arm/fpu.c +++ b/arm/fpu.c @@ -54,7 +54,7 @@ static inline bool arch_collect_entropy(uint64_t *random) "stp q26, q27, [%0], #32\n\t" \ "stp q28, q29, [%0], #32\n\t" \ "stp q30, q31, [%0], #32\n\t" \ - : "=r" (__val) \ + : "+r" (__val) \ : \ : "v0", "v1", "v2", "v3", \ "v4", "v5", "v6", "v7", \ @@ -87,8 +87,8 @@ do { \ "ldp q26, q27, [%0], #32\n\t" \ "ldp q28, q29, [%0], #32\n\t" \ "ldp q30, q31, [%0], #32\n\t" \ + : "+r" (__val) \ : \ - : "r" (__val) \ : "v0", "v1", "v2", "v3", \ "v4", "v5", "v6", "v7", \ "v8", "v9", "v10", "v11", \ @@ -138,8 +138,8 @@ do { \ "str z29, [%0, #29, MUL VL]\n" \ "str z30, [%0, #30, MUL VL]\n" \ "str z31, [%0, #31, MUL VL]\n" \ - : "=r" (__val) \ : \ + : "r" (__val) \ : "z0", "z1", "z2", "z3", \ "z4", "z5", "z6", "z7", \ "z8", "z9", "z10", "z11", \