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Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v2 1/5] x86/cpufeatures: Rename X86_FEATURE_FAST_CPPC to have AMD prefix Date: Mon, 21 Oct 2024 22:46:04 -0500 Message-ID: <20241022034608.32396-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022034608.32396-1-mario.limonciello@amd.com> References: <20241022034608.32396-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B078:EE_|LV2PR12MB5989:EE_ X-MS-Office365-Filtering-Correlation-Id: f91ee3ca-b04d-42aa-787d-08dcf24c2980 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: UTvsceMNVyKKVDqkcP7lP6twZnOyIosEhwoGhGgokGerqeNQPR3ag/Umnugg2y0SeZ+NcQ0JevIcmxTWXXoxwMfZDbC0B+VHhu1b/ipUXofmNvFNj2cWt8u86C3YB5pIYmDyoDtPDYY7XYuVDyZKomFG4hbiHufZds2sD1zIDXUoBQno3vIzxxQlE3wFtcm4xLit36m/aX0bf1kE4tUkbquAnqSB9gN+KZWTpvWCr1W/GTuA+qLJM38cZf0fXmiF5XmCHnaqO8+S8+sdAPx0vrj+FbjAHtnKjqZmOIN/QJsXh5qe01xFMcZO5ufaSJRB1kOb+leKihlRnZ7LSqnIMBDRaIoP6z6H3gkSpg1+WrqgHW42nTR7idaV13Dbn5UvJdQYCjyCFmPhwryTjBLNMFwYuIFES5qL9+VHP7OFELMznJ/QRhv3OKgMUgnN9PthdgGx0w+7CEuJBKf6lETRADDixQ0LNF+JCfccQYlog61e6ru+phY5HV+47wPyeyHtwik/wUu39jukoORN2El2eqeczkL5P46pUjAq1n/YCEDiuu/ZteqdUzxpj06qUn1bxv9eWheX5kbA2/MCdf9NZOexipImLRuUiHigDvb/rrxR97VrDlIiK+YF5+8VN0l+7fQJihTOR5bF6spgFS3dH+coqQsy9/79K/Jogl9rLNZcM/nnSM1kYTjXRDDq4o+mo15e8oFO7+jZ8CkTo3pG+rs4yNx8v8Ymt9jnpU6Fln8D814x6pr+DwsYPaORRbQ2JIRm6gQgO4pl00OJeEL3rEw32vy7/ecDrrRAcc/wdT+F1pn/+uqTdNTKKO88cC8SHvc5jiqaEW0rf8DxiUAIFiwgDMAmixl8BqxeWDGih2JoK83mKCLxf5DgzSNW16BSFi7b+ZPeIiHZAVd01N5plU8ppdYE9YHJhQ0QMnUqWl1Adpw9gd0wbP6kV3fmuc2efdcxi0Kkw2FVQgdjVC0OjUnMhRQIszzJyfJ00J4NyuB5nXasL3gJtT9tpSn+hfYcybCy4mILOd0uj9JKIxJPc4q6lHhWHoooMgXiggnr4EvMKKhYiqYzv/4Iw5TVJFpbeG9wBlj3i5ivj1rZNNmdX4ZN/05LcCZCXXeMsEY3qM7fTzLpPo+Cmmxx6Mzn3V8ayNcXfeEpzAJOahRR2vqmm4ctCz9Ovnx4+KEe0xsfZEzPQgDSxNCU13Pgb1Goj4nQL5MDw0gK8P3+TmrTtlfvKctPsH9gCyV1P02P1R1klOjd4cnr9jp/RfjdUyt4E4HLeuVXpO09VzGc76iWiX83eM0/MhcyvJx5Rt01HniquEpuxU2xLW2zvBV1bH1CiIBcJ3sgfJfe1XWPJ48TmsB75f75R5NSVTBy7yUEAZMtI7KEaNZOBSY6IgVWz8D+LX5WgMDN11upYR92xaTGj8gPpw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 03:46:50.6708 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f91ee3ca-b04d-42aa-787d-08dcf24c2980 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B078.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5989 This feature is an AMD unique feature of some processors, so put AMD into the name. Signed-off-by: Mario Limonciello --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 2 +- drivers/cpufreq/amd-pstate.c | 2 +- tools/arch/x86/include/asm/cpufeatures.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 913fd3a7bac65..aa63437a677c0 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -473,7 +473,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ -#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index c84c30188fdf2..1db2bb81a3847 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,7 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, - { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, + { X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index b63863f77c677..717b4cf4d9c4c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -847,7 +847,7 @@ static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) transition_delay_ns = cppc_get_transition_latency(cpu); if (transition_delay_ns == CPUFREQ_ETERNAL) { - if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC)) + if (cpu_feature_enabled(X86_FEATURE_AMD_FAST_CPPC)) return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; else return AMD_PSTATE_TRANSITION_DELAY; diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index dd4682857c120..23698d0f4bb47 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -472,7 +472,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ -#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ /* * BUG word(s) From patchwork Tue Oct 22 03:46:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13845071 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2044.outbound.protection.outlook.com [40.107.94.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5292F9463; 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Mon, 21 Oct 2024 22:46:50 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . 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Bit 30 indicates the heterogeneous core topology feature, if the bit set, it means not all instances at the current hierarchical level have the same core topology. This is described in the AMD64 Architecture Programmers Manual Volume 2 and 3, doc ID #25493 and #25494. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v1->v2: * Drop tags * Squash original attempt and new changes with feedback together --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index aa63437a677c0..51b38bc667960 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -474,6 +474,7 @@ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 1db2bb81a3847..307a917415343 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -52,6 +52,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, + { X86_FEATURE_AMD_HETEROGENEOUS_CORES, CPUID_EAX, 30, 0x80000026, 0 }, { 0, 0, 0, 0, 0 } }; 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This flag is beneficial for processors with one or more CCDs and relies on x86_sched_itmt_flags(). Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- arch/x86/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 766f092dab80b..b5a8f0891135b 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -497,8 +497,9 @@ static int x86_cluster_flags(void) static int x86_die_flags(void) { - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return x86_sched_itmt_flags(); + if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) || + cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) + return x86_sched_itmt_flags(); return 0; } From patchwork Tue Oct 22 03:46:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13845074 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2082.outbound.protection.outlook.com [40.107.223.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E2C1F5FD; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B073.mail.protection.outlook.com (10.167.243.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Tue, 22 Oct 2024 03:46:55 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 21 Oct 2024 22:46:52 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v2 4/5] x86/cpu: Add CPU type to struct cpuinfo_topology Date: Mon, 21 Oct 2024 22:46:07 -0500 Message-ID: <20241022034608.32396-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022034608.32396-1-mario.limonciello@amd.com> References: <20241022034608.32396-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B073:EE_|DS7PR12MB8370:EE_ X-MS-Office365-Filtering-Correlation-Id: bf977f1e-f876-4cbe-1082-08dcf24c2c1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|36860700013|30052699003|376014|1800799024; X-Microsoft-Antispam-Message-Info: yOyan6tA9o577vbqmzfcCtdtYVHh9aSkaJU6hAZ8zkx7ON3Dqo0/7EgqSXJPb7wCU3gITcSBZIQLU1Wl0uLxFPhiRA8i4jwVbOktRBIZZYnQ/N1VhZCO/7sA5WEE02y30Qu5SPRhZCedhVsjFMO1nHkVKVPtaNRSnn+W8TussIr3+nYcJKaInwrABW4Hnvx1k3vR/Csu4gJz1+guQT/3zwLsOeBhcf7y7wD+hs0p4mrXZXIG8p2PBCGM+sKKVLS2XTrJiO7Eka+PfqXp6eU94TcvKapdoga4YYatidWtDApYVye+pemcVMq17mpdHe4nXoy4pi2XELhg9LU9hHtODq+6GfnHE1/hSmB7VEsUmH1I4fdzstNwynhU7PeECdEw3N8TgjMLkcZSOblstYw24qNdYRjexjn9ioaPoe9pNih7IPHOlXahiHxWqS9EootRl7V2r4C6mTQ8lrR99AAvOzKnNfz0X5PmShKmkyX0advdcXqdHfxTE7vAIU1zvupZueLKDCHaZuTjjhRjW6Tidq4lksR+KyHAgtgr1kvnJCFHnqMjswW5eUYRM4JUORQCxm2nYJvBiU+tp/TgVokz1f9ukDguW62i6VTfyk0CM/HapeKeUktptpvQbT47uQK8oPfC9GDczoORwAu7WVfdQaLBKMH/Gdy8e7LQw81h90uJEWufEL7Ho7/Wu6voU1xfrIKFzMW03M9V7TqGvrLt+r00LdnVCHdpAuDSFCNQmw/m5QHKRQJSKgSgkaGiuesRsWiO+B9+7FAsi3tGEqeTOUA1Tzy5zdH0yAbKf55L1nIW9hAAOmwrR6C7vdDnZpIJbZlr/vN+fbTznoyaYuZ4tcP4RfI4h6AzNa69/O24s+y39eJ+OUrw1o1O5D57HDXZn3IQX7IPPVsoWqCWV++0WFd7j7JIrVZDzumRyM0vLuolzliSGx0C11CBV5gc7GcuEdoAHf05M/qC5XOtzfo0R7Myn6k2xJfLebRkW+GzwtSgw5jKaXPupG0wqxwG2xEhwgZvJDh1r9irW2lS4IJJfiqGjwIZ+YR6NgzSI1XUn9Nk9BQLZ//8YR0RHDM2XP6MfRnIM5QhGc0rr1jOgOrCTAwsMCXS3MvtsspiBmNYs3NjJXtKybSFq00ThC9DopeTQ3B/kO9Dfqgn7MX+7bbGxkgWU0tVso2j07SXiU8M37JSpJ/wfw37RmNhpiT/N41FuflfjmeLjfR0BiSmMcpXHOC6Gv7pIyd/f2I2tVWn+QAwq2Y3KxNqa7Zv6LoIDkxi1dOy48iOqIqeEmWmBlzN8fcEKIH967YPb7OsYSLg1hZ32LFe3EgtKFVKui6vPbXEoWfyt2V3Chvh3tlN8VS/ooiKa1d2xrDb6M/lHfQf3laAdIuFbmfdRL9Z+cvmZYuwS+/SbbQ0dXjFETfB/2zagA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(36860700013)(30052699003)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 03:46:55.0484 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf977f1e-f876-4cbe-1082-08dcf24c2c1a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8370 From: Pawan Gupta Sometimes it is required to take actions based on if a CPU is a performance or efficiency core. As an example, intel_pstate driver uses the Intel core-type to determine CPU scaling. Also, some CPU vulnerabilities only affect a specific CPU type, like RFDS only affects Intel Atom. Hybrid systems that have variants P+E, P-only(Core) and E-only(Atom), it is not straightforward to identify which variant is affected by a type specific vulnerability. Such processors do have CPUID field that can uniquely identify them. Like, P+E, P-only and E-only enumerates CPUID.1A.CORE_TYPE identification, while P+E additionally enumerates CPUID.7.HYBRID. Based on this information, it is possible for boot CPU to identify if a system has mixed CPU types. Add a new field hw_cpu_type to struct cpuinfo_topology that stores the hardware specific CPU type. This saves the overhead of IPIs to get the CPU type of a different CPU. CPU type is populated early in the boot process, before vulnerabilities are enumerated. Signed-off-by: Pawan Gupta Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- * Take this patch from Pawan's series and fix up for feedback left on it. * Add in AMD case as well --- arch/x86/include/asm/cpu.h | 19 +++++++++++++++++++ arch/x86/include/asm/processor.h | 18 ++++++++++++++++++ arch/x86/include/asm/topology.h | 8 ++++++++ arch/x86/kernel/cpu/amd.c | 14 ++++++++++++++ arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/intel.c | 18 ++++++++++++++++++ arch/x86/kernel/cpu/topology_amd.c | 3 +++ arch/x86/kernel/cpu/topology_common.c | 13 +++++++++++++ 8 files changed, 94 insertions(+) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 98eced5084ca7..28bb177241131 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -53,6 +53,8 @@ static inline void bus_lock_init(void) {} #ifdef CONFIG_CPU_SUP_INTEL u8 get_this_hybrid_cpu_type(void); u32 get_this_hybrid_cpu_native_id(void); +u32 intel_native_model_id(struct cpuinfo_x86 *c); +enum x86_topology_cpu_type intel_cpu_type(struct cpuinfo_x86 *c); #else static inline u8 get_this_hybrid_cpu_type(void) { @@ -63,6 +65,23 @@ static inline u32 get_this_hybrid_cpu_native_id(void) { return 0; } + +static u32 intel_native_model_id(struct cpuinfo_x86 *c) +{ + return 0; +} +static enum x86_topology_cpu_type intel_cpu_type(struct cpuinfo_x86 *c) +{ + return TOPO_CPU_TYPE_UNKNOWN; +} +#endif +#ifdef CONFIG_CPU_SUP_AMD +enum x86_topology_cpu_type amd_cpu_type(struct cpuinfo_x86 *c); +#else +static inline enum x86_topology_cpu_type amd_cpu_type(struct cpuinfo_x86 *c) +{ + return TOPO_CPU_TYPE_UNKNOWN; +} #endif #ifdef CONFIG_IA32_FEAT_CTL void init_ia32_feat_ctl(struct cpuinfo_x86 *c); diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4a686f0e5dbf6..872e5a429d00d 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -105,6 +105,24 @@ struct cpuinfo_topology { // Cache level topology IDs u32 llc_id; u32 l2c_id; + + // Hardware defined CPU-type + union { + u32 cpu_type; + struct { + // CPUID.1A.EAX[23-0] + u32 intel_native_model_id:24; + // CPUID.1A.EAX[31-24] + u32 intel_type:8; + }; + struct { + // CPUID 0x80000026.EBX + u32 amd_num_processors :16, + amd_power_efficiency_ranking :8, + amd_native_model_id :4, + amd_type :4; + }; + }; }; struct cpuinfo_x86 { diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index aef70336d6247..5b344ff81219d 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -114,6 +114,12 @@ enum x86_topology_domains { TOPO_MAX_DOMAIN, }; +enum x86_topology_cpu_type { + TOPO_CPU_TYPE_PERFORMANCE, + TOPO_CPU_TYPE_EFFICIENCY, + TOPO_CPU_TYPE_UNKNOWN, +}; + struct x86_topology_system { unsigned int dom_shifts[TOPO_MAX_DOMAIN]; unsigned int dom_size[TOPO_MAX_DOMAIN]; @@ -149,6 +155,8 @@ extern unsigned int __max_threads_per_core; extern unsigned int __num_threads_per_package; extern unsigned int __num_cores_per_package; +enum x86_topology_cpu_type topology_cpu_type(struct cpuinfo_x86 *c); + static inline unsigned int topology_max_packages(void) { return __max_logical_packages; diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index fab5caec0b72e..779073e5a6468 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,9 @@ #include "cpu.h" +#define TOPO_HW_CPU_TYPE_AMD_PERFORMANCE 0 +#define TOPO_HW_CPU_TYPE_AMD_EFFICIENCY 1 + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1205,3 +1208,14 @@ void amd_check_microcode(void) if (cpu_feature_enabled(X86_FEATURE_ZEN2)) on_each_cpu(zenbleed_check_cpu, NULL, 1); } + +enum x86_topology_cpu_type amd_cpu_type(struct cpuinfo_x86 *c) +{ + switch (c->topo.amd_type) { + case TOPO_HW_CPU_TYPE_AMD_PERFORMANCE: + return TOPO_CPU_TYPE_PERFORMANCE; + case TOPO_HW_CPU_TYPE_AMD_EFFICIENCY: + return TOPO_CPU_TYPE_EFFICIENCY; + } + return TOPO_CPU_TYPE_UNKNOWN; +} diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 3baf3e4358347..c3361e496df99 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -22,6 +22,7 @@ static int cpu_debug_show(struct seq_file *m, void *p) seq_printf(m, "die_id: %u\n", c->topo.die_id); seq_printf(m, "cu_id: %u\n", c->topo.cu_id); seq_printf(m, "core_id: %u\n", c->topo.core_id); + seq_printf(m, "cpu_type: %u\n", topology_cpu_type(c)); seq_printf(m, "logical_pkg_id: %u\n", c->topo.logical_pkg_id); seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); seq_printf(m, "llc_id: %u\n", c->topo.llc_id); diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index d1de300af1737..8887b5ed1fbca 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -878,6 +878,8 @@ static const struct cpu_dev intel_cpu_dev = { cpu_dev_register(intel_cpu_dev); #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 +#define TOPO_HW_CPU_TYPE_INTEL_ATOM 0x20 +#define TOPO_HW_CPU_TYPE_INTEL_CORE 0x40 /** * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU @@ -907,3 +909,19 @@ u32 get_this_hybrid_cpu_native_id(void) return cpuid_eax(0x0000001a) & (BIT_ULL(X86_HYBRID_CPU_TYPE_ID_SHIFT) - 1); } + +u32 intel_native_model_id(struct cpuinfo_x86 *c) +{ + return c->topo.intel_native_model_id; +} + +enum x86_topology_cpu_type intel_cpu_type(struct cpuinfo_x86 *c) +{ + switch (c->topo.intel_type) { + case TOPO_HW_CPU_TYPE_INTEL_ATOM: + return TOPO_CPU_TYPE_EFFICIENCY; + case TOPO_HW_CPU_TYPE_INTEL_CORE: + return TOPO_CPU_TYPE_PERFORMANCE; + } + return TOPO_CPU_TYPE_UNKNOWN; +} diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c index 7d476fa697ca5..03b3c9c3a45e2 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -182,6 +182,9 @@ static void parse_topology_amd(struct topo_scan *tscan) if (cpu_feature_enabled(X86_FEATURE_TOPOEXT)) has_topoext = cpu_parse_topology_ext(tscan); + if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) + tscan->c->topo.cpu_type = cpuid_ebx(0x80000026); + if (!has_topoext && !parse_8000_0008(tscan)) return; diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index 9a6069e7133c9..04b012dffa473 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -27,6 +27,16 @@ void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom, } } +enum x86_topology_cpu_type topology_cpu_type(struct cpuinfo_x86 *c) +{ + if (c->x86_vendor == X86_VENDOR_INTEL) + return intel_cpu_type(c); + if (c->x86_vendor == X86_VENDOR_AMD) + return amd_cpu_type(c); + + return TOPO_CPU_TYPE_UNKNOWN; +} + static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c) { struct { @@ -87,6 +97,7 @@ static void parse_topology(struct topo_scan *tscan, bool early) .cu_id = 0xff, .llc_id = BAD_APICID, .l2c_id = BAD_APICID, + .cpu_type = TOPO_CPU_TYPE_UNKNOWN, }; struct cpuinfo_x86 *c = tscan->c; struct { @@ -132,6 +143,8 @@ static void parse_topology(struct topo_scan *tscan, bool early) case X86_VENDOR_INTEL: if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) parse_legacy(tscan); + if (c->cpuid_level >= 0x1a) + c->topo.cpu_type = cpuid_eax(0x1a); break; case X86_VENDOR_HYGON: if (IS_ENABLED(CONFIG_CPU_SUP_HYGON)) From patchwork Tue Oct 22 03:46:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13845073 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2077.outbound.protection.outlook.com [40.107.102.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8355770FD; 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Mon, 21 Oct 2024 22:46:54 -0500 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v2 5/5] x86/amd: Use heterogeneous core topology for identifying boost numerator Date: Mon, 21 Oct 2024 22:46:08 -0500 Message-ID: <20241022034608.32396-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241022034608.32396-1-mario.limonciello@amd.com> References: <20241022034608.32396-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|SA1PR12MB7365:EE_ X-MS-Office365-Filtering-Correlation-Id: 4da1fa2d-03b8-455c-f4e1-08dcf24c2c9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: fopKHDYmT5F8gFpeEHL2P3t3QQN9B0mZy4qh0FXlzdGz5yhSu71Dn1yqtYXucarhfFihSW8lB27JwJxviyoG9PZkA35WGU7q97nP3lPz639QBZ22w7kFThPK1FDKJs9zbp2KxoTDANb8rAzhqtFIS1lNDLoXp5mugHsBVQshQHIVJ1VeRtENVEY53AH9JKu28PW3KvPfFzDom7yHEvazmYTZbiBcFYV3bUf/NXdLgCkqEhkoPoFqf8SpIQKWp0vGnS7HgZyG/wxl0pm8W8sWs3VFoLSBtqXC/sj0zEIbF0l4rTBTgVrIFFs+MVC/xXAYOl6gYxIt0T36Q8k+lA3y2J2uleXs6/kj7CQUXl3bWLjIJhRbio0o/60sFTJYWBSW3gdAfGvDXnVmAVXWpA/psfCXjM22m3liGpl0iXLNgPoudOzvlC7i5QXYpVno8mkeKDU8z9hAZFv8dHm2/9A6G1rfmnPFdGwmJYHOrIMTSh3owmmOxRX2Ckr9jAcnulqjuHm+YewCsmr70uJd4MMkMK2njei8aT75mrRTXsADb6umJofPPS97arbf+YWRlQ0o6xx/v/4GwTyFrxn+oaoSod5H6lzFHFkQ2hjn+rc+wsDw8syiQ2i7Hi7ER6Qc4tWKitzGSSiLbg+gZfeNqxk3R+fNeTWTIGB08z1Eswgai4XFCYOqWrnQ2cRbb8GxuU2/uFwVVvqTZVGrRSu9k4r1d8Mku/WPRXVOjA8lmU5YnzwoKhS93FwSCNgyr+n5xgh0xoEaTbe5pdXTfwiiIfw7f7wc9+JzvxdHUk2CpxuJfR6GZlmMVOvQ31Dj7yMtG4PMfxUxV+jKyCEQVyop9/JluNL+9XlqvF7PC1WL4OwZV9j2+Nq4pLzSc9pjJjBzi9/WS+NkbM2MCcAjFh19+4w5YLKj7H68Zgj6lGLooQua1APuhL9Tj6gkVbziCj9wnJ5xvd4UiZEyuoY49SrxDSKKku99T/o+eAjsFKkjL4AJnv0O25+MwA+pAMHmFWG6T7R1mrXDy7DAkiPGQR4jBahMCMl4FO2kIL4J80NpBYBOruiCWdzo4O/oCEi+llgPkx8O4ye0JOXWueAUuyn+FaxdG+pr32p7SVctOvr1S+gmr0fpbIUiEaRxaKvVOllWNqDDe1UG6NsWzezlVQ9hr9HBW4QM1MWAMKDCqnbfQdwC5Cc+VGiDpgaUFNBnf9aMClYZGqdR7zJ051/a0jafFRCMyLLhPR6sjrkQQmslgqLYpoh7Web8AXdfdYJ4f+FKktgftIx/f8JbZP09347LuL13XMDqSZ1XsxZKBL+WCh/HOUJ1+wSbthyjwz2h4v7yREZq3ABu7S3c8YVltjiREE5fX2rDVpTtDxn825NgAd65XlPUz28i8WvFHmITrsLAV8FMPlLQpILEhiyLhIuRP4KVEQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 03:46:55.8906 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4da1fa2d-03b8-455c-f4e1-08dcf24c2c9c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7365 AMD heterogeneous designs include two types of cores: * Performance * Efficiency Each core type has different highest performance values configured by the platform. Drivers such as `amd_pstate` need to identify the type of core to correctly set an appropriate boost numerator to calculate the maximum frequency. X86_FEATURE_AMD_HETEROGENEOUS_CORES is used to identify whether the SoC supports heterogeneous core type by reading CPUID leaf Fn_0x80000026. On performance cores the scaling factor of 196 is used. On efficiency cores the scaling factor is the value reported as the highest perf. Efficiency cores have the same preferred core rankings. Suggested-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/kernel/acpi/cppc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 956984054bf30..4fd007eac0c71 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -234,8 +234,10 @@ EXPORT_SYMBOL_GPL(amd_detect_prefcore); */ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) { + enum x86_topology_cpu_type core_type = topology_cpu_type(&cpu_data(cpu)); bool prefcore; int ret; + u32 tmp; ret = amd_detect_prefcore(&prefcore); if (ret) @@ -261,6 +263,27 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) break; } } + + /* detect if running on heterogeneous design */ + switch (core_type) { + case TOPO_CPU_TYPE_UNKNOWN: + break; + case TOPO_CPU_TYPE_PERFORMANCE: + /* use the max scale for performance cores */ + *numerator = CPPC_HIGHEST_PERF_PERFORMANCE; + return 0; + case TOPO_CPU_TYPE_EFFICIENCY: + /* use the highest perf value for efficiency cores */ + ret = amd_get_highest_perf(cpu, &tmp); + if (ret) + return ret; + *numerator = tmp; + return 0; + default: + pr_warn("WARNING: Undefined core type %d found\n", core_type); + break; + } + *numerator = CPPC_HIGHEST_PERF_PREFCORE; return 0;