From patchwork Wed Oct 23 06:52:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6683FD2E01C for ; Wed, 23 Oct 2024 06:50:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6717210E74A; Wed, 23 Oct 2024 06:50:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XekNAQEw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8DFEB10E74A; Wed, 23 Oct 2024 06:50:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666244; x=1761202244; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=es/HjCAJYCzwCPU7dULSoJgOHBK4YaktiMq3kR5cz+I=; b=XekNAQEwtbzTwPHqf4jeyyRIrp1QCQc5aLImsjoPZCWefpQldWfa3h6D kJzhc3XMwNZ67MQC4Z75TRPdrjZYijt3pfwdgOJoqt7cLqI2lFCJ81TCx G3/QZfGAQ+Z0PSbzDcOMF/4Rr8UTica+qg3jCAibSeJNJNtbBx308kHyO DE8Xgv8ugq3zpDwMoOuYpWkYTpwwTYA5vqI5sI7pBOcLegcT3dH0S5Nha NX4dZLCrLJrOj5G/n0BTQ2A1tEVCVixjIUrCeciXocJEPbXcFPfHtdyou nMMatsa7tBzbCcBU6u5o1wlfk2x+S/ds5pyAFoMV5qMkSEo47eZCES2mz g==; X-CSE-ConnectionGUID: gpDxQ8fYTnOaPBr7Sdy3KA== X-CSE-MsgGUID: 68Syqr21T6yW0TDbh58pag== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097460" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097460" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:43 -0700 X-CSE-ConnectionGUID: zySYvNgFSOOxvxYtXPGmmw== X-CSE-MsgGUID: 5khqJcAyR02lLIjj/6+fJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691481" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:42 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices per Line Date: Wed, 23 Oct 2024 12:22:42 +0530 Message-ID: <20241023065257.190035-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For some platforms, the maximum slices per DSC engine is 4, while for others it is 2. Update the comment to reflect this and clarify that the 'valid_dsc_slicecount' list represents the valid number of slices per pipe. Currently, we are working with 1, and 2 slices per DSC engine, which works for all platforms. With this the number of slices per pipe can be 1,2 or 4 with different slice & DSC engine configuration. Add a #TODO for adding support for 4 slices per DSC engine where supported. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7e04913bc2ff..286b272aa98c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -108,8 +108,14 @@ /* Constants for DP DSC configurations */ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; -/* With Single pipe configuration, HW is capable of supporting maximum - * of 4 slices per line. +/* + * With Single pipe configuration, HW is capable of supporting maximum of: + * 2 slices per line for ICL, BMG + * 4 slices per line for other platforms. + * For now consider a max of 2 slices per line, which works for all platforms. + * With this we can have max of 4 DSC Slices per pipe. + * + * #TODO Split this better to use 4 slices/dsc engine where supported. */ static const u8 valid_dsc_slicecount[] = {1, 2, 4}; From patchwork Wed Oct 23 06:52:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 061BDD2E018 for ; Wed, 23 Oct 2024 06:50:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7673E10E74B; Wed, 23 Oct 2024 06:50:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Qm3I+/dl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B93610E74B; Wed, 23 Oct 2024 06:50:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666245; x=1761202245; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bKIdguoOO+jNmz6np+D9p0VXdun1W/pZQv6j2o7C5ug=; b=Qm3I+/dlXPZyba/CWR7FdKQ5hQRF7t/qjgy60k1B6PyDtV3MCUZ2hOsH 3aK9Ri1EJUIF1DBjtUr8wTSBEhtUbunmvu0FrYDhAQAPIlsAVXDZOIBKE SNF/5jEhl2QDKXH5mgCKN7AuN2YakdYjh7tTr70OSfufv2wzj72jJF3Cb wSQorf18YQJaAHpuOT+l4AZGXLQuZV+iUxxyTEx6QdO/TPsXDQrYlU85Q 19ZlPa7foJXl1DalwQHW4ApQihjaoUforG6ChXffcMHPzceAt7DNayoyK n7ZFOUj6cShpWpZEgN0F2fbHogN4GKM3ZuXIx+E/JIxM42ya7y+8KI0mI w==; X-CSE-ConnectionGUID: ZVZyS5UuQCymtTKt2DEjRA== X-CSE-MsgGUID: o0nUFjf/QTKBoKgBh9ravQ== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097463" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097463" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:45 -0700 X-CSE-ConnectionGUID: 2OhlyJIrQdGDMz9I9bfPbA== X-CSE-MsgGUID: TXPpLintTdq+zsRxoM+i+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691490" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:44 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter Date: Wed, 23 Oct 2024 12:22:43 +0530 Message-ID: <20241023065257.190035-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" At the moment dsc_split represents whether the dsc splitter is used or not. With 3 DSC engines, the splitter can split into two streams or three streams. Instead of representing the splitter's state, it is more effective to represent the number of DSC streams per pipe. Replace the `dsc.dsc_split` member with `dsc.num_streams` to indicate the number of DSC streams used per pipe. This change will implicitly convey the splitter's operation mode. v2: Avoid new enum for dsc split. (Suraj) v3: -Replace dsc_split with num_stream. (Suraj) -Avoid extra parentheses. (Jani) Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 +++- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- drivers/gpu/drm/i915/display/intel_vdsc.c | 16 +++++++++++----- 5 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 87a27d91d15d..7d5571c39b7e 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1595,7 +1595,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, /* FIXME: split only when necessary */ if (crtc_state->dsc.slice_count > 1) - crtc_state->dsc.dsc_split = true; + crtc_state->dsc.num_streams = 2; + else + crtc_state->dsc.num_streams = 1; /* FIXME: initialize from VBT */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef1436146325..3dfff0a8c386 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5741,7 +5741,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); PIPE_CONF_CHECK_BOOL(dsc.compression_enable); - PIPE_CONF_CHECK_BOOL(dsc.dsc_split); + PIPE_CONF_CHECK_I(dsc.num_streams); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); PIPE_CONF_CHECK_BOOL(splitter.enable); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f..5611a4dd6a6f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1235,7 +1235,7 @@ struct intel_crtc_state { /* Display Stream compression state */ struct { bool compression_enable; - bool dsc_split; + int num_streams; /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; u8 slice_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 286b272aa98c..77487a55280c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2409,7 +2409,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * then we need to use 2 VDSC instances. */ if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) - pipe_config->dsc.dsc_split = true; + pipe_config->dsc.num_streams = 2; + else + pipe_config->dsc.num_streams = 1; ret = intel_dp_dsc_compute_params(connector, pipe_config); if (ret < 0) { diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 40525f5c4c42..afc40d180dec 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -379,7 +379,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) { - return crtc_state->dsc.dsc_split ? 2 : 1; + return crtc_state->dsc.num_streams; } int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) @@ -976,8 +976,14 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) if (!crtc_state->dsc.compression_enable) goto out; - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && - (dss_ctl1 & JOINER_ENABLE); + if (dss_ctl1 & JOINER_ENABLE) { + if (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) + crtc_state->dsc.num_streams = 2; + else + crtc_state->dsc.num_streams = 1; + } else { + crtc_state->dsc.num_streams = 0; + } intel_dsc_get_pps_config(crtc_state); out: @@ -988,10 +994,10 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state) { drm_printf_indent(p, indent, - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n", + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), crtc_state->dsc.slice_count, - str_yes_no(crtc_state->dsc.dsc_split)); + crtc_state->dsc.num_streams); } void intel_vdsc_state_dump(struct drm_printer *p, int indent, From patchwork Wed Oct 23 06:52:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E966CD2E01F for ; Wed, 23 Oct 2024 06:50:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C4C810E753; Wed, 23 Oct 2024 06:50:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bxTW8QlD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D09210E74C; Wed, 23 Oct 2024 06:50:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666247; x=1761202247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8LwXJCglBB/sPofhDyBEblLJrBhz6btjVpj04G4qZCY=; b=bxTW8QlDSHNuXXQqBrJ3UaSrssBPK4eO5JKdSeY/ge4tvXnyhlOSYKAW krq+AmWleLV0/qXYy1fS+OG839sTMl9h4s8syePD41Lf11cILDxz6mZQy ADP19z5U1/nBAC765UG4NgthJxAiSd8VQExDwt0KFuN47n1sb9mbKvF35 7NzBFV45bDaB9Ag0KD10DMh1JkE7YGbaZEBQKZSrHBYuWpW7R2I+CmK7W 5FuOsz0tWNKFdDUW37GXPQeVPS4B+twdqCEy0AIz7Rvmrk4zMHJEiQXX3 gdifh0NVCmHB5MtREE9kviqizIOcYZzuAzXlPHlsiMqYKmiSzJrLTKUVP A==; X-CSE-ConnectionGUID: Uesn0a1BQVqd16amgNAW3Q== X-CSE-MsgGUID: 5rJSpwEiRzGNV7Dztx5uqA== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097465" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097465" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:46 -0700 X-CSE-ConnectionGUID: IFttxzXhQCaij4/aW8qizg== X-CSE-MsgGUID: +wM6WmIoSQeWmzAORZU1Rg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691499" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:45 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 03/16] drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Date: Wed, 23 Oct 2024 12:22:44 +0530 Message-ID: <20241023065257.190035-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead. While at it, use REG_BIT macro for the bits. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index afc40d180dec..159f83edd5b0 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -770,9 +770,9 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) intel_dsc_pps_configure(crtc_state); - dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; + dss_ctl2_val |= VDSC0_ENABLE; if (vdsc_instances_per_pipe > 1) { - dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; + dss_ctl2_val |= VDSC1_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } if (crtc_state->joiner_pipes) { @@ -972,12 +972,12 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); - crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; + crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; if (!crtc_state->dsc.compression_enable) goto out; if (dss_ctl1 & JOINER_ENABLE) { - if (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) + if (dss_ctl2 & VDSC1_ENABLE) crtc_state->dsc.num_streams = 2; else crtc_state->dsc.num_streams = 1; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index bf32a3b46fb1..d7a72b95ee7e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -21,8 +21,8 @@ #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 #define DSS_CTL2 _MMIO(0x67404) -#define LEFT_BRANCH_VDSC_ENABLE (1 << 31) -#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) +#define VDSC0_ENABLE REG_BIT(31) +#define VDSC1_ENABLE REG_BIT(15) #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) From patchwork Wed Oct 23 06:52:45 2024 Content-Type: text/plain; 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d="scan'208";a="84691503" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:47 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 Date: Wed, 23 Oct 2024 12:22:45 +0530 Message-ID: <20241023065257.190035-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduce the register bits to enable the 3rd DSC engine VDSC2. Add support to read/write these bits. v2: Only introduce bits that are used and update the subject and commit message. (Suraj) Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +++++++++- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 159f83edd5b0..29b1aa7f4f94 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -775,6 +775,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) dss_ctl2_val |= VDSC1_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } + + if (vdsc_instances_per_pipe > 2) { + dss_ctl2_val |= VDSC2_ENABLE; + dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES; + } + if (crtc_state->joiner_pipes) { if (intel_crtc_ultrajoiner_enable_needed(crtc_state)) dss_ctl1_val |= ULTRA_JOINER_ENABLE; @@ -977,7 +983,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) goto out; if (dss_ctl1 & JOINER_ENABLE) { - if (dss_ctl2 & VDSC1_ENABLE) + if (dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES)) + crtc_state->dsc.num_streams = 3; + else if (dss_ctl2 & VDSC1_ENABLE) crtc_state->dsc.num_streams = 2; else crtc_state->dsc.num_streams = 1; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index d7a72b95ee7e..474a7f9f3881 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -22,6 +22,8 @@ #define DSS_CTL2 _MMIO(0x67404) #define VDSC0_ENABLE REG_BIT(31) +#define VDSC2_ENABLE REG_BIT(30) +#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) #define VDSC1_ENABLE REG_BIT(15) #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) From patchwork Wed Oct 23 06:52:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70A0BD2E01B for ; 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X-CSE-ConnectionGUID: nW5JpCdRSUu7b+t9aoBh9A== X-CSE-MsgGUID: XzhxYgDVQR+Urktp5+cO6A== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097471" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097471" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:50 -0700 X-CSE-ConnectionGUID: c7xaDRfQT8q0JWJxF111hA== X-CSE-MsgGUID: PXmamDbZSaWa4Wr40Sojtw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691508" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:48 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 05/16] drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine Date: Wed, 23 Oct 2024 12:22:46 +0530 Message-ID: <20241023065257.190035-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS registers for the 3rd DSC engine Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +++++--- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 6 ++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 29b1aa7f4f94..4143109aaab6 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -402,8 +402,10 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); - if (dsc_reg_num >= 3) + if (dsc_reg_num >= 4) MISSING_CASE(dsc_reg_num); + if (dsc_reg_num >= 3) + dsc_reg[2] = BMG_DSC2_PPS(pipe, pps); if (dsc_reg_num >= 2) dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps); if (dsc_reg_num >= 1) @@ -415,7 +417,7 @@ static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - i915_reg_t dsc_reg[2]; + i915_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); @@ -815,7 +817,7 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - i915_reg_t dsc_reg[2]; + i915_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; u32 val; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 474a7f9f3881..2d478a84b07c 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -59,8 +59,10 @@ #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 +#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB 0x78970 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 +#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC 0x78A70 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) @@ -73,8 +75,12 @@ #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) +#define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB, \ + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC) #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) +#define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4)) /* PPS 0 */ #define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23) From patchwork Wed Oct 23 06:52:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB793D2E01C for ; Wed, 23 Oct 2024 06:50:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E925F10E75A; Wed, 23 Oct 2024 06:50:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Xb/n4Hn4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E65810E752; Wed, 23 Oct 2024 06:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666251; x=1761202251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tjBcq/usllITqwtcxzbzejklsVHWnCuUGjUtoK8N8sk=; b=Xb/n4Hn4yxRUY4kVYHcId2m4dOSzVRRxZxYQsu8tLQtfoVMuoA/HmdA1 hUri7LB6omLwlJKC6ah3W4QfIqZZ0xRYciwLJjA1nQ2q0KovIbfbcpPaL TJasqF7+P0jhFVs2LQ5uXpgWodH9ze8DzD8MTOBq51xdBFNq28LmBh2/l BiUB/RSAa/Pj5Z1kLkjVnSfkIVqqcEIBgfCCi6XGawlsZbG1riSQRjh0t /82BCsYDncxKEE4eJ31GjUytpOChMhlYMDLLhI4JHjicpxqhYtoZf19GN wCrHoaZB3o5yHoMbEs+Gs7tM10zA/fAXftRJ5ROhEmkULZ71xhN5Uvpbh A==; X-CSE-ConnectionGUID: 75uLQnTcR9OPDO9tka0qCQ== X-CSE-MsgGUID: bdqquN4WR6CrmoJCWdwucA== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097472" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097472" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:51 -0700 X-CSE-ConnectionGUID: 2TP1WNTTQ/SvgQDoTLsCqQ== X-CSE-MsgGUID: vsg6GvaLSV+ZpnTc/SjhuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691511" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:50 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count Date: Wed, 23 Oct 2024 12:22:47 +0530 Message-ID: <20241023065257.190035-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to the DSC spec, the slice width should be chosen such that the picture width (hactive) is evenly divisible by the slice width. If not, extra pixels (padding) must be added to the last slice to ensure all slices have the same width. Currently, we do not support handling these extra pixels. Therefore, select a slice count that evenly divides the hactive (slice_width = hactive / slice_count). This check is already implemented for DSI, where the slice count is selected from the BIOS. For DP, currently with 1, 2, 4 slices per pipe it is unlikely to have slice count not being able to divide hactive, but with 3 DSC engines and 3 slices, we can have such cases. Adding this check prepares for future scenarios where such configurations might be used. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 77487a55280c..3b20ea844925 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1037,6 +1037,9 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) continue; + if (mode_hdisplay % test_slice_count) + continue; + if (min_slice_count <= test_slice_count) return test_slice_count; } From patchwork Wed Oct 23 06:52:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECC30D2E018 for ; Wed, 23 Oct 2024 06:50:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F23F10E757; Wed, 23 Oct 2024 06:50:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SN6Ns6WL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id C050010E757; Wed, 23 Oct 2024 06:50:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666253; x=1761202253; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JIx/kJxxkTWFies8iN46JiY6fx7eZa5O9so0MW/fDsA=; b=SN6Ns6WL5assqxPj2Z2OQLjp7vm3Vg/10/HZFPnCcb06AHH4l3esm//T yA6tMBifgEhNC2NoBsU8tbnEG/AhrbQlLIyyM5CUvXLXxwtQfAINUVlB8 kQUhKfyx4k8HRoJHnSXBPrf4+VMWqoM00Bz0ussuGOiBRucq5zIBzFOBN WTaaKqdnpakjwIcU7tCBGG7KFD0A5ojMKHPpvhWV9w/7TsHfpxYXqb2Oo s3c51ccJtfJvpb8cHyEUIY8nUvxA5P54I+xRFTZklN8wpL0j4ouBc3Zsa rhwRwa2w5r8kFx/4M/5Pk3AMzcoPLKEyaqgAodt+cETpwDWOWhmuXk1oQ A==; X-CSE-ConnectionGUID: sqDyVgp6QZ6bQtm0aI5Ymg== X-CSE-MsgGUID: nJ22iekrQWKcme87lZNVgw== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097473" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097473" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:53 -0700 X-CSE-ConnectionGUID: /x04iSKJTFiHHFxVFRpzNg== X-CSE-MsgGUID: 1esmACgISCCeBlEyf/TwrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691534" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:51 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 07/16] drm/i915/dp: Enable 3 DSC engines for 12 slices Date: Wed, 23 Oct 2024 12:22:48 +0530 Message-ID: <20241023065257.190035-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Certain resolutions require 12 DSC slices support along with ultrajoiner. For such cases, the third DSC Engine per Pipe is enabled. Each DSC Engine processes 1 Slice, resulting in a total of 12 VDSC slices (4 Pipes * 3 DSC Instances per Pipe). Add support for 12 DSC slices and 3 DSC engines for such modes. v2: Add missing check for 3 slices support only with 4 joined pipes. (Suraj) Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3b20ea844925..4065fc26e70e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,9 +115,12 @@ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; * For now consider a max of 2 slices per line, which works for all platforms. * With this we can have max of 4 DSC Slices per pipe. * + * For higher resolutions where 12 slice support is required with + * ultrajoiner, only then each pipe can support 3 slices. + * * #TODO Split this better to use 4 slices/dsc engine where supported. */ -static const u8 valid_dsc_slicecount[] = {1, 2, 4}; +static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; /** * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) @@ -1025,6 +1028,13 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; + /* + * 3 DSC Slices per pipe need 3 DSC engines, + * which is supported only with Ultrajoiner. + */ + if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4) + continue; + if (test_slice_count > drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) break; @@ -2410,8 +2420,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. + * In case of Ultrajoiner along with 12 slices we need to use 3 + * VDSC instances. */ - if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) + if (pipe_config->joiner_pipes && num_joined_pipes == 4 && + pipe_config->dsc.slice_count == 12) + pipe_config->dsc.num_streams = 3; + else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) pipe_config->dsc.num_streams = 2; else pipe_config->dsc.num_streams = 1; From patchwork Wed Oct 23 06:52:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 818D1D2E01D for ; Wed, 23 Oct 2024 06:50:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A542810E756; Wed, 23 Oct 2024 06:50:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LUFjFeTf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 52ACC10E757; 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22 Oct 2024 23:50:54 -0700 X-CSE-ConnectionGUID: Q6sw8USGTIqQ5GILWbuKlQ== X-CSE-MsgGUID: XrtN8PrOQxypNodfX50Teg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691557" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:53 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION Date: Wed, 23 Oct 2024 12:22:49 +0530 Message-ID: <20241023065257.190035-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add macro for Pixel replication support with DSC. Bspec: 49259, 68912 Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 071a36b51f79..a21b910879df 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -149,6 +149,9 @@ enum intel_display_subplatform { #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) +#define HAS_PIXEL_REPLICATION(i915) (HAS_DSC(i915) && \ + (DISPLAY_VER(i915) >= 20 || \ + DISPLAY_VER_FULL(i915) == IP_VER(14, 1))) #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) From patchwork Wed Oct 23 06:52:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC256D2E020 for ; Wed, 23 Oct 2024 06:51:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 48A7310E758; Wed, 23 Oct 2024 06:51:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CKkvRk5E"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id D1D3C10E75C; Wed, 23 Oct 2024 06:50:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666256; x=1761202256; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eiHmzIxzkculnuc6dVIOGIGRHJlIW53uRG7zMScLR0w=; b=CKkvRk5EgHEALnO+G/OrRHcGWC+Xgd6wUEER71sWXEEyuUWhxCHI7ixj QCDTSL04b6YwFeBi+FITaCZ1HdDjYzTySCOxc1AKK5HH85a9HeaWI0NPV C/rFTTHrJ3M7yqoYs5f68Xsd8VTq+DMWBilV1c6gJhC8eyDK6jLaSey17 ZPzA/VLqa7NoiZ61GRgJQb/lBUko2hZRqOZgDzuthdVnVQTgKggTSbA1V eLFquFYwnCrUUoz+1VKgheNIMcFLKhAGTYrJEPEkzFLgHLIrVM5+3YR6z ca25R4fGkJcuUGsZ6KW14vQzhwY0zouPG08jO1pkPPWILSEcEdc/zbcE3 w==; X-CSE-ConnectionGUID: ILPxfvf2QYWOyX5LMkE3eg== X-CSE-MsgGUID: 7lbNNwwIQHK/br/jyuVpCQ== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097478" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097478" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:56 -0700 X-CSE-ConnectionGUID: 6tpnV13AT+WIq7QpmkcH8Q== X-CSE-MsgGUID: rkCISqgrRfCuDc7karWYnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691586" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:54 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 09/16] drm/i915/display: Add support for DSC pixel replication Date: Wed, 23 Oct 2024 12:22:50 +0530 Message-ID: <20241023065257.190035-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With 3 VDSC engines and Ultrajoiner, we may encounter a situation where hactive is not a multiple of slice count. In this case we need to add extra pixels to the last slice to distribute pixels evenly across slices. Add member to store DSC pixel replication when hactive is not divisible by slice count. Fill DSS_CTL3 register with the replicated pixel count. Also add this in dsc state dump. v2: Use macro REG_FIELD_PREP and HAS_PIXEL_REPLICATION. (Suraj) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 27 ++++++++++++++++--- .../gpu/drm/i915/display/intel_vdsc_regs.h | 8 ++++++ 4 files changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3dfff0a8c386..aa9e44970752 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5743,6 +5743,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(dsc.compression_enable); PIPE_CONF_CHECK_I(dsc.num_streams); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); + PIPE_CONF_CHECK_I(dsc.replicated_pixels); PIPE_CONF_CHECK_BOOL(splitter.enable); PIPE_CONF_CHECK_I(splitter.link_count); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5611a4dd6a6f..282aab2d1b5d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1239,6 +1239,7 @@ struct intel_crtc_state { /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; u8 slice_count; + int replicated_pixels; struct drm_dsc_config config; } dsc; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 4143109aaab6..8b1639a94438 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -765,6 +765,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; u32 dss_ctl2_val = 0; + u32 dss_ctl3_val = 0; int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); if (!crtc_state->dsc.compression_enable) @@ -795,8 +796,16 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) if (intel_crtc_is_bigjoiner_primary(crtc_state)) dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } + + if (crtc_state->dsc.replicated_pixels) + dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.replicated_pixels); + intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); + + if (HAS_PIXEL_REPLICATION(dev_priv) && dss_ctl3_val) + intel_de_write(dev_priv, + BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder), dss_ctl3_val); } void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) @@ -809,6 +818,10 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) old_crtc_state->joiner_pipes) { intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); + + if (HAS_PIXEL_REPLICATION(dev_priv)) + intel_de_write(dev_priv, + BMG_PIPE_DSS_CTL3(old_crtc_state->cpu_transcoder), 0); } } @@ -966,7 +979,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; - u32 dss_ctl1, dss_ctl2; + u32 dss_ctl1, dss_ctl2, dss_ctl3 = 0; if (!intel_dsc_source_support(crtc_state)) return; @@ -980,6 +993,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); + if (HAS_PIXEL_REPLICATION(dev_priv)) + dss_ctl3 = intel_de_read(dev_priv, BMG_PIPE_DSS_CTL3(crtc_state->cpu_transcoder)); + crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; if (!crtc_state->dsc.compression_enable) goto out; @@ -995,6 +1011,10 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.num_streams = 0; } + if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) + crtc_state->dsc.replicated_pixels = + dss_ctl3 & DSC_PIXEL_REPLICATION_MASK; + intel_dsc_get_pps_config(crtc_state); out: intel_display_power_put(dev_priv, power_domain, wakeref); @@ -1004,10 +1024,11 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state) { drm_printf_indent(p, indent, - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d, replicated pixels: %d\n", FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), crtc_state->dsc.slice_count, - crtc_state->dsc.num_streams); + crtc_state->dsc.num_streams, + crtc_state->dsc.replicated_pixels); } void intel_vdsc_state_dump(struct drm_printer *p, int indent, diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 2d478a84b07c..f07fad6239bc 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -50,6 +50,14 @@ _ICL_PIPE_DSS_CTL2_PB, \ _ICL_PIPE_DSS_CTL2_PC) +#define _BMG_PIPE_DSS_CTL3_PB 0x782f0 +#define _BMG_PIPE_DSS_CTL3_PC 0x784f0 +#define BMG_PIPE_DSS_CTL3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _BMG_PIPE_DSS_CTL3_PB, \ + _BMG_PIPE_DSS_CTL3_PC) +#define DSC_PIXEL_REPLICATION_MASK REG_GENMASK(15, 0) +#define DSC_PIXEL_REPLICATION(count) (REG_FIELD_PREP(DSC_PIXEL_REPLICATION_MASK, (count))) + /* Icelake Display Stream Compression Registers */ #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) From patchwork Wed Oct 23 06:52:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF0FAD2E01B for ; Wed, 23 Oct 2024 06:50:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 526A210E746; Wed, 23 Oct 2024 06:50:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="X5+VeKx6"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 65CC610E75B; Wed, 23 Oct 2024 06:50:57 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="84691593" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:56 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 10/16] drm/i915/dp_mst: Account for pixel replication for MST overhead with DSC Date: Wed, 23 Oct 2024 12:22:51 +0530 Message-ID: <20241023065257.190035-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the extra pixels to the hactive while computing overhead with DSC. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_vdsc.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.h | 6 ++++++ 4 files changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 60baf4072dc9..e90a9dc1a8f5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -20,6 +20,7 @@ struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; struct intel_digital_port; +struct intel_display; struct intel_dp; struct intel_encoder; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1a2ff3e1cb68..2bd33e1b318e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -92,20 +92,34 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, bool ssc, int dsc_slice_count, int bpp_x16) { + struct intel_display *display = to_intel_display(crtc_state); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; unsigned long flags = DRM_DP_BW_OVERHEAD_MST; int overhead; + int replicated_pixels = 0; flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0; flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; - if (dsc_slice_count) + if (dsc_slice_count) { flags |= DRM_DP_BW_OVERHEAD_DSC; + /* + * When hdisplay is not divisible by dsc_slice_count, extra pixels + * are added to last slice. Need to account for the extra overhead due + * to these extra pixels. + */ + if (adjusted_mode->hdisplay % dsc_slice_count) + replicated_pixels = + intel_dsc_get_replicated_pixels(display, + adjusted_mode->hdisplay, + dsc_slice_count, + crtc_state->output_format); + } overhead = drm_dp_bw_overhead(crtc_state->lane_count, - adjusted_mode->hdisplay, + adjusted_mode->hdisplay + replicated_pixels, dsc_slice_count, bpp_x16, flags); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 8b1639a94438..9eaf608995dc 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1040,3 +1040,23 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, intel_vdsc_dump_state(p, indent, crtc_state); drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); } + +int intel_dsc_get_replicated_pixels(struct intel_display *display, + int mode_hdisplay, + int slice_count, + enum intel_output_format output_format) +{ + int replicated_pixels; + int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count); + + if (!HAS_PIXEL_REPLICATION(display)) + return 0; + + /* Odd slice width is not supported by YCbCr420 format */ + if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return 0; + + replicated_pixels = (slice_width * slice_count) - mode_hdisplay; + + return replicated_pixels; +} diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 290b2e9b3482..41b8b5c5866e 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -10,9 +10,11 @@ struct drm_printer; +enum intel_output_format; enum transcoder; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_encoder; bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state); @@ -31,5 +33,9 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); +int intel_dsc_get_replicated_pixels(struct intel_display *display, + int mode_hdisplay, + int slice_count, + enum intel_output_format output_format); #endif /* __INTEL_VDSC_H__ */ From patchwork Wed Oct 23 06:52:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CC47D2E01B for ; Wed, 23 Oct 2024 06:51:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A71910E760; Wed, 23 Oct 2024 06:51:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="32097482" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097482" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:59 -0700 X-CSE-ConnectionGUID: 7Yy+npMHQj+0Zwfkv8iZwQ== X-CSE-MsgGUID: SBf0IB1LRE+wtfBArF5dAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691598" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:50:58 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 11/16] drm/i915/dp: Account for pixel replication for BW computation with DSC Date: Wed, 23 Oct 2024 12:22:52 +0530 Message-ID: <20241023065257.190035-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Include the extra pixels added while computing bandwidth with DSC. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4065fc26e70e..f4a446824cb3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1940,6 +1940,23 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_cloc return available_bw > required_bw; } +static +u32 adjust_clock_for_extra_pixels(const struct drm_display_mode *adjusted_mode, + int extra_pixels) +{ + u32 clock = adjusted_mode->clock; + u16 htotal = adjusted_mode->htotal; + + if (!extra_pixels) + return clock; + /* + * clock = (htotal) * (vtotal) * refresh_rate + * adjusted_clock = (htotal + extra_pixels) * (vtotal) * refresh_rate + * = clock + (clock * extra_pixels / htotal) + */ + return clock + extra_pixels * (clock / htotal); +} + static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, @@ -1948,8 +1965,12 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, { const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int link_rate, lane_count; + u32 adjusted_clock; int i; + adjusted_clock = adjust_clock_for_extra_pixels(adjusted_mode, + pipe_config->dsc.replicated_pixels); + for (i = 0; i < intel_dp->num_common_rates; i++) { link_rate = intel_dp_common_rate(intel_dp, i); if (link_rate < limits->min_rate || link_rate > limits->max_rate) @@ -1959,7 +1980,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, lane_count <= limits->max_lane_count; lane_count <<= 1) { if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, - lane_count, adjusted_mode->clock, + lane_count, adjusted_clock, pipe_config->output_format, timeslots)) continue; From patchwork Wed Oct 23 06:52:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75D0BD2E01E for ; Wed, 23 Oct 2024 06:51:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 166CF10E764; Wed, 23 Oct 2024 06:51:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AC6KA+xx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19FF910E75C; Wed, 23 Oct 2024 06:51:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666264; x=1761202264; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hv7YLVkJJKTT2VNLvv46icwwunGTkWFQjo7uFj9dvko=; b=AC6KA+xxlllnxAAUtDgnoB+iPzR6bwWtDH/ibozbf+qkNC62bFwOfHEr 8eV0/oHdpqg1zYXtgAXdb3aSYjJ+7TUIZfW3bVBzxnKH/KrNQQ3VCKgUZ DHS66MAXYVlokvPOaYSEhM5Qa81lcYzPEQDWq//WeXtj/RebKNJPfzDim ZuM5H4fDQp7GYWT392I1P4idJmES+RbSMqjpZ+Ax9LykzrfskSTb/mTr9 LZm8RoQxZJ9oEfzTI79/zMqc70VahZFqyV1PDBCzc6uuSGR0KpXnBixMk tBPZhBcSACh1aFO2E6MnAmS6fMYUpN8IOInwwh4ojLA4fAuSCNZ7dOPLT g==; X-CSE-ConnectionGUID: YASatE9OTCuTMFypyyGiUg== X-CSE-MsgGUID: 41FEN9wFTKGt3B2klJuMlQ== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097495" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097495" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:04 -0700 X-CSE-ConnectionGUID: ajBn4doMQjmIWAoGGttiDQ== X-CSE-MsgGUID: oJq4AuxnQMeXbLFPJmYpRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691618" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:01 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 12/16] drm/i915/display: Account for pixel replication in pipe_src Date: Wed, 23 Oct 2024 12:22:53 +0530 Message-ID: <20241023065257.190035-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With DSC pixel replication, extra pixels are added in the last slice of the last pipe. Due to this the total hactive gets increased by few pixels. Adjust the computation for pipe source width to account for pixel replication. These extra pixels will be take care by the Splitter logic in hardware. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index aa9e44970752..8065ed921952 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2514,6 +2514,22 @@ void intel_encoder_get_config(struct intel_encoder *encoder, intel_crtc_readout_derived_state(crtc_state); } +static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels) +{ + /* Account for Pixel replication: + * Pixel replication is required due to the rounding of slice_width (Hactive / slice_count). + * + * Splitter HW takes care of these by removing replicated pixels from the last pipe. + */ + + if (!replicated_pixels) + return width; + + width += replicated_pixels; + + return width; +} + static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) { int num_pipes = intel_crtc_num_joined_pipes(crtc_state); @@ -2522,7 +2538,9 @@ static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) if (num_pipes == 1) return; - width = drm_rect_width(&crtc_state->pipe_src); + width = intel_splitter_adjust_pipe_width(drm_rect_width(&crtc_state->pipe_src), + crtc_state->dsc.replicated_pixels); + height = drm_rect_height(&crtc_state->pipe_src); drm_rect_init(&crtc_state->pipe_src, 0, 0, From patchwork Wed Oct 23 06:52:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29C98D2E01F for ; Wed, 23 Oct 2024 06:51:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD8DF10E765; Wed, 23 Oct 2024 06:51:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MKm43V5T"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F9C310E762; Wed, 23 Oct 2024 06:51:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666264; x=1761202264; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k9Ugfvo26XuQP34ms6NjO4xTjQADEzrYE6WveB9BBOc=; b=MKm43V5TiaoUmB837z2ND6Dg1boQHGVKQSNAPBjPe+4IgcyYfaOB8X9S YjUJ/5TexRb1JgB4gF8minxmXRhbmo95Fqi/P29Xnmztr2Q2ebkSLaAnn v7Kzd8vWf/kfBm7+1qpb8+ETvhq2eSVbtQPas/gAlQZxb6+QCJbrwl89m d9FVY8ayFx3B1NUuS8TySeUSwf3jc+MBhwFp1HTukglTxdTAOhF+pXA4v qrlRnR5jDSlc8qfjmGOuYMsXYJGDrMYRxTfTrajqeegF1kbaOPOr/Mi/B tMA6lt8yM0jwdQHuqLiQIg3tdQUNrYOfj9ne+6JstmJFYBTSp7cn/yCdT g==; X-CSE-ConnectionGUID: agl26054S3+SMnKSAGecCA== X-CSE-MsgGUID: LE9lrMv0QiSFyUWEXB6PoA== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097498" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097498" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:04 -0700 X-CSE-ConnectionGUID: tNTSiGXmTO2J3pf2osrmmA== X-CSE-MsgGUID: NPAX1HtGRzeDXjbIP1dw/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691623" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:03 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 13/16] drm/i915/dp: Enable DSC pixel replication Date: Wed, 23 Oct 2024 12:22:54 +0530 Message-ID: <20241023065257.190035-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Allow DSC slice count that do not divide the hactive evenly by adding extra pixels (replicated pixels). Check if the pixel replication is supported and store the no. of replicated pixel count in crtc_state. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++----- drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++ 5 files changed, 44 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f4a446824cb3..026254687a8d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -992,9 +992,11 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, + enum intel_output_format output_format, int num_joined_pipes) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); + struct drm_i915_private *i915 = to_i915(display->drm); u8 min_slice_count, i; int max_slice_width; @@ -1047,7 +1049,11 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) continue; - if (mode_hdisplay % test_slice_count) + if (mode_hdisplay % test_slice_count && + !intel_dsc_can_use_pixel_replication(display, + mode_hdisplay, + test_slice_count, + output_format)) continue; if (min_slice_count <= test_slice_count) @@ -1474,6 +1480,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, intel_dp_dsc_get_slice_count(connector, target_clock, mode->hdisplay, + output_format, num_joined_pipes); } @@ -2366,6 +2373,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, int timeslots, bool compute_pipe_bpp) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct intel_connector *connector = @@ -2428,6 +2436,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, intel_dp_dsc_get_slice_count(connector, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, + pipe_config->output_format, num_joined_pipes); if (!dsc_dp_slice_count) { drm_dbg_kms(&dev_priv->drm, @@ -2437,6 +2446,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->dsc.slice_count = dsc_dp_slice_count; } + + pipe_config->dsc.replicated_pixels = + intel_dsc_get_replicated_pixels(display, + adjusted_mode->crtc_hdisplay, + pipe_config->dsc.slice_count, + pipe_config->output_format); + /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index e90a9dc1a8f5..7460675c16f6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -150,6 +150,7 @@ int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector int bpc); u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, + enum intel_output_format output_format, int num_joined_pipes); int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, struct intel_connector *connector, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2bd33e1b318e..794a5121e661 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -172,6 +172,7 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec return intel_dp_dsc_get_slice_count(connector, adjusted_mode->clock, adjusted_mode->hdisplay, + crtc_state->output_format, num_joined_pipes); } @@ -1538,6 +1539,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, intel_dp_dsc_get_slice_count(intel_connector, target_clock, mode->hdisplay, + INTEL_OUTPUT_FORMAT_RGB, num_joined_pipes); } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 9eaf608995dc..0aa2d96ee329 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1041,6 +1041,22 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); } +bool intel_dsc_can_use_pixel_replication(struct intel_display *display, + int mode_hdisplay, u8 slice_count, + enum intel_output_format output_format) +{ + int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count); + + if (!HAS_PIXEL_REPLICATION(display)) + return false; + + /* Odd slice width is not supported by YCbCr420 format */ + if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return false; + + return true; +} + int intel_dsc_get_replicated_pixels(struct intel_display *display, int mode_hdisplay, int slice_count, @@ -1049,11 +1065,10 @@ int intel_dsc_get_replicated_pixels(struct intel_display *display, int replicated_pixels; int slice_width = DIV_ROUND_UP(mode_hdisplay, slice_count); - if (!HAS_PIXEL_REPLICATION(display)) - return 0; - - /* Odd slice width is not supported by YCbCr420 format */ - if (slice_width % 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + if (!intel_dsc_can_use_pixel_replication(display, + mode_hdisplay, + slice_count, + output_format)) return 0; replicated_pixels = (slice_width * slice_count) - mode_hdisplay; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 41b8b5c5866e..3611fc53840d 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -33,6 +33,9 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); +bool intel_dsc_can_use_pixel_replication(struct intel_display *display, + int mode_hdisplay, u8 slice_count, + enum intel_output_format output_format); int intel_dsc_get_replicated_pixels(struct intel_display *display, int mode_hdisplay, int slice_count, From patchwork Wed Oct 23 06:52:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D11B4D2E018 for ; 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X-CSE-ConnectionGUID: hl6yorvDQqyLbbXEHhS2ZQ== X-CSE-MsgGUID: WnVfBjeqSU2YBTUV6bXGVw== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097502" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097502" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:06 -0700 X-CSE-ConnectionGUID: k9bGlUx7SWGh8r2lCH3ApA== X-CSE-MsgGUID: Q1SgWRQhS8u7qs9zc5Mxow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691630" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:04 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 14/16] drm/i915/dsc: Introduce odd pixel removal Date: Wed, 23 Oct 2024 12:22:55 +0530 Message-ID: <20241023065257.190035-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With 3 DSC engines we can support 12 slices. With ultra joiner usecase while dividing the width into 12 slices, we might end up having odd number of pixels per pipe. As per Bspec, pipe src size should be even, so an extra pixel is added in each pipe. For Pipe A and C the odd pixel is added at the end of pipe and for Pipe B and D it is added at the beginning of the pipe. This extra pixel needs to be dropped in Splitter hardware. Introduce bits to account for odd pixel removal while programming DSS CTL. Add a new member in crtc state to track if we need to account for the odd pixel. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 9 +++++++++ drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 2 ++ 4 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8065ed921952..bab1ab1236df 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5762,6 +5762,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(dsc.num_streams); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); PIPE_CONF_CHECK_I(dsc.replicated_pixels); + PIPE_CONF_CHECK_BOOL(dsc.has_odd_pixel); PIPE_CONF_CHECK_BOOL(splitter.enable); PIPE_CONF_CHECK_I(splitter.link_count); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 282aab2d1b5d..9a4a699d34c4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1235,6 +1235,7 @@ struct intel_crtc_state { /* Display Stream compression state */ struct { bool compression_enable; + bool has_odd_pixel; int num_streams; /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 0aa2d96ee329..71c69be7989f 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -797,6 +797,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } + if (crtc_state->dsc.has_odd_pixel) { + dss_ctl2_val |= ODD_PIXEL_REMOVAL; + if (crtc->pipe == PIPE_A || crtc->pipe == PIPE_C) + dss_ctl2_val |= ODD_PIXEL_REMOVAL_CONFIG_EOL; + } + if (crtc_state->dsc.replicated_pixels) dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.replicated_pixels); @@ -1011,6 +1017,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.num_streams = 0; } + if (dss_ctl2 & ODD_PIXEL_REMOVAL) + crtc_state->dsc.has_odd_pixel = true; + if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK) crtc_state->dsc.replicated_pixels = dss_ctl3 & DSC_PIXEL_REPLICATION_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index f07fad6239bc..9c4cf80c2064 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -24,6 +24,8 @@ #define VDSC0_ENABLE REG_BIT(31) #define VDSC2_ENABLE REG_BIT(30) #define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) +#define ODD_PIXEL_REMOVAL REG_BIT(18) +#define ODD_PIXEL_REMOVAL_CONFIG_EOL REG_BIT(17) #define VDSC1_ENABLE REG_BIT(15) #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) From patchwork Wed Oct 23 06:52:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CBF3D2E01B for ; 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X-CSE-ConnectionGUID: hHsGUVsWTxmTTwdVKGNaBA== X-CSE-MsgGUID: PWNl4TzmRH2wq5slq8cw9Q== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097509" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097509" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:07 -0700 X-CSE-ConnectionGUID: ZTSv828wTiKQNsXyr7t7Mg== X-CSE-MsgGUID: gqHKhceVRbiYF4VlEzQhSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691633" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:06 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 15/16] drm/i915/display: Adjust Pipe SRC Width for Odd Pixels Date: Wed, 23 Oct 2024 12:22:56 +0530 Message-ID: <20241023065257.190035-16-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enhance the `intel_splitter_adjust_pipe_width` helper to account for both pixel replication and odd pixels. When the display width is divided among multiple pipes, extra pixels can make the pipe source width odd. Since hardware expects an even width, an extra pixel is added to each pipe to ensure even width. The splitter hardware will remove these extra pixels. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bab1ab1236df..67dfada13eab 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2514,12 +2514,18 @@ void intel_encoder_get_config(struct intel_encoder *encoder, intel_crtc_readout_derived_state(crtc_state); } -static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels) +static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels, + bool has_odd_pixel, int num_pipes) { - /* Account for Pixel replication: + /* Account for Pixel replication + Odd pixel: * Pixel replication is required due to the rounding of slice_width (Hactive / slice_count). * - * Splitter HW takes care of these by removing replicated pixels from the last pipe. + * These extra pixels when added to the pipe source width, can make the pipe source width + * odd. Since HW expects the pipe source width to be even, therefore one extra pixel needs + * to be added to the pipe source width to make it even. + * + * Splitter HW takes care of these by removing odd pixel from each pipe and + * replicated pixels from the last pipe. */ if (!replicated_pixels) @@ -2527,7 +2533,11 @@ static int intel_splitter_adjust_pipe_width(int width, int replicated_pixels) width += replicated_pixels; - return width; + if (!has_odd_pixel) + return width; + + /* Account for one extra pixel for each pipe */ + return width + num_pipes; } static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) @@ -2539,7 +2549,9 @@ static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) return; width = intel_splitter_adjust_pipe_width(drm_rect_width(&crtc_state->pipe_src), - crtc_state->dsc.replicated_pixels); + crtc_state->dsc.replicated_pixels, + crtc_state->dsc.has_odd_pixel, + num_pipes); height = drm_rect_height(&crtc_state->pipe_src); From patchwork Wed Oct 23 06:52:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13846562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71C92D2E01B for ; Wed, 23 Oct 2024 06:51:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 174C210E75B; Wed, 23 Oct 2024 06:51:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FwYNLldY"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD7FA10E766; Wed, 23 Oct 2024 06:51:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729666269; x=1761202269; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7dfMhnorMMaNUpOgkl6t1AcTCVe+qyMxdojYeV1HHjw=; b=FwYNLldYHj54JNqkiWp226EiK7GM7XMQSCz0jt83LbHiMhwJpkzz3ml1 W6q9kIijAmdFHpFERV+jD+y5gJDqb5HTH7fbItCU4IlCipWk04w7IgQ25 MX5LgNJ0B/LaEdlB/6Ya+QpHlXNhwskPJqARvwLdN/OxoWbLoaCNfQQNJ Y8ES3ImBgz0meP4P32PLkryrSBb0FBB02lR7IYzT5qiRuxYcNMRHTzYJT QiceU8QvXvWUu/PtiBk6km0feP74ytKeWkhkis/hJ80QN3yJ+UqZrynRs 1R/RZ5ep2OiN28TfQ5yOzQ6+E11MxvrGsSDfjdUlRh8A8sqCc8YJrmfVj g==; X-CSE-ConnectionGUID: 5yQ6rXjZRx2QzugtwuVgNg== X-CSE-MsgGUID: 22Hofui4Qx2jfv3V/nwUJg== X-IronPort-AV: E=McAfee;i="6700,10204,11233"; a="32097514" X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="32097514" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:09 -0700 X-CSE-ConnectionGUID: bs0cH3j6QUKHK1+rOy2O+g== X-CSE-MsgGUID: bmEoADb8QcCtKFCxr7/CfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,225,1725346800"; d="scan'208";a="84691640" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2024 23:51:07 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, suraj.kandpal@intel.com Subject: [PATCH 16/16] drm/i915/dp: Add Check for Odd Pixel Requirement Date: Wed, 23 Oct 2024 12:22:57 +0530 Message-ID: <20241023065257.190035-17-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> References: <20241023065257.190035-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Check if Odd pixel is required during DSC compute config and update the crtc_state to track the presence of odd pixels. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 026254687a8d..b512e2dd9b37 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2366,6 +2366,14 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, return 0; } +static bool intel_dp_dsc_needs_odd_pixel(int hdisplay, int replicated_pixels, int num_pipes) +{ + if (!replicated_pixels || num_pipes == 1) + return false; + + return ((hdisplay + replicated_pixels) / num_pipes) % 2; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -2452,6 +2460,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_hdisplay, pipe_config->dsc.slice_count, pipe_config->output_format); + pipe_config->dsc.has_odd_pixel = + intel_dp_dsc_needs_odd_pixel(adjusted_mode->crtc_hdisplay, + pipe_config->dsc.replicated_pixels, + num_joined_pipes); /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate