From patchwork Wed Oct 23 13:21:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13847092 Received: from out-180.mta0.migadu.com (out-180.mta0.migadu.com [91.218.175.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9A931AB6ED for ; Wed, 23 Oct 2024 13:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689703; cv=none; b=fkhRjPzfnbgIPobo5/iQrXIiv6xsGWei4oW3vjBZR9JjjsHt6BwmDrByyWNMSbwfOzqHa60FbHG4AF/Sif0AOgaSoEDvx25MCV5iF5BGf4YlRH9tSUbtYltT8NeHj9onwtmMYJqO1EcVLZn003Jvawq18PWPXjHJ3DtSeFQrgyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689703; c=relaxed/simple; bh=eproeieP2guIsENpttWunUHTCzySL//7W9mGNrZ9PHk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hagKcs4cb7KuBqYt6huK0QUo3fFoDyY18Bzi/5VPOmxfJ2LqoRHfi3Pr2BwVmdr/8GNFzOOiwKG5yOyK2UlZ+6QbwmWVV/3WXX69AoBlbp8hGPBsuNC9ANc0Sg+imTc6bQnxhDJPeIiEJO5OhtxSLjFmjfgYqShr4WdDcKKDh6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Px1Hzl1g; arc=none smtp.client-ip=91.218.175.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Px1Hzl1g" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729689699; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cgbOwzQMc+kT3Z3Q0ZRUFULWs2irjvHdzSBuM71eWkA=; b=Px1Hzl1g/+LfykaXLvfKi/Q5H4a9cxu4Y09Q8bOiHxdQLRulSY0CEfWMWiCgDwsY86tLX+ Xb4hLvZViQVV8G22QsYzbBEJIzUWGvi4ldLpc9HHBJQSR11Oq9c/zMiaASLUFShQ9Jo8S9 MoP4nX+6zLozg9m+Q6gywE7JM9eqKzg= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 1/4] riscv: Bump NR_CPUS to 256 Date: Wed, 23 Oct 2024 15:21:32 +0200 Message-ID: <20241023132130.118073-7-andrew.jones@linux.dev> In-Reply-To: <20241023132130.118073-6-andrew.jones@linux.dev> References: <20241023132130.118073-6-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Besides a bit more memory used for the .bss section, where there are NR_CPUS sized arrays, and a tiny bit more stack used by functions with cpumasks on their stacks, then there's no harm in bumping NR_CPUS. Bump it to 256, which should cover us for quite a while. Signed-off-by: Andrew Jones --- lib/riscv/asm/setup.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/riscv/asm/setup.h b/lib/riscv/asm/setup.h index a13159bfe395..a031ebe7d762 100644 --- a/lib/riscv/asm/setup.h +++ b/lib/riscv/asm/setup.h @@ -4,7 +4,7 @@ #include #include -#define NR_CPUS 16 +#define NR_CPUS 256 extern struct thread_info cpus[NR_CPUS]; extern int nr_cpus; extern uint64_t timebase_frequency; From patchwork Wed Oct 23 13:21:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13847093 Received: from out-179.mta0.migadu.com (out-179.mta0.migadu.com [91.218.175.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68BC31AE00B for ; Wed, 23 Oct 2024 13:21:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689706; cv=none; b=rOM8lrDHuIGuwWYz6p4E9RUWOyv/iaJa8GzisT6zMQ8BmoAn1vmw2/2DjQYrCLXjq73RQsD3sQMJfRfdP/wtA+Aox92YH2KDCOpmZbLe4WWPTj8twzmX/tZ7o40J83//HMyHhI1XuAWyTfM/V7Zw1kVJaLs5ANFrDT3fngvCIHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689706; c=relaxed/simple; bh=q/5dHEBagCDK99UL3gUlS2h98GdDCGGJRpsxT6/3e3A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ogI2vpbSArrWoBOqMgyuZSPPmLPooSWGDzbExA6lpSaVR2gPD/DklU1hwZDnBaQlMkcIBh8gX1HGzOIHv4+K2xvRQiwqGcQeh1chTm3JK/ZMwdfOjxi37VHNBt4su3WipqCB7Bhs3hQDrP2+rFjIYtp7eh9BlX0GtkulHxGqmY0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=FdSutKbr; arc=none smtp.client-ip=91.218.175.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="FdSutKbr" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729689702; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v4n6iXUzuE7MoPSEF0ddVeFcFHlzBfHTUGSIQ/G9qu4=; b=FdSutKbr+n7M6TgBthyAaF8qcxESYQIgxvYeGZ+VnbE5FGkNMTj03ppIQK0dBEhU0SJX8c GcO3or5UYcOlpvUf9pjn4G14pI3zsdoptmz/+ffm7JvRD46wRwZaEflil76u3t8Ru/4uV4 WzTzSm5NZStcGTGjB2xES9P1eBCwaYU= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 2/4] riscv: Filter unmanaged harts from present mask Date: Wed, 23 Oct 2024 15:21:33 +0200 Message-ID: <20241023132130.118073-8-andrew.jones@linux.dev> In-Reply-To: <20241023132130.118073-6-andrew.jones@linux.dev> References: <20241023132130.118073-6-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT We use SBI to manage harts and SBI may have a different idea of which harts it should manage than our hardware description. Filter out all harts which fail an SBI HSM status call from the present mask to ensure we don't try to use them. Signed-off-by: Andrew Jones --- lib/riscv/setup.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/lib/riscv/setup.c b/lib/riscv/setup.c index f347ad6352d7..211945448b0f 100644 --- a/lib/riscv/setup.c +++ b/lib/riscv/setup.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -51,7 +52,9 @@ static void cpu_set_fdt(int fdtnode __unused, u64 regval, void *info __unused) cpus[cpu].cpu = cpu; cpus[cpu].hartid = regval; - set_cpu_present(cpu, true); + + if (!sbi_hart_get_status(cpus[cpu].hartid).error) + set_cpu_present(cpu, true); } static void cpu_init_acpi(void) @@ -61,7 +64,7 @@ static void cpu_init_acpi(void) static void cpu_init(void) { - int ret; + int ret, me; nr_cpus = 0; if (dt_available()) { @@ -71,7 +74,9 @@ static void cpu_init(void) cpu_init_acpi(); } - set_cpu_online(hartid_to_cpu(csr_read(CSR_SSCRATCH)), true); + me = hartid_to_cpu(csr_read(CSR_SSCRATCH)); + assert(cpu_present(me)); + set_cpu_online(me, true); cpu0_calls_idle = true; } From patchwork Wed Oct 23 13:21:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13847094 Received: from out-171.mta1.migadu.com (out-171.mta1.migadu.com [95.215.58.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC1541AE018 for ; Wed, 23 Oct 2024 13:21:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689708; cv=none; b=Dg5u+W7w8E2lB/bVfu5ENU613ThquPHaTT6NkognzxINW0aOKb+fkBmHu5OpjyUhjaGuFbAKVkZsCHHB+THK1Nk4LbVND5vZIkILN7dRIrwxKMe060WLmaqXqELI/Jo4jaHScwL7xgPAUfpX6Ssg3bPvvrVFkAPJM+L5KlaoqRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689708; c=relaxed/simple; bh=uGy2Tdom1P6MSr0n5d/7evDoV1fqiacc+jFCAfkZUJc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tHAZgG8nT3ng6gvIM7cVnWMRH7DuXLMvSO7h2Xf2CGx9OGhW+D/DCAhpoJt6Hs3RZ0OQMK5/I08ullmd1RwvcZDuobRhWPgGbaz4Vevdlc38EUpxiddkpN0g/iYgwvNpslp2sC1bx5Scu4Re+qKOREmtT62R5FBi8znYEQtnn0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=puXWbn4x; arc=none smtp.client-ip=95.215.58.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="puXWbn4x" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729689705; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=b5ln1rtoJpJgmzh9v/JiEP0bJ5A/bzOlNsyfFTmukE8=; b=puXWbn4xIhdKnF680eXYpH/Za5XvN8PIQP1A+r4RVPvZLOXs+bUNevUYLEIxJRdF6zb/76 YFSi7aYuhCD6TWaHY7FzEFkxgl20VPJdsL0le6JkO4osu1xFcilwK2XaN3YOjjkfoDvAat GGNVSx/KORH+vr2TCIhJL4DlzMHAP24= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 3/4] riscv: Fix secondary_entry Date: Wed, 23 Oct 2024 15:21:34 +0200 Message-ID: <20241023132130.118073-9-andrew.jones@linux.dev> In-Reply-To: <20241023132130.118073-6-andrew.jones@linux.dev> References: <20241023132130.118073-6-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT The last few instructions of secondary_entry had the right concept, but were the totally wrong implementation. Without setting ra, then, when the boot function doesn't stay in an infinite loop, like do_idle() would, we'd go off into the weeds when trying to return from it. Make sure we set ra to come back to where we can then call do_idle() instead. The bug was found by inspection since nobody is calling smp_boot_secondary() with anything other than do_idle() at this time. Fixes: 9c92b28e6b7b ("riscv: Add SMP support") Signed-off-by: Andrew Jones --- riscv/cstart.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv/cstart.S b/riscv/cstart.S index bae1d2f5b4d5..687173706d83 100644 --- a/riscv/cstart.S +++ b/riscv/cstart.S @@ -154,9 +154,9 @@ secondary_entry: mv a0, sp call secondary_cinit addi sp, sp, SECONDARY_DATA_SIZE - jr a0 - la a0, do_idle - jr a0 + jalr ra, a0 + call do_idle + j . /* unreachable */ /* * Save context to address in a0. From patchwork Wed Oct 23 13:21:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13847095 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 651331AC8AE for ; Wed, 23 Oct 2024 13:21:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689713; cv=none; b=XxpLd5wRwcJVrSZQrZQYNXTt45Jc0UWj8wGmJsoQIJmDaF20WAyfu6NcSGvDXzK005knCg/CaK69xsSbq3VBehHxww7QsA85/4q2oAh+sAgpZ9Q/S2WXA1WG6sRXApCbLXTnl4zDIjiXBGoyhXCSEyz427SFIoak9mdTvLjfcao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729689713; c=relaxed/simple; bh=MydZWpquF4n+CRZGVxGaYdwOH4b7Q8U/Iy+qcqVU8z4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ps4yWf+NGokkiG1m/R45dt/xCnRYTsYxzAGb6F62cGJEyAilT2KYYnhv6MeWoN3vMNCcbR2qlykifkmpf9pxZgAdKbHk1LCQbrqKl/lzu3zI1Kh6/JRtSLo882D7dWINQid/lqEnImlLj3nkZED7KUo22y/Xe+t7VEgY7Qqe5CE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=BQBr5S2s; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="BQBr5S2s" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1729689709; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Nh3KjWy9iMLDSdx8xjwI08CQw6sxDmd7hGwJRrvc7UY=; b=BQBr5S2scTAX50tMufJcEaRHKgZpnuxvgRQu9C1Jd1mV8mWocl9ZFdfJmp/IyoVLry3WUp ULv8gkcqYuPVLaCrF4SAGTTSPCmXj6GadHS9EKMk1T3TjiSXachK7D9a+CHsvYJA9clEs9 8G11q7tXV5VQmWqGBzPRjjjBKQ/JBgU= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: atishp@rivosinc.com, jamestiotio@gmail.com Subject: [kvm-unit-tests PATCH 4/4] riscv: Rework smp_boot_secondary Date: Wed, 23 Oct 2024 15:21:35 +0200 Message-ID: <20241023132130.118073-10-andrew.jones@linux.dev> In-Reply-To: <20241023132130.118073-6-andrew.jones@linux.dev> References: <20241023132130.118073-6-andrew.jones@linux.dev> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Use HSM status to determine when a secondary should be started. Also save the stack pointer so a secondary may be stopped and started again without leaking old stacks. Signed-off-by: Andrew Jones --- lib/riscv/asm/processor.h | 1 + lib/riscv/smp.c | 49 +++++++++++++++++++++++++++------------ riscv/cstart.S | 1 + 3 files changed, 36 insertions(+), 15 deletions(-) diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 4063255a3475..401042724cee 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -13,6 +13,7 @@ struct thread_info { int cpu; unsigned long hartid; unsigned long isa[1]; + unsigned long sp; exception_fn exception_handlers[EXCEPTION_CAUSE_MAX]; exception_fn interrupt_handlers[INTERRUPT_CAUSE_MAX]; }; diff --git a/lib/riscv/smp.c b/lib/riscv/smp.c index eb7061abfe7f..e92f83e1310d 100644 --- a/lib/riscv/smp.c +++ b/lib/riscv/smp.c @@ -19,8 +19,6 @@ cpumask_t cpu_present_mask; cpumask_t cpu_online_mask; cpumask_t cpu_idle_mask; -static cpumask_t cpu_started; - secondary_func_t secondary_cinit(struct secondary_data *data) { struct thread_info *info; @@ -37,27 +35,40 @@ secondary_func_t secondary_cinit(struct secondary_data *data) static void __smp_boot_secondary(int cpu, secondary_func_t func) { - struct secondary_data *sp = alloc_pages(1) + SZ_8K - 16; - phys_addr_t sp_phys; + void *sp_mem = (void *)cpus[cpu].sp; + struct secondary_data *data; struct sbiret ret; - sp -= sizeof(struct secondary_data); - sp->satp = csr_read(CSR_SATP); - sp->stvec = csr_read(CSR_STVEC); - sp->func = func; + if (!sp_mem) { + phys_addr_t sp_phys; + + sp_mem = alloc_pages(1) + SZ_8K - 16; + sp_phys = virt_to_phys(sp_mem); + cpus[cpu].sp = __pa(sp_phys); - sp_phys = virt_to_phys(sp); - assert(sp_phys == __pa(sp_phys)); + assert(sp_phys == cpus[cpu].sp); + } - ret = sbi_hart_start(cpus[cpu].hartid, (unsigned long)&secondary_entry, __pa(sp_phys)); + sp_mem -= sizeof(struct secondary_data); + data = (struct secondary_data *)sp_mem; + data->satp = csr_read(CSR_SATP); + data->stvec = csr_read(CSR_STVEC); + data->func = func; + + ret = sbi_hart_start(cpus[cpu].hartid, (unsigned long)&secondary_entry, cpus[cpu].sp); assert(ret.error == SBI_SUCCESS); } void smp_boot_secondary(int cpu, void (*func)(void)) { - int ret = cpumask_test_and_set_cpu(cpu, &cpu_started); + struct sbiret ret; - assert_msg(!ret, "CPU%d already boot once", cpu); + do { + ret = sbi_hart_get_status(cpus[cpu].hartid); + assert(!ret.error); + } while (ret.value == SBI_EXT_HSM_STOP_PENDING); + + assert_msg(ret.value == SBI_EXT_HSM_STOPPED, "CPU%d is not stopped", cpu); __smp_boot_secondary(cpu, func); while (!cpu_online(cpu)) @@ -66,10 +77,18 @@ void smp_boot_secondary(int cpu, void (*func)(void)) void smp_boot_secondary_nofail(int cpu, void (*func)(void)) { - int ret = cpumask_test_and_set_cpu(cpu, &cpu_started); + struct sbiret ret; + + do { + ret = sbi_hart_get_status(cpus[cpu].hartid); + assert(!ret.error); + } while (ret.value == SBI_EXT_HSM_STOP_PENDING); - if (!ret) + if (ret.value == SBI_EXT_HSM_STOPPED) __smp_boot_secondary(cpu, func); + else + assert_msg(ret.value == SBI_EXT_HSM_START_PENDING || ret.value == SBI_EXT_HSM_STARTED, + "CPU%d is in an unexpected state %ld", cpu, ret.value); while (!cpu_online(cpu)) smp_wait_for_event(); diff --git a/riscv/cstart.S b/riscv/cstart.S index 687173706d83..b7ee9b9c96b3 100644 --- a/riscv/cstart.S +++ b/riscv/cstart.S @@ -149,6 +149,7 @@ secondary_entry: csrw CSR_SSCRATCH, a0 mv sp, a1 mv fp, zero + addi sp, sp, -SECONDARY_DATA_SIZE REG_L a0, SECONDARY_STVEC(sp) csrw CSR_STVEC, a0 mv a0, sp