From patchwork Thu Oct 24 06:49:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13848388 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6945170A01; Thu, 24 Oct 2024 06:50:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; cv=none; b=YS5aIecDUsVKd36kHyco7qJXoCScB0b09bSVF63mCJUwGqgQqH4raDTbtHptSSP9Ds81lJ7Td9dIdg4KesjJDa9pM11lz7NVtpjfdPxhJxSxYfeOHplR1BxvcXWCyngwjqXox2+tKKMzcw94HHmUETt8Q1tEkr6nFigC74zR9QA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; c=relaxed/simple; bh=xdW+RqS+KhtO8Xn8g+KLEKZQeyEVDoJBGhd9KwYVrMU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Hth67WRvw4tDnhcTN2c0Qb1q2/zZZWaKXmxpNdWo1ojHvG1lDYA+IxUMjIW5Y24pK71KkMdlm5LLqdznnC51VRyOL52PujMIDDmFR9a2OuSDMUV0PqD1IoHWwboE2xVDrXK8zgTzh6FdXQNw/HpeQJeorGcMEApkovlBV1r5rHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=P7Y64DeD; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="P7Y64DeD" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id EB52FA0472; Thu, 24 Oct 2024 08:50:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=9kcK20iVik8G/2yaDlCQ en7V77J/07VB3CEhNbKk+Vw=; b=P7Y64DeDUMDqV1+fL/v79QtAS8b947qyfv6t Ob/DszJW4BfnVQO+ZIuPHyztgQ3JIMVggJPvomUP2gaeQ3hUb7knnSe6v5dqa4Qh ZN1WvNNo0LGePmeN9sgVTo6fbB1q/0Vu+s3O3z2yGi4DqOvgANAx8hBrzbg99uvY sYOrb6jf0BTOBxnOqDHH8aLvSEnC/KkYOvhP1a1ryfmzv4+T7jm9WUE687MmUa+H 6pQDX01uQ/Vvs903jKxzFgTaVil/pgwL+Wy67+7qQuQivLg3CmYjsOpYaFMG/WDX An0dD3MJ+k1luI83rnvOCf2z8/7tXVWi6v80A+N4PkHN4h2FhlaYbOltBSiF7p1c +9myPLMYW2WcsidjqAaVC4nKuDIKIr9Lt5qYYpeSXh8UoWTpb4cHMBuReDJlUPQZ fCxCB5eIzz+qa5AZyOQ639kOYO8D5xXc+nANu5ddvP2wQqbS5q3QcRnxBYfxNvlB hwVaUIxRxhxXv5rmU+Gf4W9+4OLnDJRUQ/5r7AbRGWJXjtyzy4G+F9XOAp5Y8cEa /Oeb8rjCJc0iugjpqLzxTsaHDVeEjkBr2L73QWgnA27iG5VYgCaTs3E4ueAT79pb cnybZMvJ3ES0hLk0M91AmcRmFr/CzreGhSc5WmjNFdlR6kQsRzCwH/FLcwzLvnHm DGJx+A8= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: , , , CC: Mesih Kilinc , =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [PATCH 01/10] dma-engine: sun4i: Add a quirk to support different chips Date: Thu, 24 Oct 2024 08:49:22 +0200 Message-ID: <20241024064931.1144605-2-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <13ab5cec-25e5-4e82-b956-5c154641d7ab@prolan.hu> References: Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1729752648;VERSION=7978;MC=3262522948;ID=135548;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677065 From: Mesih Kilinc Allwinner suniv F1C100s has similar DMA engine to sun4i. Several registers has different addresses. Total dma channels, endpoint counts and max burst counts are also different. In order to support F1C100s add a quirk structure to hold IC specific data. Signed-off-by: Mesih Kilinc [ csokas.bence: Resolve conflict in `sun4i_dma_prep_dma_cyclic()`, fix whitespace ] Signed-off-by: Csókás, Bence --- drivers/dma/sun4i-dma.c | 138 ++++++++++++++++++++++++++++++---------- 1 file changed, 106 insertions(+), 32 deletions(-) diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index 2e7f9b07fdd2..5efbed7c546f 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,8 @@ #define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5) #define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type) +#define SUN4I_MAX_BURST 8 + /** Normal DMA register values **/ /* Normal DMA source/destination data request type values */ @@ -132,6 +135,32 @@ #define SUN4I_DDMA_MAX_SEG_SIZE SZ_16M #define SUN4I_DMA_MAX_SEG_SIZE SUN4I_NDMA_MAX_SEG_SIZE +/* + * Hardware channels / ports representation + * + * The hardware is used in several SoCs, with differing numbers + * of channels and endpoints. This structure ties those numbers + * to a certain compatible string. + */ +struct sun4i_dma_config { + u32 ndma_nr_max_channels; + u32 ndma_nr_max_vchans; + + u32 ddma_nr_max_channels; + u32 ddma_nr_max_vchans; + + u32 dma_nr_max_channels; + + void (*set_dst_data_width)(u32 *p_cfg, s8 data_width); + void (*set_src_data_width)(u32 *p_cfg, s8 data_width); + int (*convert_burst)(u32 maxburst); + + u8 ndma_drq_sdram; + u8 ddma_drq_sdram; + + u8 max_burst; +}; + struct sun4i_dma_pchan { /* Register base of channel */ void __iomem *base; @@ -170,7 +199,7 @@ struct sun4i_dma_contract { }; struct sun4i_dma_dev { - DECLARE_BITMAP(pchans_used, SUN4I_DMA_NR_MAX_CHANNELS); + unsigned long *pchans_used; struct dma_device slave; struct sun4i_dma_pchan *pchans; struct sun4i_dma_vchan *vchans; @@ -178,6 +207,7 @@ struct sun4i_dma_dev { struct clk *clk; int irq; spinlock_t lock; + const struct sun4i_dma_config *cfg; }; static struct sun4i_dma_dev *to_sun4i_dma_dev(struct dma_device *dev) @@ -200,7 +230,17 @@ static struct device *chan2dev(struct dma_chan *chan) return &chan->dev->device; } -static int convert_burst(u32 maxburst) +static void set_dst_data_width_a10(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUN4I_DMA_CFG_DST_DATA_WIDTH(data_width); +} + +static void set_src_data_width_a10(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(data_width); +} + +static int convert_burst_a10(u32 maxburst) { if (maxburst > 8) return -EINVAL; @@ -233,15 +273,15 @@ static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv, int i, max; /* - * pchans 0-SUN4I_NDMA_NR_MAX_CHANNELS are normal, and - * SUN4I_NDMA_NR_MAX_CHANNELS+ are dedicated ones + * pchans 0-priv->cfg->ndma_nr_max_channels are normal, and + * priv->cfg->ndma_nr_max_channels+ are dedicated ones */ if (vchan->is_dedicated) { - i = SUN4I_NDMA_NR_MAX_CHANNELS; - max = SUN4I_DMA_NR_MAX_CHANNELS; + i = priv->cfg->ndma_nr_max_channels; + max = priv->cfg->dma_nr_max_channels; } else { i = 0; - max = SUN4I_NDMA_NR_MAX_CHANNELS; + max = priv->cfg->ndma_nr_max_channels; } spin_lock_irqsave(&priv->lock, flags); @@ -444,6 +484,7 @@ generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, size_t len, struct dma_slave_config *sconfig, enum dma_transfer_direction direction) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_promise *promise; int ret; @@ -467,13 +508,13 @@ generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, sconfig->src_addr_width, sconfig->dst_addr_width); /* Source burst */ - ret = convert_burst(sconfig->src_maxburst); + ret = priv->cfg->convert_burst(sconfig->src_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_SRC_BURST_LENGTH(ret); /* Destination burst */ - ret = convert_burst(sconfig->dst_maxburst); + ret = priv->cfg->convert_burst(sconfig->dst_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_DST_BURST_LENGTH(ret); @@ -482,13 +523,13 @@ generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, ret = convert_buswidth(sconfig->src_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(ret); + priv->cfg->set_src_data_width(&promise->cfg, ret); /* Destination bus width */ ret = convert_buswidth(sconfig->dst_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_DST_DATA_WIDTH(ret); + priv->cfg->set_dst_data_width(&promise->cfg, ret); return promise; @@ -510,6 +551,7 @@ static struct sun4i_dma_promise * generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, size_t len, struct dma_slave_config *sconfig) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_promise *promise; int ret; @@ -524,13 +566,13 @@ generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, SUN4I_DDMA_CFG_BYTE_COUNT_MODE_REMAIN; /* Source burst */ - ret = convert_burst(sconfig->src_maxburst); + ret = priv->cfg->convert_burst(sconfig->src_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_SRC_BURST_LENGTH(ret); /* Destination burst */ - ret = convert_burst(sconfig->dst_maxburst); + ret = priv->cfg->convert_burst(sconfig->dst_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_DST_BURST_LENGTH(ret); @@ -539,13 +581,13 @@ generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, ret = convert_buswidth(sconfig->src_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(ret); + priv->cfg->set_src_data_width(&promise->cfg, ret); /* Destination bus width */ ret = convert_buswidth(sconfig->dst_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_DST_DATA_WIDTH(ret); + priv->cfg->set_dst_data_width(&promise->cfg, ret); return promise; @@ -622,6 +664,7 @@ static struct dma_async_tx_descriptor * sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan); struct dma_slave_config *sconfig = &vchan->cfg; struct sun4i_dma_promise *promise; @@ -638,8 +681,8 @@ sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, */ sconfig->src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; sconfig->dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - sconfig->src_maxburst = 8; - sconfig->dst_maxburst = 8; + sconfig->src_maxburst = priv->cfg->max_burst; + sconfig->dst_maxburst = priv->cfg->max_burst; if (vchan->is_dedicated) promise = generate_ddma_promise(chan, src, dest, len, sconfig); @@ -654,11 +697,13 @@ sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, /* Configure memcpy mode */ if (vchan->is_dedicated) { - promise->cfg |= SUN4I_DMA_CFG_SRC_DRQ_TYPE(SUN4I_DDMA_DRQ_TYPE_SDRAM) | - SUN4I_DMA_CFG_DST_DRQ_TYPE(SUN4I_DDMA_DRQ_TYPE_SDRAM); + promise->cfg |= + SUN4I_DMA_CFG_SRC_DRQ_TYPE(priv->cfg->ddma_drq_sdram) | + SUN4I_DMA_CFG_DST_DRQ_TYPE(priv->cfg->ddma_drq_sdram); } else { - promise->cfg |= SUN4I_DMA_CFG_SRC_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM) | - SUN4I_DMA_CFG_DST_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM); + promise->cfg |= + SUN4I_DMA_CFG_SRC_DRQ_TYPE(priv->cfg->ndma_drq_sdram) | + SUN4I_DMA_CFG_DST_DRQ_TYPE(priv->cfg->ndma_drq_sdram); } /* Fill the contract with our only promise */ @@ -673,6 +718,7 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len, size_t period_len, enum dma_transfer_direction dir, unsigned long flags) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan); struct dma_slave_config *sconfig = &vchan->cfg; struct sun4i_dma_promise *promise; @@ -696,11 +742,11 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len, if (vchan->is_dedicated) { io_mode = SUN4I_DDMA_ADDR_MODE_IO; linear_mode = SUN4I_DDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_DDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ddma_drq_sdram; } else { io_mode = SUN4I_NDMA_ADDR_MODE_IO; linear_mode = SUN4I_NDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_NDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ndma_drq_sdram; } if (dir == DMA_MEM_TO_DEV) { @@ -793,6 +839,7 @@ sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction dir, unsigned long flags, void *context) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan); struct dma_slave_config *sconfig = &vchan->cfg; struct sun4i_dma_promise *promise; @@ -818,11 +865,11 @@ sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, if (vchan->is_dedicated) { io_mode = SUN4I_DDMA_ADDR_MODE_IO; linear_mode = SUN4I_DDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_DDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ddma_drq_sdram; } else { io_mode = SUN4I_NDMA_ADDR_MODE_IO; linear_mode = SUN4I_NDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_NDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ndma_drq_sdram; } if (dir == DMA_MEM_TO_DEV) @@ -1150,6 +1197,10 @@ static int sun4i_dma_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + priv->cfg = of_device_get_match_data(&pdev->dev); + if (!priv->cfg) + return -ENODEV; + priv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); @@ -1197,23 +1248,26 @@ static int sun4i_dma_probe(struct platform_device *pdev) priv->slave.dev = &pdev->dev; - priv->pchans = devm_kcalloc(&pdev->dev, SUN4I_DMA_NR_MAX_CHANNELS, + priv->pchans = devm_kcalloc(&pdev->dev, priv->cfg->dma_nr_max_channels, sizeof(struct sun4i_dma_pchan), GFP_KERNEL); priv->vchans = devm_kcalloc(&pdev->dev, SUN4I_DMA_NR_MAX_VCHANS, sizeof(struct sun4i_dma_vchan), GFP_KERNEL); - if (!priv->vchans || !priv->pchans) + priv->pchans_used = devm_kcalloc(&pdev->dev, + BITS_TO_LONGS(priv->cfg->dma_nr_max_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!priv->vchans || !priv->pchans || !priv->pchans_used) return -ENOMEM; /* - * [0..SUN4I_NDMA_NR_MAX_CHANNELS) are normal pchans, and - * [SUN4I_NDMA_NR_MAX_CHANNELS..SUN4I_DMA_NR_MAX_CHANNELS) are + * [0..priv->cfg->ndma_nr_max_channels) are normal pchans, and + * [priv->cfg->ndma_nr_max_channels..priv->cfg->dma_nr_max_channels) are * dedicated ones */ - for (i = 0; i < SUN4I_NDMA_NR_MAX_CHANNELS; i++) + for (i = 0; i < priv->cfg->ndma_nr_max_channels; i++) priv->pchans[i].base = priv->base + SUN4I_NDMA_CHANNEL_REG_BASE(i); - for (j = 0; i < SUN4I_DMA_NR_MAX_CHANNELS; i++, j++) { + for (j = 0; i < priv->cfg->dma_nr_max_channels; i++, j++) { priv->pchans[i].base = priv->base + SUN4I_DDMA_CHANNEL_REG_BASE(j); priv->pchans[i].is_dedicated = 1; @@ -1284,8 +1338,28 @@ static void sun4i_dma_remove(struct platform_device *pdev) clk_disable_unprepare(priv->clk); } +static struct sun4i_dma_config sun4i_a10_dma_cfg = { + .ndma_nr_max_channels = SUN4I_NDMA_NR_MAX_CHANNELS, + .ndma_nr_max_vchans = SUN4I_NDMA_NR_MAX_VCHANS, + + .ddma_nr_max_channels = SUN4I_DDMA_NR_MAX_CHANNELS, + .ddma_nr_max_vchans = SUN4I_DDMA_NR_MAX_VCHANS, + + .dma_nr_max_channels = SUN4I_NDMA_NR_MAX_CHANNELS + + SUN4I_DDMA_NR_MAX_CHANNELS, + + .set_dst_data_width = set_dst_data_width_a10, + .set_src_data_width = set_src_data_width_a10, + .convert_burst = convert_burst_a10, + + .ndma_drq_sdram = SUN4I_NDMA_DRQ_TYPE_SDRAM, + .ddma_drq_sdram = SUN4I_DDMA_DRQ_TYPE_SDRAM, + + .max_burst = SUN4I_MAX_BURST, +}; + static const struct of_device_id sun4i_dma_match[] = { - { .compatible = "allwinner,sun4i-a10-dma" }, + { .compatible = "allwinner,sun4i-a10-dma", .data = &sun4i_a10_dma_cfg }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun4i_dma_match); From patchwork Thu Oct 24 06:49:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13848385 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CBC7175D50; Thu, 24 Oct 2024 06:50:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; cv=none; b=Kq1EGevZemEf70ceGglzyleAnL6lYciGvX5miKkHO8UM3EQeYo46qcvPqI1RhooEU4byAFcKoLtbww/yLjoCDH01D0HHuDC3dyNmp0TJQ2mSC3GiIMg46r4EbSKTJ9T7zUcEk1bC6L/GUWFjdOo9r21gqumVHXp/buLtiCnTjMw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; c=relaxed/simple; bh=OfqqZUFbF5ur/gCAQtvYoTBdw4wYk5M2eXPxex2njbk=; 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Thu, 24 Oct 2024 08:50:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=oEkMkOoeysYlj2KcLEx7 PgbymfxkS+ZogQhGsMWtRJg=; b=Bl5t6sXlV7X7dFZwUX7P84yQLLobWyw7Phyu nSrBStmsWPT3XVu1X/e3SQQcSNCwni+VYLTYRx0VqE9vb5mHbTVOBDw9MWGeo1+H eShqSzLPp8JIf9rSONfy5rMnz5PpviAoNab/1JGqPQiIpCWzMUsg/Qx/UOCRWDlO cc7yBgoA4FKpNJX5FK7YXtszRsUiBoZt35nRdYI9JWfSFlFhQl1Q4rNu5HJ95QsH es7ToRb1//C48ozqxsqGQzLftikhVmd3YM44GsFPYmlIBZVnafjobrTBWhwO27HG fg01OM9FZTuBldilzijhWw5Rh+wXHcYx6hQtrd/OogQGBeQDQ9L+S7D3KvYBkz5x YAhQ8XiYptVXqGDmquyoroWqkQWcC03U13FVWakAm7NFOsvzgQjYWTcPeQ9govol q5L6dJ2iwrLOF65uPr7jzkPXhpic1YS3AWbNpvNnLTItsV2SYJJSASDNEjuuUW94 VCNL3XjyFz24X41tJ1pXgCPAKZ7F9Xlm3Ts7fCbkEVE6Nk2kqOeGqrEJg7Udej0s wru7pNVPI1CJJ0XcZxRM5pKYH3GME9njP0ROuKcZLwMZrk8a7F5iY81j/a07/UbY F1zBSa8IaVHuHoYdwA/cEKvID8TynioDTcIrtp0vJRZ8v8v+PkXxyn5PRXcPHb7L 2402iN0= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: , , , CC: Mesih Kilinc , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Subject: [PATCH 02/10] dma-engine: sun4i: Add has_reset option to quirk Date: Thu, 24 Oct 2024 08:49:23 +0200 Message-ID: <20241024064931.1144605-3-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <13ab5cec-25e5-4e82-b956-5c154641d7ab@prolan.hu> References: Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1729752650;VERSION=7978;MC=1474290725;ID=135549;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677065 From: Mesih Kilinc Allwinner suniv F1C100s has a reset bit for DMA in CCU. Sun4i do not has this bit but in order to support suniv we need to add it. So add support for reset bit. Signed-off-by: Mesih Kilinc --- drivers/dma/sun4i-dma.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index 5efbed7c546f..0b99b3884971 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -159,6 +160,7 @@ struct sun4i_dma_config { u8 ddma_drq_sdram; u8 max_burst; + bool has_reset; }; struct sun4i_dma_pchan { @@ -208,6 +210,7 @@ struct sun4i_dma_dev { int irq; spinlock_t lock; const struct sun4i_dma_config *cfg; + struct reset_control *rst; }; static struct sun4i_dma_dev *to_sun4i_dma_dev(struct dma_device *dev) @@ -1215,6 +1218,15 @@ static int sun4i_dma_probe(struct platform_device *pdev) return PTR_ERR(priv->clk); } + if (priv->cfg->has_reset) { + priv->rst = devm_reset_control_get_exclusive(&pdev->dev, + NULL); + if (IS_ERR(priv->rst)) { + dev_err(&pdev->dev, "Failed to get reset control\n"); + return PTR_ERR(priv->rst); + } + } + platform_set_drvdata(pdev, priv); spin_lock_init(&priv->lock); @@ -1287,6 +1299,16 @@ static int sun4i_dma_probe(struct platform_device *pdev) return ret; } + /* Deassert the reset control */ + if (priv->rst) { + ret = reset_control_deassert(priv->rst); + if (ret) { + dev_err(&pdev->dev, + "Failed to deassert the reset control\n"); + goto err_clk_disable; + } + } + /* * Make sure the IRQs are all disabled and accounted for. The bootloader * likes to leave these dirty @@ -1356,6 +1378,7 @@ static struct sun4i_dma_config sun4i_a10_dma_cfg = { .ddma_drq_sdram = SUN4I_DDMA_DRQ_TYPE_SDRAM, .max_burst = SUN4I_MAX_BURST, + .has_reset = false, }; static const struct of_device_id sun4i_dma_match[] = { From patchwork Thu Oct 24 06:49:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13848387 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DE9A189911; Thu, 24 Oct 2024 06:50:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; cv=none; b=n2CgaYoC4X894XHAwqsxatYqSEIhnV9XmhqGG76ng92PCXCkSs2J86+DJHSFCzhybfn+RgDnef5mzaETDwta3NR+Wsz/4J8mboC7PCbRDCCCph7MgU4R7/Joc2am4eRS6OzIZQ6mGh3UUlqbXQnQ7CYS4il8v/+v+2ykFc7ifHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; c=relaxed/simple; bh=dp+DSjy0O9qZHwMwnoGVEI8E4uceciDPmkCtu2FWcF4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qzWjbH8DzyqtE3iZWhG0xsbAh6SBqS6BIuRPbx88hxQGVGZBYej3+3GvVl5sSKRuQeLlMzlFo2QKtHuyx9UD9yzYqCqDnSviiL/3looTpaIwdH+gQ+O1hFYQZGEbGPRs09w6pPNGT0PsriKuELw+iU7OrkC3gw/dUYPY886Ttas= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=RSD2mKmN; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="RSD2mKmN" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id C22C8A06B3; Thu, 24 Oct 2024 08:50:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=REUvKdAlvm77Y+j57Tey GIN8QeQ3OrJBLD44k4+2Y8A=; b=RSD2mKmNiQD3HVPIe4kTtusuYd9QWpcd8NQZ 2W/K+Ubbmn172cqm/rR7yt9G7bnNq3oxixEe45YKe6qUJ0zQs9UQXC59nnoiqgMT J0WF3hlZKxJmHIUTCDN0CmiIjVLaM1DpTTspSY/AV+GCychkyuAIt9E/S994WUez /uXZ7X6qKaEoW4xMR0GHkRHNqtdQjLCxcOpjWhp6ILUxCMeZ9ddhcLi5/7qmEGDx hR6lpjzoMIKfgC5F4gJIs/CKga1LtQ2bFn9IhDh0A+1/oFS4hVvHUfbysbKDxCpU +NxQnlHLX2ISI5nq4ABlfYxYEJCM9boi57vJDUBPvy/Er6qUa5M6RznA6/Q6Jjlm ZPj50sZypExkrfWca7qaFaF2ZZDu1VNwTRGX8ZltasSFfCZ5AxweU0gnOjQhaD3+ fjFOwYdd5ur+24utWJsGn8PmH1k4ILCBfImxbcEzWEangQ0kkCR7sLvZm7fyn07g jcqSv2RJ+d4yD784cqdHyxcOU49QHGDkVZlRfqq1tIHDBbPO2XgZG2o9DOpIvoym HACMF40TvjiASuvrePIJEjKbmYw89O7rp295Fj+QwMzuytmL914eFdPAWv1HkkKy BH2C0V+P6gm2p8Cc8ApgEr7hrOYQYobEPN5ntH5lHd69QuELPIwErihUTtoSJd8f CEWxfpA= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: Chen-Yu Tsai , Maxime Ripard , , , , , CC: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= , "Vinod Koul" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland Subject: [PATCH 03/10] dt-bindings: dmaengine: Add Allwinner suniv F1C100s DMA Date: Thu, 24 Oct 2024 08:49:24 +0200 Message-ID: <20241024064931.1144605-4-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <13ab5cec-25e5-4e82-b956-5c154641d7ab@prolan.hu> References: Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1729752651;VERSION=7978;MC=2906467838;ID=135550;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677065 Add compatible string for Allwinner suniv F1C100s DMA. [ csokas.bence: reimplemented in YAML ] Signed-off-by: Csókás, Bence Acked-by: Conor Dooley --- .../devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml index 02d5bd035409..9b5180c0a7c4 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml @@ -22,7 +22,9 @@ properties: number. compatible: - const: allwinner,sun4i-a10-dma + enum: + - allwinner,sun4i-a10-dma + - allwinner,suniv-f1c100s-dma reg: maxItems: 1 From patchwork Thu Oct 24 06:49:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13848386 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A54B189B97; Thu, 24 Oct 2024 06:51:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; cv=none; b=LJZoMmBjTVZwnLjVCk5b4j1DIiIbK5g50AauZ3UrNf2CiYhsDnU2MEsAtLF7rMWf6r5RgQ8cpKzvCqmhd8J6BFgjYmHrD2BkIYqyRKcBucZqFJXeGB3smBQsZOYgHOT4sn9qBwf03kJngtKxHaJnJ6zusn0T04A4W3kwmVYlAKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729752662; c=relaxed/simple; bh=PJWR+CZIGa0P6PEQdchIJleLyEnonKlBSBJjjMKwbJY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QUE/gNgOmZFCShV7lah7CKKKg0vGzlbY6Dj50vKXVH2z67e7IVKFqeuRihCQAdLdGCs2Ew3tb2Sn9yGrm0kP6n3WV5xKyZDXSfoihhnGxCatoGVFS2KD7jYtj98KpXDeJ+gh4wZ6RcbB46zg2S8PCIFvIxw17EazGOayR1usgU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=lJfHRNt2; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="lJfHRNt2" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id 0EAD8A0748; Thu, 24 Oct 2024 08:50:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=bCOr7HBIDtYy/EPAaUt7 c9PayAvfuOB03DwDU0g3UPM=; b=lJfHRNt2gV+vLdQHCvrRxzwzyWw5YofL0NdD kFUJ6J+duzj9cIn2Eqou78Kyvq0XSUdZrQzbkppjhIsTXQafzgFCubN0VhyUe60R rJsqACo8V9HIMRWGhUdncEGEjyHT9Z0TI91fK/9sc1aP5kPL3AUOH85ukL/tsud/ X5kyTqblHNx8fAadAqb1yHc9NWrhrBuRtynz62ja432THexTYnnpqwONxNrvMozS 54WCI/SaAXdAJyevQIAtho2t5S6iO7QUoM/4Dk6IcLFW4P3rgRZeFIUzOYJ8Uvzj 77pzd0YqIauuQRO/ZB1aEtjzep3DHKMQEJ3DaCOd51/R5DeMHDuAE1Ol58ptAUpJ mbbghC3dmwHgQPPy++s6JzsQE0uG+7kTl+A8BO1wY6b96iyGuRWkzLRMj8PX2O3R Kl2OEYqU3h9hOMucvJyZCe81UrdnjISJn8FZK6rQq9bV6//3SZycioO3gFw272sv o8SsyHY0iVUR2bwn9Io4+4RLCAO18v6iedZERkNBD1xhpXEoQ50yiJ/ryM/cTKQl ajNNfOs7j9Kz3/IOQ2ReFqGThnTS/c+749ckZtpPRx4hoLizpVaJNrAZfad5LYXH KL9JXmbvy0zOCLMW+UkYkHak0I5pccaPahl0v8yHl18Vc/oDhtQPKGZ++SK92Rtu TIsGifc= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: , , , CC: Mesih Kilinc , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [PATCH 04/10] dma-engine: sun4i: Add support for Allwinner suniv F1C100s Date: Thu, 24 Oct 2024 08:49:25 +0200 Message-ID: <20241024064931.1144605-5-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <13ab5cec-25e5-4e82-b956-5c154641d7ab@prolan.hu> References: Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1729752652;VERSION=7978;MC=3421499292;ID=135551;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677065 From: Mesih Kilinc DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4 DDMA channels and endpoints are different. Also F1C100s has reset bit for DMA in CCU. Add support for it. Signed-off-by: Mesih Kilinc --- drivers/dma/Kconfig | 4 +-- drivers/dma/sun4i-dma.c | 60 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index d9ec1e69e428..fc25bfc356f3 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -162,8 +162,8 @@ config DMA_SA11X0 config DMA_SUN4I tristate "Allwinner A10 DMA SoCs support" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I - default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV + default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV) select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index 0b99b3884971..2ffc19d93c14 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -33,7 +33,11 @@ #define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5) #define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type) +#define SUNIV_DMA_CFG_DST_DATA_WIDTH(width) ((width) << 24) +#define SUNIV_DMA_CFG_SRC_DATA_WIDTH(width) ((width) << 8) + #define SUN4I_MAX_BURST 8 +#define SUNIV_MAX_BURST 4 /** Normal DMA register values **/ @@ -41,6 +45,9 @@ #define SUN4I_NDMA_DRQ_TYPE_SDRAM 0x16 #define SUN4I_NDMA_DRQ_TYPE_LIMIT (0x1F + 1) +#define SUNIV_NDMA_DRQ_TYPE_SDRAM 0x11 +#define SUNIV_NDMA_DRQ_TYPE_LIMIT (0x17 + 1) + /** Normal DMA register layout **/ /* Dedicated DMA source/destination address mode values */ @@ -54,6 +61,9 @@ #define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15) #define SUN4I_NDMA_CFG_SRC_NON_SECURE BIT(6) +#define SUNIV_NDMA_CFG_CONT_MODE BIT(29) +#define SUNIV_NDMA_CFG_WAIT_STATE(n) ((n) << 26) + /** Dedicated DMA register values **/ /* Dedicated DMA source/destination address mode values */ @@ -66,6 +76,9 @@ #define SUN4I_DDMA_DRQ_TYPE_SDRAM 0x1 #define SUN4I_DDMA_DRQ_TYPE_LIMIT (0x1F + 1) +#define SUNIV_DDMA_DRQ_TYPE_SDRAM 0x1 +#define SUNIV_DDMA_DRQ_TYPE_LIMIT (0x9 + 1) + /** Dedicated DMA register layout **/ /* Dedicated DMA configuration register layout */ @@ -119,6 +132,11 @@ #define SUN4I_DMA_NR_MAX_VCHANS \ (SUN4I_NDMA_NR_MAX_VCHANS + SUN4I_DDMA_NR_MAX_VCHANS) +#define SUNIV_NDMA_NR_MAX_CHANNELS 4 +#define SUNIV_DDMA_NR_MAX_CHANNELS 4 +#define SUNIV_NDMA_NR_MAX_VCHANS (24 * 2 - 1) +#define SUNIV_DDMA_NR_MAX_VCHANS 10 + /* This set of SUN4I_DDMA timing parameters were found experimentally while * working with the SPI driver and seem to make it behave correctly */ #define SUN4I_DDMA_MAGIC_SPI_PARAMETERS \ @@ -243,6 +261,16 @@ static void set_src_data_width_a10(u32 *p_cfg, s8 data_width) *p_cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(data_width); } +static void set_dst_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUNIV_DMA_CFG_DST_DATA_WIDTH(data_width); +} + +static void set_src_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUNIV_DMA_CFG_SRC_DATA_WIDTH(data_width); +} + static int convert_burst_a10(u32 maxburst) { if (maxburst > 8) @@ -252,6 +280,15 @@ static int convert_burst_a10(u32 maxburst) return (maxburst >> 2); } +static int convert_burst_f1c100s(u32 maxburst) +{ + if (maxburst > 4) + return -EINVAL; + + /* 1 -> 0, 4 -> 1 */ + return (maxburst >> 2); +} + static int convert_buswidth(enum dma_slave_buswidth addr_width) { if (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) @@ -1381,8 +1418,31 @@ static struct sun4i_dma_config sun4i_a10_dma_cfg = { .has_reset = false, }; +static struct sun4i_dma_config suniv_f1c100s_dma_cfg = { + .ndma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS, + .ndma_nr_max_vchans = SUNIV_NDMA_NR_MAX_VCHANS, + + .ddma_nr_max_channels = SUNIV_DDMA_NR_MAX_CHANNELS, + .ddma_nr_max_vchans = SUNIV_DDMA_NR_MAX_VCHANS, + + .dma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS + + SUNIV_DDMA_NR_MAX_CHANNELS, + + .set_dst_data_width = set_dst_data_width_f1c100s, + .set_src_data_width = set_src_data_width_f1c100s, + .convert_burst = convert_burst_f1c100s, + + .ndma_drq_sdram = SUNIV_NDMA_DRQ_TYPE_SDRAM, + .ddma_drq_sdram = SUNIV_DDMA_DRQ_TYPE_SDRAM, + + .max_burst = SUNIV_MAX_BURST, + .has_reset = true, +}; + static const struct of_device_id sun4i_dma_match[] = { { .compatible = "allwinner,sun4i-a10-dma", .data = &sun4i_a10_dma_cfg }, + { .compatible = "allwinner,suniv-f1c100s-dma", + .data = &suniv_f1c100s_dma_cfg }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun4i_dma_match);