From patchwork Thu Oct 24 09:25:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Karl.Li" X-Patchwork-Id: 13848619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 950CDD0BB7F for ; Thu, 24 Oct 2024 09:31:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Thu, 24 Oct 2024 02:26:52 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 24 Oct 2024 17:26:47 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 24 Oct 2024 17:26:47 +0800 From: Karl.Li To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Karl Li CC: , , , , Chungying Lu , , Karl Li Subject: [PATCH 1/3] dt-bindings: mailbox: mediatek: Add apu-mailbox document Date: Thu, 24 Oct 2024 17:25:43 +0800 Message-ID: <20241024092608.431581-2-karl.li@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024092608.431581-1-karl.li@mediatek.com> References: <20241024092608.431581-1-karl.li@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--13.460500-8.000000 X-TMASE-MatchedRID: YXgS1C6OPWx/dZAjNXEbFgPZZctd3P4BWjWsWQUWzVoCsxyhR8y7CQaT alM8C773wvUxdKBGcQwRA4hwIn2MDY2WQSzu3zX3T7jCYv2QJPG7atxTbKDEIPufvd3T2+v3oAW Nnmn5m56Neg5tL2+jnh12U5je5b4a7bdBxC9wVFeBlNt4VSGvIV3HHpZF/7mweuOjdf174McfPl xxE3mQszYLbDMMWtWewKX8fpO+yjINsM5qvTUs054CIKY/Hg3AaZGo0EeYG978V77yhJRgo99pj zubZ2rHwrbXMGDYqV8kL2NLniq3NVDiHpFdHheQuDMYOBqTn6YXj2OqpTl9ta7mcBhy8Pft X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--13.460500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: DBEC2FDE3AEB68C307DBA82FD95F9BB603F9FAFD5EF28C10EC52C826E39BFB0E2000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241024_022658_339903_AEA2302D X-CRM114-Status: GOOD ( 13.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Karl Li Add apu-mailbox dt-binding document. Signed-off-by: Karl Li --- .../mailbox/mediatek,apu-mailbox.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml new file mode 100644 index 000000000000..cb4530799bef --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,apu-mailbox.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,apu-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek APU mailbox + +maintainers: + - Karl Li + +description: + The MediaTek APU-Mailbox facilitates communication with the + APU microcontroller. Within the MediaTek APU subsystem, a + message passing mechanism is built on top of the mailbox system. + The mailbox only has limited space for each message. The firmware + expects the message header from the mailbox, while the message body + is passed through some fixed shared memory. + +properties: + compatible: + enum: + - mediatek,mt8188-apu-mailbox + - mediatek,mt8196-apu-mailbox + + "#mbox-cells": + const: 1 + description: + The cell describe which channel the device will use. + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - "#mbox-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + apu_mailbox: mailbox@4c200000 { + compatible = "mediatek,mt8196-apu-mailbox"; + reg = <0 0x4c200000 0 0xfffff>; + interrupts = ; + #mbox-cells = <1>; + }; From patchwork Thu Oct 24 09:25:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Karl.Li" X-Patchwork-Id: 13848645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1504CDDE69 for ; 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Thu, 24 Oct 2024 02:26:51 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 24 Oct 2024 17:26:49 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 24 Oct 2024 17:26:49 +0800 From: Karl.Li To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Karl Li CC: , , , , Chungying Lu , , Karl Li Subject: [PATCH 2/3] mailbox: add support for bottom half received data Date: Thu, 24 Oct 2024 17:25:44 +0800 Message-ID: <20241024092608.431581-3-karl.li@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024092608.431581-1-karl.li@mediatek.com> References: <20241024092608.431581-1-karl.li@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241024_022655_223979_9BCCE467 X-CRM114-Status: GOOD ( 15.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Karl Li Within the MediaTek APU subsystem, a message passing mechanism is constructed on top of the mailbox system. The mailbox only has limited space for each message. The MTK APU firmware expects the message header from the mailbox, while the message body is passed through some fixed shared memory. The mailbox interrupt also serves as a mutex for the shared memory. Thus the interrupt may only be cleared after the message is handled. Add a new sleepable rx callback for mailbox clients for cases where handling the incoming data needs to sleep. Signed-off-by: Karl Li --- drivers/mailbox/mailbox.c | 16 ++++++++++++++++ include/linux/mailbox_client.h | 2 ++ include/linux/mailbox_controller.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index d3d26a2c9895..d58a77fcf804 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -164,6 +164,22 @@ void mbox_chan_received_data(struct mbox_chan *chan, void *mssg) } EXPORT_SYMBOL_GPL(mbox_chan_received_data); +/** + * mbox_chan_received_data_bh - A way for controller driver to push data + * received from remote to the upper layer. + * @chan: Pointer to the mailbox channel on which RX happened. + * @mssg: Client specific message typecasted as void * + * + * For the operations which is not atomic can be called from + * mbox_chan_received_data_bh(). + */ +void mbox_chan_received_data_bh(struct mbox_chan *chan, void *mssg) +{ + if (chan->cl->rx_callback_bh) + chan->cl->rx_callback_bh(chan->cl, mssg); +} +EXPORT_SYMBOL_GPL(mbox_chan_received_data_bh); + /** * mbox_chan_txdone - A way for controller driver to notify the * framework that the last TX has completed. diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h index 734694912ef7..2cc6fa4e1bf9 100644 --- a/include/linux/mailbox_client.h +++ b/include/linux/mailbox_client.h @@ -22,6 +22,7 @@ struct mbox_chan; * if the client receives some ACK packet for transmission. * Unused if the controller already has TX_Done/RTR IRQ. * @rx_callback: Atomic callback to provide client the data received + * @rx_callback_bh: Non-atomic callback to provide client the data received * @tx_prepare: Atomic callback to ask client to prepare the payload * before initiating the transmission if required. * @tx_done: Atomic callback to tell client of data transmission @@ -33,6 +34,7 @@ struct mbox_client { bool knows_txdone; void (*rx_callback)(struct mbox_client *cl, void *mssg); + void (*rx_callback_bh)(struct mbox_client *cl, void *mssg); void (*tx_prepare)(struct mbox_client *cl, void *mssg); void (*tx_done)(struct mbox_client *cl, void *mssg, int r); }; diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index 6fee33cb52f5..74c6a31cd313 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -130,6 +130,7 @@ struct mbox_chan { int mbox_controller_register(struct mbox_controller *mbox); /* can sleep */ void mbox_controller_unregister(struct mbox_controller *mbox); /* can sleep */ void mbox_chan_received_data(struct mbox_chan *chan, void *data); /* atomic */ +void mbox_chan_received_data_bh(struct mbox_chan *chan, void *data); /* can sleep */ void mbox_chan_txdone(struct mbox_chan *chan, int r); /* atomic */ int devm_mbox_controller_register(struct device *dev, From patchwork Thu Oct 24 09:25:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Karl.Li" X-Patchwork-Id: 13848636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFA4CD0BB7A for ; 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Thu, 24 Oct 2024 02:26:53 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 24 Oct 2024 17:26:50 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 24 Oct 2024 17:26:50 +0800 From: Karl.Li To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Karl Li CC: , , , , Chungying Lu , , Karl Li Subject: [PATCH 3/3] mailbox: mediatek: Add mtk-apu-mailbox driver Date: Thu, 24 Oct 2024 17:25:45 +0800 Message-ID: <20241024092608.431581-4-karl.li@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241024092608.431581-1-karl.li@mediatek.com> References: <20241024092608.431581-1-karl.li@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.620800-8.000000 X-TMASE-MatchedRID: 4kHyKE737jM9S3IiQd+eNWgZSmduwyweUAjrAJWsTe8It7KhKWdvFOJ1 Z55wDcxT8AyWk2NFMNZM8qdoCvOVvj13WcdbGR6Qzbh2+gTKAQ+AfODDLypXmvFJXtgF4GFL0JL YEuZmPHUC470HKuzgB1rcv8nBrrT3BrU1duOq6zS3D7EeeyZCMwrefVId6fzVjnLTb30f4043dV Tnu0EmWDqE8reTKDts781jTNgzH3VZT98H9cWYnJMSBMTQNiSAKSiQ6eagz6JX14Hy+eYp7+YI8 JecFTbdRw3fpQHgw3sGYQd6rNaIOSJFbDWAdpZLHPYwOJi6PLmXYX34rFl3x2d6vNuG6CqySAKU IhfaB7A0RbGKWWKZ/3Qe11JD81nVu9okb5cOFzbKl4yJoI+fG9O4VcbrqWuq8EAby1w1DMl576m y5IxjulD3U31Zcw/LhxHjE30dAnsfE8yM4pjsDwtuKBGekqUpOlxBO2IcOBaIHGa67w1D28oh7y qmhyfdMbuKPPB0sroSZzN3LFJ282uTKbq4kNjO X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.620800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 0BF7B7E278F88FE729E9F1441FC5995BADA4A3936A1666D1E2EF3D5FE850B0772000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241024_022659_262994_BE9AD17C X-CRM114-Status: GOOD ( 27.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Karl Li Add mtk-apu-mailbox driver to support the communication with APU remote microprocessor. Also, the mailbox hardware contains extra spare (scratch) registers that other hardware blocks use to communicate through. Expose these with custom mtk_apu_mbox_(read|write)() functions. Signed-off-by: Karl Li --- drivers/mailbox/Kconfig | 9 + drivers/mailbox/Makefile | 2 + drivers/mailbox/mtk-apu-mailbox.c | 222 ++++++++++++++++++++++++ include/linux/mailbox/mtk-apu-mailbox.h | 20 +++ 4 files changed, 253 insertions(+) create mode 100644 drivers/mailbox/mtk-apu-mailbox.c create mode 100644 include/linux/mailbox/mtk-apu-mailbox.h diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 6fb995778636..2338e08a110a 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -240,6 +240,15 @@ config MTK_ADSP_MBOX between processors with ADSP. It will place the message to share buffer and will access the ipc control. +config MTK_APU_MBOX + tristate "MediaTek APU Mailbox Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Say yes here to add support for the MediaTek APU Mailbox + driver. The mailbox implementation provides access from the + application processor to the MediaTek AI Processing Unit. + If unsure say N. + config MTK_CMDQ_MBOX tristate "MediaTek CMDQ Mailbox Support" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 3c3c27d54c13..6b6dcc78d644 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -53,6 +53,8 @@ obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_MTK_ADSP_MBOX) += mtk-adsp-mailbox.o +obj-$(CONFIG_MTK_APU_MBOX) += mtk-apu-mailbox.o + obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o diff --git a/drivers/mailbox/mtk-apu-mailbox.c b/drivers/mailbox/mtk-apu-mailbox.c new file mode 100644 index 000000000000..b347ebd34ef7 --- /dev/null +++ b/drivers/mailbox/mtk-apu-mailbox.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include + +#define INBOX (0x0) +#define OUTBOX (0x20) +#define INBOX_IRQ (0xc0) +#define OUTBOX_IRQ (0xc4) +#define INBOX_IRQ_MASK (0xd0) + +#define SPARE_OFF_START (0x40) +#define SPARE_OFF_END (0xB0) + +struct mtk_apu_mailbox { + struct device *dev; + void __iomem *regs; + struct mbox_controller controller; + u32 msgs[MSG_MBOX_SLOTS]; +}; + +struct mtk_apu_mailbox *g_mbox; + +static irqreturn_t mtk_apu_mailbox_irq_top_half(int irq, void *dev_id) +{ + struct mtk_apu_mailbox *mbox = dev_id; + struct mbox_chan *link = &mbox->controller.chans[0]; + int i; + + for (i = 0; i < MSG_MBOX_SLOTS; i++) + mbox->msgs[i] = readl(mbox->regs + OUTBOX + i * sizeof(u32)); + + mbox_chan_received_data(link, &mbox->msgs); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t mtk_apu_mailbox_irq_btm_half(int irq, void *dev_id) +{ + struct mtk_apu_mailbox *mbox = dev_id; + struct mbox_chan *link = &mbox->controller.chans[0]; + + mbox_chan_received_data_bh(link, &mbox->msgs); + writel(readl(mbox->regs + OUTBOX_IRQ), mbox->regs + OUTBOX_IRQ); + + return IRQ_HANDLED; +} + +static int mtk_apu_mailbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mtk_apu_mailbox *mbox = container_of(chan->mbox, + struct mtk_apu_mailbox, + controller); + struct mtk_apu_mailbox_msg *msg = data; + int i; + + if (msg->send_cnt <= 0 || msg->send_cnt > MSG_MBOX_SLOTS) { + dev_err(mbox->dev, "%s: invalid send_cnt %d\n", __func__, msg->send_cnt); + return -EINVAL; + } + + /* + * Mask lowest "send_cnt-1" interrupts bits, so the interrupt on the other side + * triggers only after the last data slot is written (sent). + */ + writel(GENMASK(msg->send_cnt - 2, 0), mbox->regs + INBOX_IRQ_MASK); + for (i = 0; i < msg->send_cnt; i++) + writel(msg->data[i], mbox->regs + INBOX + i * sizeof(u32)); + + return 0; +} + +static bool mtk_apu_mailbox_last_tx_done(struct mbox_chan *chan) +{ + struct mtk_apu_mailbox *mbox = container_of(chan->mbox, + struct mtk_apu_mailbox, + controller); + + return readl(mbox->regs + INBOX_IRQ) == 0; +} + +static const struct mbox_chan_ops mtk_apu_mailbox_ops = { + .send_data = mtk_apu_mailbox_send_data, + .last_tx_done = mtk_apu_mailbox_last_tx_done, +}; + +/** + * mtk_apu_mbox_write - Write value to specifice mtk_apu_mbox spare register. + * @val: Value to be written. + * @offset: Offset of the spare register. + * + * Return: 0 if successful + * negative value if error happened + */ +int mtk_apu_mbox_write(u32 val, u32 offset) +{ + if (!g_mbox) { + pr_err("mtk apu mbox was not initialized, stop writing register\n"); + return -ENODEV; + } + + if (offset < SPARE_OFF_START || offset >= SPARE_OFF_END) { + dev_err(g_mbox->dev, "Invalid offset %d for mtk apu mbox spare register\n", offset); + return -EINVAL; + } + + writel(val, g_mbox->regs + offset); + return 0; +} +EXPORT_SYMBOL_NS(mtk_apu_mbox_write, MTK_APU_MAILBOX); + +/** + * mtk_apu_mbox_read - Read value to specifice mtk_apu_mbox spare register. + * @offset: Offset of the spare register. + * @val: Pointer to store read value. + * + * Return: 0 if successful + * negative value if error happened + */ +int mtk_apu_mbox_read(u32 offset, u32 *val) +{ + if (!g_mbox) { + pr_err("mtk apu mbox was not initialized, stop reading register\n"); + return -ENODEV; + } + + if (offset < SPARE_OFF_START || offset >= SPARE_OFF_END) { + dev_err(g_mbox->dev, "Invalid offset %d for mtk apu mbox spare register\n", offset); + return -EINVAL; + } + + *val = readl(g_mbox->regs + offset); + + return 0; +} +EXPORT_SYMBOL_NS(mtk_apu_mbox_read, MTK_APU_MAILBOX); + +static int mtk_apu_mailbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_apu_mailbox *mbox; + int irq = -1, ret = 0; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + mbox->dev = dev; + platform_set_drvdata(pdev, mbox); + + mbox->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mbox->regs)) + return PTR_ERR(mbox->regs); + + mbox->controller.txdone_irq = false; + mbox->controller.txdone_poll = true; + mbox->controller.txpoll_period = 1; + mbox->controller.ops = &mtk_apu_mailbox_ops; + mbox->controller.dev = dev; + /* + * Here we only register 1 mbox channel. + * The remaining channels are used by other modules. + */ + mbox->controller.num_chans = 1; + mbox->controller.chans = devm_kcalloc(dev, mbox->controller.num_chans, + sizeof(*mbox->controller.chans), + GFP_KERNEL); + if (!mbox->controller.chans) + return -ENOMEM; + + ret = devm_mbox_controller_register(dev, &mbox->controller); + if (ret) + return ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(dev, irq, mtk_apu_mailbox_irq_top_half, + mtk_apu_mailbox_irq_btm_half, IRQF_ONESHOT, + dev_name(dev), mbox); + if (ret) + return dev_err_probe(dev, ret, "Failed to request IRQ\n"); + + g_mbox = mbox; + + dev_dbg(dev, "registered mtk apu mailbox\n"); + + return 0; +} + +static void mtk_apu_mailbox_remove(struct platform_device *pdev) +{ + g_mbox = NULL; +} + +static const struct of_device_id mtk_apu_mailbox_of_match[] = { + { .compatible = "mediatek,mt8188-apu-mailbox" }, + { .compatible = "mediatek,mt8196-apu-mailbox" }, + {} +}; +MODULE_DEVICE_TABLE(of, mtk_apu_mailbox_of_match); + +static struct platform_driver mtk_apu_mailbox_driver = { + .probe = mtk_apu_mailbox_probe, + .remove = mtk_apu_mailbox_remove, + .driver = { + .name = "mtk-apu-mailbox", + .of_match_table = mtk_apu_mailbox_of_match, + }, +}; + +module_platform_driver(mtk_apu_mailbox_driver); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek APU Mailbox Driver"); diff --git a/include/linux/mailbox/mtk-apu-mailbox.h b/include/linux/mailbox/mtk-apu-mailbox.h new file mode 100644 index 000000000000..d1457d16ce9b --- /dev/null +++ b/include/linux/mailbox/mtk-apu-mailbox.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024 MediaTek Inc. + * + */ + +#ifndef __MTK_APU_MAILBOX_H__ +#define __MTK_APU_MAILBOX_H__ + +#define MSG_MBOX_SLOTS (8) + +struct mtk_apu_mailbox_msg { + int send_cnt; + u32 data[MSG_MBOX_SLOTS]; +}; + +int mtk_apu_mbox_write(u32 val, u32 offset); +int mtk_apu_mbox_read(u32 offset, u32 *val); + +#endif /* __MTK_APU_MAILBOX_H__ */