From patchwork Thu Oct 24 11:31:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meghana Malladi X-Patchwork-Id: 13848821 X-Patchwork-Delegate: kuba@kernel.org Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F7A96CDBA; Thu, 24 Oct 2024 11:32:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729769556; cv=none; b=hgciveZW5dse1XYltyRgVmzr+QoMGIUWg3koSl7Xj/b8Oho9WUQF6BO/KtXMMlhT85/awhHmtjqD8dl6CPo3N2RKhBtIbk8ra6pSTym5BBKDbzjD44Jqv3vztDHeqMjVIRzKSEPsJmr7QkqDpt7OrCx2Q+g3Elpjl1jz0snmgX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729769556; c=relaxed/simple; bh=lDea2FMjqGZ9k9qRL6S/dGNvhzc3tfHV/cof20gJ+mk=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=ZrgQI/r9IU7fwVenu2gOBxAbUJgIiODtsp8iM4k3c1Q8sW2YNlF6BQOmuGmMS76oRBGtnn+ELbJMf9Moe2cJUa5od2zM2i99Z7mZcEScsIEKYoc6wBcA7btinnnplJEtPp17o0Jn+7K+McOHMhkN68w1D0q7WAZNCW4VZY0/QLU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ZJU367tW; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZJU367tW" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49OBW7LM116527; Thu, 24 Oct 2024 06:32:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729769527; bh=aMLsOpWO/pYNkEAk0fPsDrgjjgnzlpp9C0m/g9waCuE=; h=From:To:CC:Subject:Date; b=ZJU367tW0yBQ3ojql4Noam33G+/lcMIbRFioV8ISAsq7Qyhevfv+jXYdJdeuaLAPT zsKrqv+vu71oIZZ7yY6wQ9334E/oQvfXWUEWNY3S/vYl+RDkjPxsoUiEDGasf/8U0v titvqwvfkkNXg2uFGZA4bsR972oHBmfKyN//043Y= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49OBW7Bt026893 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Oct 2024 06:32:07 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 24 Oct 2024 06:32:07 -0500 Received: from fllvsmtp7.itg.ti.com (10.64.40.31) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 24 Oct 2024 06:32:06 -0500 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by fllvsmtp7.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49OBW61O044845; Thu, 24 Oct 2024 06:32:06 -0500 Received: from localhost (meghana-pc.dhcp.ti.com [10.24.69.13] (may be forged)) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 49OBW5Ug002932; Thu, 24 Oct 2024 06:32:05 -0500 From: Meghana Malladi To: , , , , , , , , , CC: , , , , , Roger Quadros , Subject: [PATCH net v2] net: ti: icssg-prueth: Fix 1 PPS sync Date: Thu, 24 Oct 2024 17:01:40 +0530 Message-ID: <20241024113140.973928-1-m-malladi@ti.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-Patchwork-Delegate: kuba@kernel.org The first PPS latch time needs to be calculated by the driver (in rounded off seconds) and configured as the start time offset for the cycle. After synchronizing two PTP clocks running as master/slave, missing this would cause master and slave to start immediately with some milliseconds drift which causes the PPS signal to never synchronize with the PTP master. Fixes: 186734c15886 ("net: ti: icssg-prueth: add packet timestamping and ptp support") Signed-off-by: Meghana Malladi Reviewed-by: Vadim Fedorenko Reviewed-by: MD Danish Anwar --- Hello, This patch is based on net-next tagged next-20241023. v1:https://lore.kernel.org/all/20241023091213.593351-1-m-malladi@ti.com/ Changes since v1 (v2-v1): - Use roundup() instead of open coding as suggested by Vadim Fedorenko Regards, Meghana. drivers/net/ethernet/ti/icssg/icssg_prueth.c | 12 ++++++++++-- drivers/net/ethernet/ti/icssg/icssg_prueth.h | 11 +++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) base-commit: 73840ca5ef361f143b89edd5368a1aa8c2979241 diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/ethernet/ti/icssg/icssg_prueth.c index 0556910938fa..6876e8181066 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c @@ -411,6 +411,8 @@ static int prueth_perout_enable(void *clockops_data, struct prueth_emac *emac = clockops_data; u32 reduction_factor = 0, offset = 0; struct timespec64 ts; + u64 current_cycle; + u64 start_offset; u64 ns_period; if (!on) @@ -449,8 +451,14 @@ static int prueth_perout_enable(void *clockops_data, writel(reduction_factor, emac->prueth->shram.va + TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET); - writel(0, emac->prueth->shram.va + - TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET); + current_cycle = icssg_readq(emac->prueth->shram.va + + TIMESYNC_FW_WC_CYCLECOUNT_OFFSET); + + /* Rounding of current_cycle count to next second */ + start_offset = roundup(current_cycle, MSEC_PER_SEC); + + icssg_writeq(start_offset, emac->prueth->shram.va + + TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET); return 0; } diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.h b/drivers/net/ethernet/ti/icssg/icssg_prueth.h index 8722bb4a268a..a4af2dbcca31 100644 --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.h +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.h @@ -330,6 +330,17 @@ static inline int prueth_emac_slice(struct prueth_emac *emac) extern const struct ethtool_ops icssg_ethtool_ops; extern const struct dev_pm_ops prueth_dev_pm_ops; +static inline u64 icssg_readq(const void __iomem *addr) +{ + return readl(addr) + ((u64)readl(addr + 4) << 32); +} + +static inline void icssg_writeq(u64 val, void __iomem *addr) +{ + writel(lower_32_bits(val), addr); + writel(upper_32_bits(val), addr + 4); +} + /* Classifier helpers */ void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac);