From patchwork Fri Oct 25 20:47:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF268D149F5 for ; Fri, 25 Oct 2024 20:47:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E1F1310EB88; Fri, 25 Oct 2024 20:47:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="APhSE0Me"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3F9D10EB83; Fri, 25 Oct 2024 20:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729889268; x=1761425268; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=N+WrtTCSB4IKUl9UOWsKa3ai0LH3UXE4popZJPeVoRs=; b=APhSE0MeyKiudvYDzlHolAXvwfk4KRmFQ1E8kZqRqqKNFwNiGDnRtMOx 758nlEw0sW9zbUWQvd03In7XOlNh+b7zkrLVO+4ps++AbNCsWcqP2ANu/ ofozzCypdeIRwu/tDy4ofpgVuSFTvuIe7CxC71rQbSEWcJJzDRunP37Zn L6kqzm2xhATl1S7M4Wwr4syMt2Jp0BpVPLteNnWyiUZqaTxdLO6/76bkY F8Q65zsV5B+twYr0wOS93sbmzFGr8NNAp0azmBbdcl7Dt4U6v918UO8wF F/BcKEc+sdwiFNuCLCJe9IFImi45H8KDb6C70emxSgO9qK5TE0OvNSHdI Q==; X-CSE-ConnectionGUID: caVR4JhIRE6XtpEjoh/EZw== X-CSE-MsgGUID: LAf8yOMcT3Wx9S6oMJfjnQ== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484200" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484200" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:47 -0700 X-CSE-ConnectionGUID: whWL4YNiTYSMvSKAPm405g== X-CSE-MsgGUID: aKpLAs+aRGK9uwy36fmtng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057182" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 01/11] drm/i915/xe3lpd: Update pmdemand programming Date: Fri, 25 Oct 2024 13:47:33 -0700 Message-Id: <20241025204743.211510-2-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper There are some minor changes to pmdemand handling on Xe3: - Active scalers are no longer tracked. We can simply skip the readout and programming of this field. - Active dbuf slices are no longer tracked. We should skip the readout and programming of this field and also make sure that it stays 0 in our software bookkeeping so that we won't erroneously return true from intel_pmdemand_needs_update() due to mismatches. - Even though there aren't enough pipes to utilize them, the size of the 'active pipes' field has expanded to four bits, taking over the register bits previously used for dbuf slices. Since the lower bits of the mask have moved, we need to update our reads/writes to handle this properly. v2: active pipes is no longer always max 3, add in the ability to go to 4 for PTL. v3: use intel_display for display_ver check, use INTEL_NUM_PIPES v4: add a conditional for number of pipes macro vs using 3. v5: reverse conditional order of v4. v6: undo v5 and fix num_pipes assignment v7: pass display struct instead of i915, checkpatch fix Bspec: 68883, 69125 Signed-off-by: Matt Roper Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_pmdemand.c | 73 +++++++++++++------ drivers/gpu/drm/i915/display/intel_pmdemand.h | 4 +- drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 53 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c index ceaf9e3147da..32443ae8e76c 100644 --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c @@ -258,6 +258,7 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state) static bool intel_pmdemand_needs_update(struct intel_atomic_state *state) { + struct intel_display *display = to_intel_display(state); const struct intel_bw_state *new_bw_state, *old_bw_state; const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; const struct intel_crtc_state *new_crtc_state, *old_crtc_state; @@ -274,12 +275,16 @@ static bool intel_pmdemand_needs_update(struct intel_atomic_state *state) new_dbuf_state = intel_atomic_get_new_dbuf_state(state); old_dbuf_state = intel_atomic_get_old_dbuf_state(state); if (new_dbuf_state && - (new_dbuf_state->active_pipes != - old_dbuf_state->active_pipes || - new_dbuf_state->enabled_slices != - old_dbuf_state->enabled_slices)) + new_dbuf_state->active_pipes != old_dbuf_state->active_pipes) return true; + if (DISPLAY_VER(display) < 30) { + if (new_dbuf_state && + new_dbuf_state->enabled_slices != + old_dbuf_state->enabled_slices) + return true; + } + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); old_cdclk_state = intel_atomic_get_old_cdclk_state(state); if (new_cdclk_state && @@ -327,10 +332,15 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state) if (IS_ERR(new_dbuf_state)) return PTR_ERR(new_dbuf_state); - new_pmdemand_state->params.active_pipes = - min_t(u8, hweight8(new_dbuf_state->active_pipes), 3); - new_pmdemand_state->params.active_dbufs = - min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3); + if (DISPLAY_VER(i915) < 30) { + new_pmdemand_state->params.active_dbufs = + min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3); + new_pmdemand_state->params.active_pipes = + min_t(u8, hweight8(new_dbuf_state->active_pipes), 3); + } else { + new_pmdemand_state->params.active_pipes = + min_t(u8, hweight8(new_dbuf_state->active_pipes), INTEL_NUM_PIPES(i915)); + } new_cdclk_state = intel_atomic_get_cdclk_state(state); if (IS_ERR(new_cdclk_state)) @@ -395,27 +405,32 @@ intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915, reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)); - /* Set 1*/ pmdemand_state->params.qclk_gv_bw = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); pmdemand_state->params.voltage_index = REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); pmdemand_state->params.qclk_gv_index = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); - pmdemand_state->params.active_pipes = - REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); - pmdemand_state->params.active_dbufs = - REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); pmdemand_state->params.active_phys = REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); - /* Set 2*/ pmdemand_state->params.cdclk_freq_mhz = REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); pmdemand_state->params.ddiclk_max = REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); - pmdemand_state->params.scalers = - REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); + + if (DISPLAY_VER(i915) >= 30) { + pmdemand_state->params.active_pipes = + REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1); + } else { + pmdemand_state->params.active_pipes = + REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); + pmdemand_state->params.active_dbufs = + REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); + + pmdemand_state->params.scalers = + REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); + } unlock: mutex_unlock(&i915->display.pmdemand.lock); @@ -442,6 +457,10 @@ void intel_pmdemand_program_dbuf(struct drm_i915_private *i915, { u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3); + /* PM Demand only tracks active dbufs on pre-Xe3 platforms */ + if (DISPLAY_VER(i915) >= 30) + return; + mutex_lock(&i915->display.pmdemand.lock); if (drm_WARN_ON(&i915->drm, !intel_pmdemand_check_prev_transaction(i915))) @@ -460,9 +479,10 @@ void intel_pmdemand_program_dbuf(struct drm_i915_private *i915, } static void -intel_pmdemand_update_params(const struct intel_pmdemand_state *new, - const struct intel_pmdemand_state *old, - u32 *reg1, u32 *reg2, bool serialized) +intel_pmdemand_update_params(struct intel_display *display, + const struct intel_pmdemand_state *new, + const struct intel_pmdemand_state *old, + u32 *reg1, u32 *reg2, bool serialized) { /* * The pmdemand parameter updates happens in two steps. Pre plane and @@ -495,16 +515,22 @@ intel_pmdemand_update_params(const struct intel_pmdemand_state *new, update_reg(reg1, qclk_gv_bw, XELPDP_PMDEMAND_QCLK_GV_BW_MASK); update_reg(reg1, voltage_index, XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK); update_reg(reg1, qclk_gv_index, XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK); - update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK); - update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK); update_reg(reg1, active_phys, XELPDP_PMDEMAND_PHYS_MASK); /* Set 2*/ update_reg(reg2, cdclk_freq_mhz, XELPDP_PMDEMAND_CDCLK_FREQ_MASK); update_reg(reg2, ddiclk_max, XELPDP_PMDEMAND_DDICLK_FREQ_MASK); - update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK); update_reg(reg2, plls, XELPDP_PMDEMAND_PLLS_MASK); + if (DISPLAY_VER(display) >= 30) { + update_reg(reg1, active_pipes, XE3_PMDEMAND_PIPES_MASK); + } else { + update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK); + update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK); + + update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK); + } + #undef update_reg } @@ -514,6 +540,7 @@ intel_pmdemand_program_params(struct drm_i915_private *i915, const struct intel_pmdemand_state *old, bool serialized) { + struct intel_display *display = &i915->display; bool changed = false; u32 reg1, mod_reg1; u32 reg2, mod_reg2; @@ -529,7 +556,7 @@ intel_pmdemand_program_params(struct drm_i915_private *i915, reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)); mod_reg2 = reg2; - intel_pmdemand_update_params(new, old, &mod_reg1, &mod_reg2, + intel_pmdemand_update_params(display, new, old, &mod_reg1, &mod_reg2, serialized); if (reg1 != mod_reg1) { diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h index 128fd61f8f14..a1c49efdc493 100644 --- a/drivers/gpu/drm/i915/display/intel_pmdemand.h +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h @@ -20,14 +20,14 @@ struct pmdemand_params { u8 voltage_index; u8 qclk_gv_index; u8 active_pipes; - u8 active_dbufs; + u8 active_dbufs; /* pre-Xe3 only */ /* Total number of non type C active phys from active_phys_mask */ u8 active_phys; u8 plls; u16 cdclk_freq_mhz; /* max from ddi_clocks[] */ u16 ddiclk_max; - u8 scalers; + u8 scalers; /* pre-Xe3 only */ }; struct intel_pmdemand_state { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 405f409e9761..89e4381f8baa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2696,6 +2696,7 @@ #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) +#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4) #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) From patchwork Fri Oct 25 20:47:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAEA2D149F3 for ; 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X-CSE-ConnectionGUID: sXzl61rTQXSnEVtAJhTFRA== X-CSE-MsgGUID: V0ZcvhnRQhK79J6N1Q8Tqw== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484201" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484201" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:47 -0700 X-CSE-ConnectionGUID: j6N0eoJRRsycqrBGrnzEpw== X-CSE-MsgGUID: h6/0NsQEQ/+VdgYVjWJ7Hg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057184" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 02/11] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3 Date: Fri, 25 Oct 2024 13:47:34 -0700 Message-Id: <20241025204743.211510-3-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Suraj Kandpal We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI encoder. Also remove the Wa comment tag as this follows the bspec and does not implement the wa. v2: add additional definition instead of function, commit message typo fix and update. v3: restore lost conditional from v2. v4: subject line and subject message updated, fix the if ladder order, fix the bit definition order. v5: Add the bspec link and remove the Wa comment tag Bspec: 68933 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_hdcp.c | 11 +++++++---- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index ed6aa87403e2..7a32bfef8d87 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -31,7 +31,6 @@ #define KEY_LOAD_TRIES 5 #define HDCP2_LC_RETRY_CNT 3 -/* WA: 16022217614 */ static void intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, struct intel_hdcp *hdcp) @@ -43,14 +42,18 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, return; if (DISPLAY_VER(display) >= 14) { - if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_D0, STEP_FOREVER)) - intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), - 0, HDCP_LINE_REKEY_DISABLE); + if (DISPLAY_VER(display) >= 30) + intel_de_rmw(display, + TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder), + 0, XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE); else if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder), 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); + else if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_D0, STEP_FOREVER)) + intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), + 0, HDCP_LINE_REKEY_DISABLE); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 89e4381f8baa..8d758947f301 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3817,6 +3817,7 @@ enum skl_power_gate { #define TRANS_DDI_PVSYNC (1 << 17) #define TRANS_DDI_PHSYNC (1 << 16) #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) +#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15) #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) From patchwork Fri Oct 25 20:47:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15959D149F3 for ; Fri, 25 Oct 2024 20:47:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F25E510EB8A; Fri, 25 Oct 2024 20:47:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gXPb2Ug7"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 21E5110EB83; Fri, 25 Oct 2024 20:47:48 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="81057185" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 03/11] drm/i915/xe3lpd: Add check to see if edp over type c is allowed Date: Fri, 25 Oct 2024 13:47:35 -0700 Message-Id: <20241025204743.211510-4-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Suraj Kandpal Read PICA register to see if edp over type C is possible and then add the appropriate tables for it. --v2 -remove bool from intel_encoder have it in runtime_info [Jani] -initialize the bool in runtime_info init [Jani] -dont abbreviate the bool [Jani] --v3 -Remove useless display version check [Jani] -change the warn on condition [Jani] -no need for a different function for edp type c check [Jani] -dont add register in i915_reg [Jani] Bspec: 68846 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++ drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++ drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ drivers/gpu/drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++--- 5 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 8bd5a4d1b735..d05daa7a2b03 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2257,9 +2257,12 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(crtc_state); if (intel_crtc_has_dp_encoder(crtc_state)) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { + if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support) + return xe3lpd_c20_dp_edp_tables; if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) return xe2hpd_c20_edp_tables; } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index ab3ae110b68f..e8ebb12155a4 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -363,4 +363,7 @@ #define HDMI_DIV_MASK REG_GENMASK16(2, 0) #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) +#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) +#define EDP_ON_TYPEC REG_BIT(31) + #endif /* __INTEL_CX0_REG_DEFS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index aa22189e3853..949838308ec9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_cx0_phy_regs.h" #include "intel_de.h" #include "intel_display.h" #include "intel_display_device.h" @@ -1685,6 +1686,10 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 } } + if (DISPLAY_VER(i915) >= 30) + display_runtime->edp_typec_support = + intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC; + display_runtime->rawclk_freq = intel_read_rawclk(display); drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 071a36b51f79..410f8b33a8a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -232,6 +232,7 @@ struct intel_display_runtime_info { bool has_hdcp; bool has_dmc; bool has_dsc; + bool edp_typec_support; }; struct intel_display_device_info { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7e29619ba040..9f015b530289 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6441,10 +6441,11 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { /* - * Currently we don't support eDP on TypeC ports, although in - * theory it could work on TypeC legacy ports. + * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, + * although in theory it could work on TypeC legacy ports. */ - drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder)); + drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) && + DISPLAY_VER(dev_priv) < 30); type = DRM_MODE_CONNECTOR_eDP; intel_encoder->type = INTEL_OUTPUT_EDP; From patchwork Fri Oct 25 20:47:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22183D149F5 for ; Fri, 25 Oct 2024 20:47:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E3DF10EB87; Fri, 25 Oct 2024 20:47:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kz8JYB2z"; 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d="scan'208";a="33484204" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: 94N6VxUcTwCHMNxlBUARwA== X-CSE-MsgGUID: Pi3FVDmlT0iyoqYB8omu+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057187" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 04/11] drm/i915/ptl: Define IS_PANTHERLAKE macro Date: Fri, 25 Oct 2024 13:47:36 -0700 Message-Id: <20241025204743.211510-5-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dnyaneshwar Bhadane Common display code requires IS_PANTHERLAKE macro. Define the macro and set 0 as PTL is no longer support for i915. Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index de73b348b8cf..0f19cbd36829 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -536,6 +536,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, */ #define IS_LUNARLAKE(i915) (0 && i915) #define IS_BATTLEMAGE(i915) (0 && i915) +#define IS_PANTHERLAKE(i915) (0 && i915) #define IS_ARROWLAKE(i915) \ IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL) From patchwork Fri Oct 25 20:47:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B57BCD149FA for ; Fri, 25 Oct 2024 20:47:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D22F410EB90; Fri, 25 Oct 2024 20:47:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ifHvQSBf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 72A9510EB83; Fri, 25 Oct 2024 20:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729889268; x=1761425268; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=2aRMB6apax37HIZCgt0RRlAoFdFRglk/Hvo3H4yDLq4=; b=ifHvQSBfG3rUkSSv+gg6LBoRbqd/w56hrPjRE60yCByNTwlgBFYNjscS t4hlrnpK+RJsYZm7URkLwVYQuPV5cxC8FEwAau10pTYgnGtGtcCRXGllC HVS5ezcI4Ava+MUcWkOrsYuI9ZG7zcZ+1z+FT/Ee1TSzMu8LJCIdD/H3g Th8/ynB3VOOSDSHL7vm0QCCUHeXR8vi+dS4VG068qnVSKghlv7mtFR+Bd rktlph1//vcbRjN8TbIQx6utnaZmHRzYlTHWQ1g4fYh5aT2/bh0cb9lVS oQrr5wM5MaPYoUHKGHEo/dt3rJ3H0f4dMGq9fQKjQOG2pRfx71r9chTaI A==; X-CSE-ConnectionGUID: H8uz7+2dQEqF9uW/51wOuQ== X-CSE-MsgGUID: RgK0qruoReSMOqeFreCoyQ== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484205" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484205" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: QQEPqI0SQtarJtlM7ye53A== X-CSE-MsgGUID: y2VonO42RIekgJjxPrjd5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057188" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 05/11] drm/i915/cx0: Extend C10 check to PTL Date: Fri, 25 Oct 2024 13:47:37 -0700 Message-Id: <20241025204743.211510-6-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dnyaneshwar Bhadane When deciding the type of the phy, add PTL support to make sure the correct path is taken for selection of C10 PHY. Only port A is connected C10 PHY for Pantherlake. Bspec: 72571 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++ drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d05daa7a2b03..4d6e1c135bdc 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -34,6 +34,9 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_encoder_to_phy(encoder); + if (IS_PANTHERLAKE(i915) && phy == PHY_A) + return true; + if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C) return true; diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index b7041b578e5e..bd8c3de57dcd 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -67,6 +67,7 @@ static inline struct drm_i915_private *to_i915(const struct drm_device *dev) #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) #define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE) +#define IS_PANTHERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_PANTHERLAKE) #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) From patchwork Fri Oct 25 20:47:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11B70D149FE for ; Fri, 25 Oct 2024 20:47:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3924310EB96; Fri, 25 Oct 2024 20:47:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="a8AjHRVj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 96EFB10EB82; Fri, 25 Oct 2024 20:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729889269; x=1761425269; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=8Tm8t2kEZXAvSHGjZDgvrqrf38dXDVKpmO8qby0qQiw=; b=a8AjHRVjobCVHGarqObkvOol7CsTDJpalqfqdtd1YtC9rDBqsDBRD/v6 BAqq8uRujqkybxaBHW82+cIFlHscpRwbKcAUX9sGG1aMRBZrVCx+HOHd/ d3B49DkxQU4kEl8K55zxgC5ddZMipjuFhxPVJSEnS25sCyuOPLH8iR+CW 13kkrAHwHPpZWcvREtI4v2EkzeK6jyHDUEewA9BxaKaQ4xGfbjCbfTiF7 8FT18/AexGf1cfWPBSJReMhze9Nluy3u5RKjf2seKgdfvyPnl31VE3/8b QPZizgrEU8GgJmRdWEF+g86mbmKwajUDqrPNod57gXI421kMPr4VvQyy9 g==; X-CSE-ConnectionGUID: K6ECFT4zTxa+WCstg0WB/g== X-CSE-MsgGUID: uKtfiYgnTkahebTaaJSEXw== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484206" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484206" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: KvNUE8zrQvW8wnqQQBBRSA== X-CSE-MsgGUID: bhOZinsaQVKguJIVXmDdug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057189" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 06/11] drm/i915/cx0: Remove bus reset after every c10 transaction Date: Fri, 25 Oct 2024 13:47:38 -0700 Message-Id: <20241025204743.211510-7-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" C10 phy timeouts occur on xe3lpd if the c10 bus is reset every transaction. Starting with xe3lpd this is bus reset not necessary Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4d6e1c135bdc..c6e0cbff5201 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -224,7 +224,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder, * down and let the message bus to end up * in a known state */ - intel_cx0_bus_reset(encoder, lane); + if (DISPLAY_VER(i915) < 30) + intel_cx0_bus_reset(encoder, lane); return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val); } @@ -313,7 +314,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder, * down and let the message bus to end up * in a known state */ - intel_cx0_bus_reset(encoder, lane); + if (DISPLAY_VER(i915) < 30) + intel_cx0_bus_reset(encoder, lane); return 0; } From patchwork Fri Oct 25 20:47:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0425ED149FB for ; Fri, 25 Oct 2024 20:47:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1504A10EB95; Fri, 25 Oct 2024 20:47:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GdPpclOA"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id A908610EB83; Fri, 25 Oct 2024 20:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729889269; x=1761425269; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=OlbSmgYFCp6kPY5rHwOvB8io/h5G8sKMV9OU9yIhRMA=; b=GdPpclOA8wiF88AkNyWhaJtMBthPmqAKF7iOoi1w7E07dinBYytazJJd b77dcOHzYQXZYDn4xQyKHTpK2rgY8137o5fL8KT0Y38FjT1Q9OAmGUJhB Pj2aTEgfUYuGjkgaWYyH/k4hH3VgD/iOsVCzH1cMNCU9rlN9x6InZ4jWV BlY8kg8iI7G6DHIzuYb7+aixnzsq2ADdlgdPAbJI0iKfvyGUCwkMnKPaV La3dOE4hgXVkt3wlx6QDom7N1A6i+ywiUtVuRYFEWECUgSMxln2e+gaJ3 rk8fKxRp7ZboUUbOcMKC6r9tFrZ2QWiMZxMVHhqqQVQ3fd2DpFHlomKYf Q==; X-CSE-ConnectionGUID: kVbDAhGLSLeRro6h0fLRZA== X-CSE-MsgGUID: lLGEqrjaQKywhIelWZ64yA== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484207" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484207" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: Hwtn5P3pT76ePXkMfx6WdQ== X-CSE-MsgGUID: v0ad514yR8WiICmuUnwO2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057190" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:49 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 07/11] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register Date: Fri, 25 Oct 2024 13:47:39 -0700 Message-Id: <20241025204743.211510-8-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dnyaneshwar Bhadane The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD. Bspec: 69853,69878 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 +++++++++---- .../gpu/drm/i915/display/skl_universal_plane_regs.h | 1 + 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index a0a7ed01415a..60ca4f8c4a3c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1567,17 +1567,22 @@ skl_plane_async_flip(struct intel_dsb *dsb, struct intel_display *display = to_intel_display(plane->base.dev); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; - u32 plane_ctl = plane_state->ctl; + u32 plane_ctl = plane_state->ctl, plane_surf; plane_ctl |= skl_plane_ctl_crtc(crtc_state); + plane_surf = skl_plane_surf(plane_state, 0); - if (async_flip) - plane_ctl |= PLANE_CTL_ASYNC_FLIP; + if (async_flip) { + if (DISPLAY_VER(display) >= 30) + plane_surf |= PLANE_SURF_ASYNC_UPDATE; + else + plane_ctl |= PLANE_CTL_ASYNC_FLIP; + } intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), plane_ctl); intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), - skl_plane_surf(plane_state, 0)); + plane_surf); } static bool intel_format_is_p01x(u32 format) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 4ddcd7d46bbd..ff31a00d511e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -159,6 +159,7 @@ _PLANE_SURF_2_A, _PLANE_SURF_2_B) #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) #define PLANE_SURF_DECRYPT REG_BIT(2) +#define PLANE_SURF_ASYNC_UPDATE REG_BIT(0) #define _PLANE_KEYMAX_1_A 0x701a0 #define _PLANE_KEYMAX_2_A 0x702a0 From patchwork Fri Oct 25 20:47:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D233D149F2 for ; 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X-CSE-ConnectionGUID: YJbV6tqCRAerD/7CuK0eFA== X-CSE-MsgGUID: bA+FS7aTSga6C4LSKI2Opw== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484208" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484208" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: h8mjwlEDRYqT2POlreUYag== X-CSE-MsgGUID: A2TtsS6rQuKiqhgE5dSaEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057193" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:49 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 08/11] drm/i915/xe3: Underrun recovery does not exist post Xe2 Date: Fri, 25 Oct 2024 13:47:40 -0700 Message-Id: <20241025204743.211510-9-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ravi Kumar Vodapalli From platforms xe3 Underrun recovery does not exist v2: improve DISPLAY_VER checking BSpec: 68849 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Sai Teja Pottumuttu --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef1436146325..c904f529d0c5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -861,7 +861,7 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) */ if (IS_DG2(dev_priv)) tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; - else if (DISPLAY_VER(dev_priv) >= 13) + else if ((DISPLAY_VER(dev_priv) >= 13) && (DISPLAY_VER(dev_priv) < 30)) tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; /* Wa_14010547955:dg2 */ From patchwork Fri Oct 25 20:47:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D118D149F9 for ; Fri, 25 Oct 2024 20:47:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D807110EB91; Fri, 25 Oct 2024 20:47:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; 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a="33484210" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484210" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: Xi/DqnLZTPimeDeLAN51pA== X-CSE-MsgGUID: rS0qtm6FTe+spaa6Q3n+4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057195" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:49 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 09/11] drm/i915/display/xe3: disable x-tiled framebuffers Date: Fri, 25 Oct 2024 13:47:41 -0700 Message-Id: <20241025204743.211510-10-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: "Heikkila, Juha-pekka" Xe3 has no more support for x-tile on display. v2: Include up to display 29 for X-tiled support. (Gustavo) Signed-off-by: Heikkila, Juha-pekka Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a7b4cf8b6d50..6a7060889f40 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -349,7 +349,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .plane_caps = INTEL_PLANE_CAP_TILING_Y, }, { .modifier = I915_FORMAT_MOD_X_TILED, - .display_ver = DISPLAY_VER_ALL, + .display_ver = { 0, 29 }, .plane_caps = INTEL_PLANE_CAP_TILING_X, }, { .modifier = DRM_FORMAT_MOD_LINEAR, From patchwork Fri Oct 25 20:47:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7669CD149F5 for ; Fri, 25 Oct 2024 20:47:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 627FA10EB9A; Fri, 25 Oct 2024 20:47:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Yj57yPQI"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id EF76F10EB89; Fri, 25 Oct 2024 20:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729889269; x=1761425269; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=wir1OW34CDvY4sYHiQf10SnfJmQ3srInYnvu7N8Izh4=; b=Yj57yPQIyqtLyIfR2HMtuHIW+JqGjwJjW3mDNGXZd/sYz1fyPspV76eT 0ZhNdS2hRrXD22Ue8kqjZO6Ab5vTaHKMN24FH38fX/qFMKev/6/sbUBcp G0qKs9/GOE6627r3Cg4Umf70P++ThOUVhXGeTsMM+rhMr/eaDiThyZwh0 6ggKCLL6gA1fOUSGKXg9p6yx1VYVp9P9XAFVQ73B26BTknCMiU1nJ0S+I N+170AsV730x5FPbnOHvpUduOY54J/+GD5CoKNqbc2ynZM+w7iFSHPqiX poSTBTRbqN2sDU/Z4vQmcWWAZOkk4yKDYkfPkjDiwnyZ4rs5rbLJXe9Ow w==; X-CSE-ConnectionGUID: MdCRbmhyRKq7FRoUNoCvQA== X-CSE-MsgGUID: JJNgOZkkQpuiBeSEizNYvA== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484212" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484212" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: 2VTUz//CTZCYf7CP/TJVmA== X-CSE-MsgGUID: uBiQlYPaTEKh3ZH15MjMIA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057196" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:49 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 10/11] drm/i915/xe3lpd: Power request asserting/deasserting Date: Fri, 25 Oct 2024 13:47:42 -0700 Message-Id: <20241025204743.211510-11-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Mika Kahola There is a HW issue that arises when there are race conditions between TCSS entering/exiting TC7 or TC10 states while the driver is asserting/deasserting TCSS power request. As a workaround, Display driver will implement a mailbox sequence to ensure that the TCSS is in TC0 when TCSS power request is asserted/deasserted. The sequence is the following 1. Read mailbox command status and wait until run/busy bit is clear 2. Write mailbox data value '1' for power request asserting and '0' for power request deasserting 3. Write mailbox command run/busy bit and command value with 0x1 4. Read mailbox command and wait until run/busy bit is clear before continuing power request. Signed-off-by: Mika Kahola Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_tc.c | 40 +++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 +++++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 6f2ee7dbc43b..7d9f87db381c 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -1013,6 +1013,39 @@ xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled) return true; } +static bool xelpdp_tc_phy_wait_for_tcss_ready(struct drm_i915_private *i915, + bool enable) +{ + if (DISPLAY_VER(i915) < 30) + return true; + + /* check if mailbox is running busy */ + if (intel_de_wait_for_clear(i915, TCSS_DISP_MAILBOX_IN_CMD, + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) { + drm_dbg_kms(&i915->drm, + "timeout waiting for TCSS mailbox run/busy bit to clear\n"); + return false; + } + + if (enable) + intel_de_write(i915, TCSS_DISP_MAILBOX_IN_DATA, 1); + else + intel_de_write(i915, TCSS_DISP_MAILBOX_IN_DATA, 0); + + intel_de_write(i915, TCSS_DISP_MAILBOX_IN_CMD, + TCSS_DISP_MAILBOX_IN_CMD_DATA(1)); + + /* wait to clear mailbox running busy bit before continuing */ + if (intel_de_wait_for_clear(i915, TCSS_DISP_MAILBOX_IN_CMD, + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) { + drm_dbg_kms(&i915->drm, + "timeout waiting for TCSS mailbox run/busy bit to clear\n"); + return false; + } + + return true; +} + static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable) { struct drm_i915_private *i915 = tc_to_i915(tc); @@ -1022,6 +1055,13 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena assert_tc_cold_blocked(tc); + /* + * Gfx driver workaround for PTL tcss_rxdetect_clkswb_req/ack handshake + * violation when pwwreq= 0->1 during TC7/10 entry + */ + drm_WARN_ON(&i915->drm, + !xelpdp_tc_phy_wait_for_tcss_ready(i915, enable)); + val = intel_de_read(i915, reg); if (enable) val |= XELPDP_TCSS_POWER_REQUEST; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8d758947f301..452325c7f427 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4539,6 +4539,13 @@ enum skl_power_gate { #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) +#define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300) +#define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31) +#define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0) +#define TCSS_DISP_MAILBOX_IN_CMD_DATA(x) TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY | \ + REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, (x)) +#define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304) + #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) #define PRIMARY_SPI_REGIONID _MMIO(0x102084) From patchwork Fri Oct 25 20:47:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13851782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDD08D149F6 for ; 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X-CSE-ConnectionGUID: wSwTtu3ES2K1vsSQ7KiJvw== X-CSE-MsgGUID: /orp5A7YQ+eztrABL5WSRA== X-IronPort-AV: E=McAfee;i="6700,10204,11236"; a="33484213" X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="33484213" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:48 -0700 X-CSE-ConnectionGUID: bx997JTbRgu5ILh7SXhHiQ== X-CSE-MsgGUID: Kp394ObOQjq37IN1b/49nQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81057197" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 13:47:49 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v5 11/11] drm/xe/ptl: Enable PTL display Date: Fri, 25 Oct 2024 13:47:43 -0700 Message-Id: <20241025204743.211510-12-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025204743.211510-1-clinton.a.taylor@intel.com> References: <20241025204743.211510-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Haridhar Kalvala Signed-off-by: Haridhar Kalvala Signed-off-by: Clint Taylor --- drivers/gpu/drm/xe/xe_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 4085bb3b6550..6f73a243c24c 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -352,7 +352,7 @@ static const struct xe_device_desc bmg_desc = { static const struct xe_device_desc ptl_desc = { PLATFORM(PANTHERLAKE), - .has_display = false, + .has_display = true, .require_force_probe = true, };