From patchwork Sun Oct 27 09:14:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13852438 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 391CC36127; Sun, 27 Oct 2024 09:16:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020580; cv=none; b=fMS2CX6X4GnYvzwoYuYQ7P+s4uKjouihXzCSOSakHdY5y+VepynYQJvPy0Gc9RHTv1YQUVhBLKOQpwaDv6xACLK+haBtpoLU7Oa9Z1hskRPEFzNFKql6VHoJPJ2/17TcWQ8cuRkoGH2ow8lXrEqUZH9xCiNiXwTbc8IuKNKhuBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020580; c=relaxed/simple; bh=rlT2DPWfdxZcYFjIBa/WQeWWhpaYtrcCeHY85Lo4sTQ=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=MvXl+F5FhEpgXvtVC5/lzNdBJ9fFd72hpzhMHW/neCmeRNLSHXEOwLCMfTenMbSpupwW0tg5Zq232izqB0ut7G1YeCs9ETgS/uQm7YPAPgG0qRgQkG7gtm07DtbuoRIeaTvEXHU0cmZmZu8Kfs1XOCZhEVlas1yMOFudtyDkm8A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=JAeGPuby; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="JAeGPuby" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id D3311A064A; Sun, 27 Oct 2024 10:16:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:message-id:mime-version:reply-to:subject:subject:to :to; s=mail; bh=v2RgTF8D7wajG55pSlawfkLKs/fqiaH4u0qyD0R2ays=; b= JAeGPuby8nxdIEYgU2LCUerbt/ZvBPMny1rJkNCI2pKv3Sk0QgkOjz0cjGH3Nk7Q p/Ns574Z+UhSoxZWFyt5hqk20Js44Iu7lvJNgQ8Qn556IioEO5+TXj0gFgBmW+Z8 jsJ8ruco7CcqJNJzunDsGNDtPDIWtbrSVKkAfS3wUmmdXL3VaX5tmrXT5A3XPyiJ TLikMrJX0lcNhYNKvju8YgwSoPPWDiTchntqDyzMEOrq707xiVyHZe4mbHpYSZzp O+nzibGLj0Mulbczf04geSgCM9XWCdT91EalnFc4gjZcASvkcz8ms6WSLnyTpSTQ +blRZjRxdZzB4zr28hPNsOyN4U8YBX38lCmjd0qKoZK+7gj9w92mCJa6tMaUiDE/ JYJkeT9a9b/19IMdvbLcmaq0I3VSOa1WNGwdCE9VVwMzBdia3DoGQjj4opMYl9Ut mdhlOh4HrPZXUHJZ6r7q5rDNSPYGHHVjNPSdmKMBc0IceB80yAQqecelT05gfJ+I wkVosmC67Jl9+jz5TxNQ11ZAeSisOyYS7IdLTvM8YlN1kZkT8WcpU/6RM60WWo+v ACQU9FNxCnIF5/iQWJ1AzIuGNbxDbtjqJsp8cNvVBq1rR0TWNOi2K+FNsBkJDsQP VWkHaR9/cCG4vdUp6Azr9yRIEDFeLxKbz0eFSMM7j5o= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: , , , CC: Mesih Kilinc , =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [PATCH v2 01/10] dma-engine: sun4i: Add a quirk to support different chips Date: Sun, 27 Oct 2024 10:14:31 +0100 Message-ID: <20241027091440.1913863-1-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1730020571;VERSION=7978;MC=2647821118;ID=156036;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677D65 From: Mesih Kilinc Allwinner suniv F1C100s has similar DMA engine to sun4i. Several registers has different addresses. Total dma channels, endpoint counts and max burst counts are also different. In order to support F1C100s add a quirk structure to hold IC specific data. Signed-off-by: Mesih Kilinc [ csokas.bence: Resolve conflict in `sun4i_dma_prep_dma_cyclic()`, fix whitespace ] Signed-off-by: Csókás, Bence --- Notes: Changes in v2: * Whitespace drivers/dma/sun4i-dma.c | 138 ++++++++++++++++++++++++++++++---------- 1 file changed, 106 insertions(+), 32 deletions(-) diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index 2e7f9b07fdd2..d472f57a39ea 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,8 @@ #define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5) #define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type) +#define SUN4I_MAX_BURST 8 + /** Normal DMA register values **/ /* Normal DMA source/destination data request type values */ @@ -132,6 +135,32 @@ #define SUN4I_DDMA_MAX_SEG_SIZE SZ_16M #define SUN4I_DMA_MAX_SEG_SIZE SUN4I_NDMA_MAX_SEG_SIZE +/* + * Hardware channels / ports representation + * + * The hardware is used in several SoCs, with differing numbers + * of channels and endpoints. This structure ties those numbers + * to a certain compatible string. + */ +struct sun4i_dma_config { + u32 ndma_nr_max_channels; + u32 ndma_nr_max_vchans; + + u32 ddma_nr_max_channels; + u32 ddma_nr_max_vchans; + + u32 dma_nr_max_channels; + + void (*set_dst_data_width)(u32 *p_cfg, s8 data_width); + void (*set_src_data_width)(u32 *p_cfg, s8 data_width); + int (*convert_burst)(u32 maxburst); + + u8 ndma_drq_sdram; + u8 ddma_drq_sdram; + + u8 max_burst; +}; + struct sun4i_dma_pchan { /* Register base of channel */ void __iomem *base; @@ -170,7 +199,7 @@ struct sun4i_dma_contract { }; struct sun4i_dma_dev { - DECLARE_BITMAP(pchans_used, SUN4I_DMA_NR_MAX_CHANNELS); + unsigned long *pchans_used; struct dma_device slave; struct sun4i_dma_pchan *pchans; struct sun4i_dma_vchan *vchans; @@ -178,6 +207,7 @@ struct sun4i_dma_dev { struct clk *clk; int irq; spinlock_t lock; + const struct sun4i_dma_config *cfg; }; static struct sun4i_dma_dev *to_sun4i_dma_dev(struct dma_device *dev) @@ -200,7 +230,17 @@ static struct device *chan2dev(struct dma_chan *chan) return &chan->dev->device; } -static int convert_burst(u32 maxburst) +static void set_dst_data_width_a10(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUN4I_DMA_CFG_DST_DATA_WIDTH(data_width); +} + +static void set_src_data_width_a10(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(data_width); +} + +static int convert_burst_a10(u32 maxburst) { if (maxburst > 8) return -EINVAL; @@ -233,15 +273,15 @@ static struct sun4i_dma_pchan *find_and_use_pchan(struct sun4i_dma_dev *priv, int i, max; /* - * pchans 0-SUN4I_NDMA_NR_MAX_CHANNELS are normal, and - * SUN4I_NDMA_NR_MAX_CHANNELS+ are dedicated ones + * pchans 0-priv->cfg->ndma_nr_max_channels are normal, and + * priv->cfg->ndma_nr_max_channels+ are dedicated ones */ if (vchan->is_dedicated) { - i = SUN4I_NDMA_NR_MAX_CHANNELS; - max = SUN4I_DMA_NR_MAX_CHANNELS; + i = priv->cfg->ndma_nr_max_channels; + max = priv->cfg->dma_nr_max_channels; } else { i = 0; - max = SUN4I_NDMA_NR_MAX_CHANNELS; + max = priv->cfg->ndma_nr_max_channels; } spin_lock_irqsave(&priv->lock, flags); @@ -444,6 +484,7 @@ generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, size_t len, struct dma_slave_config *sconfig, enum dma_transfer_direction direction) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_promise *promise; int ret; @@ -467,13 +508,13 @@ generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, sconfig->src_addr_width, sconfig->dst_addr_width); /* Source burst */ - ret = convert_burst(sconfig->src_maxburst); + ret = priv->cfg->convert_burst(sconfig->src_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_SRC_BURST_LENGTH(ret); /* Destination burst */ - ret = convert_burst(sconfig->dst_maxburst); + ret = priv->cfg->convert_burst(sconfig->dst_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_DST_BURST_LENGTH(ret); @@ -482,13 +523,13 @@ generate_ndma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, ret = convert_buswidth(sconfig->src_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(ret); + priv->cfg->set_src_data_width(&promise->cfg, ret); /* Destination bus width */ ret = convert_buswidth(sconfig->dst_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_DST_DATA_WIDTH(ret); + priv->cfg->set_dst_data_width(&promise->cfg, ret); return promise; @@ -510,6 +551,7 @@ static struct sun4i_dma_promise * generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, size_t len, struct dma_slave_config *sconfig) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_promise *promise; int ret; @@ -524,13 +566,13 @@ generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, SUN4I_DDMA_CFG_BYTE_COUNT_MODE_REMAIN; /* Source burst */ - ret = convert_burst(sconfig->src_maxburst); + ret = priv->cfg->convert_burst(sconfig->src_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_SRC_BURST_LENGTH(ret); /* Destination burst */ - ret = convert_burst(sconfig->dst_maxburst); + ret = priv->cfg->convert_burst(sconfig->dst_maxburst); if (ret < 0) goto fail; promise->cfg |= SUN4I_DMA_CFG_DST_BURST_LENGTH(ret); @@ -539,13 +581,13 @@ generate_ddma_promise(struct dma_chan *chan, dma_addr_t src, dma_addr_t dest, ret = convert_buswidth(sconfig->src_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(ret); + priv->cfg->set_src_data_width(&promise->cfg, ret); /* Destination bus width */ ret = convert_buswidth(sconfig->dst_addr_width); if (ret < 0) goto fail; - promise->cfg |= SUN4I_DMA_CFG_DST_DATA_WIDTH(ret); + priv->cfg->set_dst_data_width(&promise->cfg, ret); return promise; @@ -622,6 +664,7 @@ static struct dma_async_tx_descriptor * sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan); struct dma_slave_config *sconfig = &vchan->cfg; struct sun4i_dma_promise *promise; @@ -638,8 +681,8 @@ sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, */ sconfig->src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; sconfig->dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - sconfig->src_maxburst = 8; - sconfig->dst_maxburst = 8; + sconfig->src_maxburst = priv->cfg->max_burst; + sconfig->dst_maxburst = priv->cfg->max_burst; if (vchan->is_dedicated) promise = generate_ddma_promise(chan, src, dest, len, sconfig); @@ -654,11 +697,13 @@ sun4i_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, /* Configure memcpy mode */ if (vchan->is_dedicated) { - promise->cfg |= SUN4I_DMA_CFG_SRC_DRQ_TYPE(SUN4I_DDMA_DRQ_TYPE_SDRAM) | - SUN4I_DMA_CFG_DST_DRQ_TYPE(SUN4I_DDMA_DRQ_TYPE_SDRAM); + promise->cfg |= + SUN4I_DMA_CFG_SRC_DRQ_TYPE(priv->cfg->ddma_drq_sdram) | + SUN4I_DMA_CFG_DST_DRQ_TYPE(priv->cfg->ddma_drq_sdram); } else { - promise->cfg |= SUN4I_DMA_CFG_SRC_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM) | - SUN4I_DMA_CFG_DST_DRQ_TYPE(SUN4I_NDMA_DRQ_TYPE_SDRAM); + promise->cfg |= + SUN4I_DMA_CFG_SRC_DRQ_TYPE(priv->cfg->ndma_drq_sdram) | + SUN4I_DMA_CFG_DST_DRQ_TYPE(priv->cfg->ndma_drq_sdram); } /* Fill the contract with our only promise */ @@ -673,6 +718,7 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len, size_t period_len, enum dma_transfer_direction dir, unsigned long flags) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan); struct dma_slave_config *sconfig = &vchan->cfg; struct sun4i_dma_promise *promise; @@ -696,11 +742,11 @@ sun4i_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf, size_t len, if (vchan->is_dedicated) { io_mode = SUN4I_DDMA_ADDR_MODE_IO; linear_mode = SUN4I_DDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_DDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ddma_drq_sdram; } else { io_mode = SUN4I_NDMA_ADDR_MODE_IO; linear_mode = SUN4I_NDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_NDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ndma_drq_sdram; } if (dir == DMA_MEM_TO_DEV) { @@ -793,6 +839,7 @@ sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction dir, unsigned long flags, void *context) { + struct sun4i_dma_dev *priv = to_sun4i_dma_dev(chan->device); struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan); struct dma_slave_config *sconfig = &vchan->cfg; struct sun4i_dma_promise *promise; @@ -818,11 +865,11 @@ sun4i_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, if (vchan->is_dedicated) { io_mode = SUN4I_DDMA_ADDR_MODE_IO; linear_mode = SUN4I_DDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_DDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ddma_drq_sdram; } else { io_mode = SUN4I_NDMA_ADDR_MODE_IO; linear_mode = SUN4I_NDMA_ADDR_MODE_LINEAR; - ram_type = SUN4I_NDMA_DRQ_TYPE_SDRAM; + ram_type = priv->cfg->ndma_drq_sdram; } if (dir == DMA_MEM_TO_DEV) @@ -1150,6 +1197,10 @@ static int sun4i_dma_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + priv->cfg = of_device_get_match_data(&pdev->dev); + if (!priv->cfg) + return -ENODEV; + priv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); @@ -1197,23 +1248,26 @@ static int sun4i_dma_probe(struct platform_device *pdev) priv->slave.dev = &pdev->dev; - priv->pchans = devm_kcalloc(&pdev->dev, SUN4I_DMA_NR_MAX_CHANNELS, + priv->pchans = devm_kcalloc(&pdev->dev, priv->cfg->dma_nr_max_channels, sizeof(struct sun4i_dma_pchan), GFP_KERNEL); priv->vchans = devm_kcalloc(&pdev->dev, SUN4I_DMA_NR_MAX_VCHANS, sizeof(struct sun4i_dma_vchan), GFP_KERNEL); - if (!priv->vchans || !priv->pchans) + priv->pchans_used = devm_kcalloc(&pdev->dev, + BITS_TO_LONGS(priv->cfg->dma_nr_max_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!priv->vchans || !priv->pchans || !priv->pchans_used) return -ENOMEM; /* - * [0..SUN4I_NDMA_NR_MAX_CHANNELS) are normal pchans, and - * [SUN4I_NDMA_NR_MAX_CHANNELS..SUN4I_DMA_NR_MAX_CHANNELS) are + * [0..priv->cfg->ndma_nr_max_channels) are normal pchans, and + * [priv->cfg->ndma_nr_max_channels..priv->cfg->dma_nr_max_channels) are * dedicated ones */ - for (i = 0; i < SUN4I_NDMA_NR_MAX_CHANNELS; i++) + for (i = 0; i < priv->cfg->ndma_nr_max_channels; i++) priv->pchans[i].base = priv->base + SUN4I_NDMA_CHANNEL_REG_BASE(i); - for (j = 0; i < SUN4I_DMA_NR_MAX_CHANNELS; i++, j++) { + for (j = 0; i < priv->cfg->dma_nr_max_channels; i++, j++) { priv->pchans[i].base = priv->base + SUN4I_DDMA_CHANNEL_REG_BASE(j); priv->pchans[i].is_dedicated = 1; @@ -1284,8 +1338,28 @@ static void sun4i_dma_remove(struct platform_device *pdev) clk_disable_unprepare(priv->clk); } +static struct sun4i_dma_config sun4i_a10_dma_cfg = { + .ndma_nr_max_channels = SUN4I_NDMA_NR_MAX_CHANNELS, + .ndma_nr_max_vchans = SUN4I_NDMA_NR_MAX_VCHANS, + + .ddma_nr_max_channels = SUN4I_DDMA_NR_MAX_CHANNELS, + .ddma_nr_max_vchans = SUN4I_DDMA_NR_MAX_VCHANS, + + .dma_nr_max_channels = SUN4I_NDMA_NR_MAX_CHANNELS + + SUN4I_DDMA_NR_MAX_CHANNELS, + + .set_dst_data_width = set_dst_data_width_a10, + .set_src_data_width = set_src_data_width_a10, + .convert_burst = convert_burst_a10, + + .ndma_drq_sdram = SUN4I_NDMA_DRQ_TYPE_SDRAM, + .ddma_drq_sdram = SUN4I_DDMA_DRQ_TYPE_SDRAM, + + .max_burst = SUN4I_MAX_BURST, +}; + static const struct of_device_id sun4i_dma_match[] = { - { .compatible = "allwinner,sun4i-a10-dma" }, + { .compatible = "allwinner,sun4i-a10-dma", .data = &sun4i_a10_dma_cfg }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun4i_dma_match); From patchwork Sun Oct 27 09:14:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13852439 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BEEE3FB0E; Sun, 27 Oct 2024 09:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020593; cv=none; b=uKj1AJhPil1Ae2BmMLUzUKRozW9RsrltuuoBK6Mi8pnZxLXJFRD7Q3V1jMyVuRVh2jPa1jB2jaq8mjwadsFRM4HUzSjFwCmt+kbXIYxnxnQfmB1Hs2DipWleumSyTOkl1Jgp4PkRsfNGk907p1GyG2eoTUr5ESbdqdO/kRcKaPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020593; c=relaxed/simple; bh=7pPG+S+CIZqN4g6kTG+np6jTj/xYcf8tKCYUcEo2HHU=; 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Sun, 27 Oct 2024 10:16:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=+DaEwnlS4lOD6gl8n5IC 4q8JgYWiQY3dTRRDj5Yl7Z8=; b=KzT7PcH5Lo5iMZPKc50bWNLOKAuIFZ8dsMdE /Gk2LC65IF03H2kmNsHR28NL553CuWdovXtj9wDh2SfhgP3guL4zA46XbrkR4ehK xuWCimb5u5jFXzJszkxVD88Cguj92U0LczDpDCqgCSuuqqU+b1+8A2h80L9SXo/v Rss8nLw5HEDJS974he7iooe7H3NbfvneWJmnxPW/gFnFYh1qDJkiOi2m+1U6rClU uNZU0PAMi2PsE6oyk9CaJffxrVrELGsEslykgvLSPQFdAnXT2tQDe2G58tliwHrV 0wJRr+UNSN5AHg65EXpsvUDMRYkeOccsdOZURJM/tqhOguAaZKX4CpdbIGf8xCKW 98r9x57wAK3LOr15FDBlxCD3ut1lIsFQTyQSFSDP1tNxlFuhklfLUqUyiains4Tl A8eII85YT0sBDu5VX4MbqCdmzqDMVGuh1iepTL3nxE4qFIIcyqmVY7+qqFbr2X3Z 41eVGVWEmGIpaadeWJvIYFnIn3Fm327W2mFYGqHCnyWJCVgQzjjGf2vIIjq/1Y3W Rm838w7zlNIbvv/JYKa2OmpQ5mPdJhM64M3F0dMOw4fqkc0J2+nBlArV1+aEuEOG D8u+fmkOdfFI6AJuN9Stx31UhoFImHf7LRgxO+Zgn4lvpu0UStFyqobpzTe66ejC s9e4KjY= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: , , , CC: Mesih Kilinc , =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Philipp Zabel" Subject: [PATCH v2 02/10] dma-engine: sun4i: Add has_reset option to quirk Date: Sun, 27 Oct 2024 10:14:32 +0100 Message-ID: <20241027091440.1913863-2-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241027091440.1913863-1-csokas.bence@prolan.hu> References: <20241027091440.1913863-1-csokas.bence@prolan.hu> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1730020588;VERSION=7978;MC=1266469769;ID=156037;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677D65 From: Mesih Kilinc Allwinner suniv F1C100s has a reset bit for DMA in CCU. Sun4i do not has this bit but in order to support suniv we need to add it. So add support for reset bit. Signed-off-by: Mesih Kilinc [ csokas.bence: Rebased and addressed comments ] Signed-off-by: Csókás, Bence --- Notes: Changes in v2: * Call reset_control_deassert() unconditionally, as it supports optional resets * Use dev_err_probe() * Whitespace drivers/dma/sun4i-dma.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index d472f57a39ea..0a45089461e1 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -159,6 +160,7 @@ struct sun4i_dma_config { u8 ddma_drq_sdram; u8 max_burst; + bool has_reset; }; struct sun4i_dma_pchan { @@ -208,6 +210,7 @@ struct sun4i_dma_dev { int irq; spinlock_t lock; const struct sun4i_dma_config *cfg; + struct reset_control *rst; }; static struct sun4i_dma_dev *to_sun4i_dma_dev(struct dma_device *dev) @@ -1215,6 +1218,15 @@ static int sun4i_dma_probe(struct platform_device *pdev) return PTR_ERR(priv->clk); } + if (priv->cfg->has_reset) { + priv->rst = devm_reset_control_get_exclusive(&pdev->dev, + NULL); + if (IS_ERR(priv->rst)) { + dev_err_probe(&pdev->dev, "Failed to get reset control\n"); + return PTR_ERR(priv->rst); + } + } + platform_set_drvdata(pdev, priv); spin_lock_init(&priv->lock); @@ -1287,6 +1299,14 @@ static int sun4i_dma_probe(struct platform_device *pdev) return ret; } + /* Deassert the reset control */ + ret = reset_control_deassert(priv->rst); + if (ret) { + dev_err(&pdev->dev, + "Failed to deassert the reset control\n"); + goto err_clk_disable; + } + /* * Make sure the IRQs are all disabled and accounted for. The bootloader * likes to leave these dirty @@ -1356,6 +1376,7 @@ static struct sun4i_dma_config sun4i_a10_dma_cfg = { .ddma_drq_sdram = SUN4I_DDMA_DRQ_TYPE_SDRAM, .max_burst = SUN4I_MAX_BURST, + .has_reset = false, }; static const struct of_device_id sun4i_dma_match[] = { From patchwork Sun Oct 27 09:14:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13852443 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BBEB44375; Sun, 27 Oct 2024 09:17:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020676; cv=none; b=tH1JCOIceX0gLObshwcBouvK6J82S/HbbIv4RPfaVKTXKICNQajt4PfplLUTiSXTI5xy2KKLrGmh68XMUMhcTMzWq6f6KZlIG7EI23Zo9FynkvIr7aS5iJVIYxJR76Yl5TaktPxL0BIA2qDj5RvxJPtCM8rBNXMf+Xs4dTGoQEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020676; c=relaxed/simple; bh=on+3n6AX8EH0bGq2EJvJqehiEym1ZHFWXYiM7nG3xAY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tqM+qHSjXtBZ1Oc8MPqgyRVFgT9ShFx5Wve8hIB/Oa2rUnY+FAqMgi8xAUBQdBlfbNe+6KQEVcmD07aswnMefuQzMt8waCl9VlWo/py14+0etdKirmZRJfA5rCUQapEMibfBS+eKQGYbg+fSHdF64qRNaQSi4qyYZihy0BpMbdo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=l/glu0QV; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="l/glu0QV" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id BE55FA064A; Sun, 27 Oct 2024 10:17:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=EWnfSa/E3TDYuPzWXzSP ismhOqK3UCMzs66VsrbxYl4=; b=l/glu0QV8NTIZ66YNSVUhoaR9YoRGczU1InJ urCfdoQXlCnVVekGVY8sXpGWIpk1DixcjFP0pRwXKfpM7S00tDXZDQuXiBpskaZO g3E4wkDmAG2cmdw0Y8/8HPbyTQuffWO60Rgoy/zAgpWRnUVvWVOH1VYq7qkxFQfR DBWnjjFZAQlCBWrJw2ihcV7OGMXQTVmMI66sgfZc21MZnn3hpj+aikG+ezC09iTz Z3xwl60rkNknhTZuPH5bIbZKPdMID5+672RUHkh9Q4W54upHiVpxCNDZ/xrl4YAF 2NBawj4SikdUaIrxuhDn3kwJs2MeVhD0aeCVi0kN91rPUMhRijm7bYWC7suxWTr5 dAAv9mK5GR8gSE/XpRPyWlUbbonLUgtC0KukRETRm0qhdiImW097gwahnzLFJ0w+ UoIwJbHC8utUFqhg8dgaafyYCaY2/5z93JZCUTgeVVLD3IFXODeyA/IaM7DL+sch xJ5vcMJZDCodFDsuEzggrb1EsQk/RqXYG+FEJxMdP2aTKoBkyTyT7ztO0Xk+MLFi NS4kE4VIDA7mKYFGMtzjRoFbDn0bW23072QZcLgxFnoIbUPDHXs0DWcOEK9x2RpQ GFQWTfMTqzfC/KDe3dZJG5Z8oO7t0yYPh1/wJbuItePk5LIJlW3E8w4zwv0kuhKn fDYuiu4= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: Chen-Yu Tsai , Maxime Ripard , , , , , CC: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= , "Conor Dooley" , Vinod Koul , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Jernej Skrabec , Samuel Holland Subject: [PATCH v2 03/10] dt-bindings: dmaengine: Add Allwinner suniv F1C100s DMA Date: Sun, 27 Oct 2024 10:14:34 +0100 Message-ID: <20241027091440.1913863-3-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241027091440.1913863-1-csokas.bence@prolan.hu> References: <20241027091440.1913863-1-csokas.bence@prolan.hu> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1730020672;VERSION=7978;MC=2900419732;ID=156038;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677D65 Add compatible string for Allwinner suniv F1C100s DMA. Acked-by: Conor Dooley Link: https://lore.kernel.org/linux-kernel/20241024-recycler-borrowing-5d4296fd4a56@spud/ [ csokas.bence: Reimplemented Mesih Kilinc's binding in YAML ] Signed-off-by: Csókás, Bence --- .../devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml index 02d5bd035409..9b5180c0a7c4 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml @@ -22,7 +22,9 @@ properties: number. compatible: - const: allwinner,sun4i-a10-dma + enum: + - allwinner,sun4i-a10-dma + - allwinner,suniv-f1c100s-dma reg: maxItems: 1 From patchwork Sun Oct 27 09:14:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmVuY2UgQ3PDs2vDoXM=?= X-Patchwork-Id: 13852444 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DA94433D0; Sun, 27 Oct 2024 09:21:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020863; cv=none; b=X4mGKj+ES6tcvbGsG7ow/KmzVW8q1BcYSl8mIy9YTpkGUKUeLLE9Uwg65sI/fJu20aI+EhKrpCQY9AniGD0hUyYEX4xRI+g6Tf5BaMQJlrCoky3xzy3AKnHSbGH0pjs1VLIFCGvgAF+PpInpqb0uToK2ZMmJLmoQPOMz1Y1AB2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730020863; c=relaxed/simple; bh=Udk2D3bPQa/VRBXaI/JkL47MYkVvJvr2ZMxMf3jtQss=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dNX8FkfgYmxJw0yzpuhBWSm0P67PdZI79eQFo1XoiLQvJ9tlmhRVnX9ITXJUNI2jtMat/9ePUW/cd9ql/FBMiCUsBtHzqo5p+LOugEc9/dkxS0iA46SI7X9wuPFAE/5esXFyD/Rw8nwQR97WFcivg6iJ5Apy9bgu2kX4A+uTMfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=peYzhbck; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="peYzhbck" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id 67977A064A; Sun, 27 Oct 2024 10:20:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=ZDNKPYZEifl3ipQUUda/ JljLACm3upo4aMWFTa7LXdA=; b=peYzhbckZTAnjTcS48bdzBak4B5XRxE7XR8M t2gnUOrZkNyk2sObNx5dXJiJCqfZWjOgl+TNYNgL2gFqQAAvztUDByt2RryQTXbt mHAatWI9YRGgcD7A2UMW/oelxh0sCR6fBkpuwRjuNN519BX4i4lbKyi+DqWeZBEv X/ewrogjOEROS3SlDH/bzJmJdNtEVZjAlG1zLco7+fyngPjLBv2DF9MQspypj78c SWnz/w7kVx2vDMUECr/FU76gLMQll4y+0ybGmJ5JKQrHR2v/gEyOcPphNFkwMJl9 8H9c8oPBlsz4D4+uyYWoDVG/ocdqBN+yeRIWD2XT1G0Mt6+NxfYx1DGWOmy8SrGO kFMyc/i6xf4A5N1xJe5537SHVr7r9Tm3PFHY8kTQhqxr/LMS2ixcXqYGTbyhTH+b ThX7oc4pilQdGHFtQLZNlwtKNd3SYX4Sx60DtjGZZE/a/sZ+7houK9A9DRcXDvUJ dI4ACrnEIHEsJVaMZVOHYMMO/mRZcJTY02mVCnC+cBZi9zaHuzsAhzdVdXeBZvg3 IShO0uMOAtEhOApzuQaFrU/xwyFwjkGUk8/zXhgzSHfXxr4NUcx1Do1rkBxJ6deu 9vsnZS/BnJj6LTUI3xHUItBT5ag/IB5L4eaoRq2fos+5vaLvCKP1nVb2179n0r6s SOFEWPw= From: =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= To: , , , CC: Mesih Kilinc , =?utf-8?b?Q3PDs2vDoXMsIEJlbmNl?= , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Subject: [PATCH v2 04/10] dma-engine: sun4i: Add support for Allwinner suniv F1C100s Date: Sun, 27 Oct 2024 10:14:35 +0100 Message-ID: <20241027091440.1913863-4-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241027091440.1913863-1-csokas.bence@prolan.hu> References: <20241027091440.1913863-1-csokas.bence@prolan.hu> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1730020858;VERSION=7978;MC=1001936460;ID=156040;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94855677D65 From: Mesih Kilinc DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4 DDMA channels and endpoints are different. Also F1C100s has reset bit for DMA in CCU. Add support for it. Signed-off-by: Mesih Kilinc [ csokas.bence: Rebased on current master ] Signed-off-by: Csókás, Bence --- drivers/dma/Kconfig | 4 +-- drivers/dma/sun4i-dma.c | 60 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index d9ec1e69e428..fc25bfc356f3 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -162,8 +162,8 @@ config DMA_SA11X0 config DMA_SUN4I tristate "Allwinner A10 DMA SoCs support" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I - default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV + default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV) select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index 0a45089461e1..cb52976b56aa 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -33,7 +33,11 @@ #define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5) #define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type) +#define SUNIV_DMA_CFG_DST_DATA_WIDTH(width) ((width) << 24) +#define SUNIV_DMA_CFG_SRC_DATA_WIDTH(width) ((width) << 8) + #define SUN4I_MAX_BURST 8 +#define SUNIV_MAX_BURST 4 /** Normal DMA register values **/ @@ -41,6 +45,9 @@ #define SUN4I_NDMA_DRQ_TYPE_SDRAM 0x16 #define SUN4I_NDMA_DRQ_TYPE_LIMIT (0x1F + 1) +#define SUNIV_NDMA_DRQ_TYPE_SDRAM 0x11 +#define SUNIV_NDMA_DRQ_TYPE_LIMIT (0x17 + 1) + /** Normal DMA register layout **/ /* Dedicated DMA source/destination address mode values */ @@ -54,6 +61,9 @@ #define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15) #define SUN4I_NDMA_CFG_SRC_NON_SECURE BIT(6) +#define SUNIV_NDMA_CFG_CONT_MODE BIT(29) +#define SUNIV_NDMA_CFG_WAIT_STATE(n) ((n) << 26) + /** Dedicated DMA register values **/ /* Dedicated DMA source/destination address mode values */ @@ -66,6 +76,9 @@ #define SUN4I_DDMA_DRQ_TYPE_SDRAM 0x1 #define SUN4I_DDMA_DRQ_TYPE_LIMIT (0x1F + 1) +#define SUNIV_DDMA_DRQ_TYPE_SDRAM 0x1 +#define SUNIV_DDMA_DRQ_TYPE_LIMIT (0x9 + 1) + /** Dedicated DMA register layout **/ /* Dedicated DMA configuration register layout */ @@ -119,6 +132,11 @@ #define SUN4I_DMA_NR_MAX_VCHANS \ (SUN4I_NDMA_NR_MAX_VCHANS + SUN4I_DDMA_NR_MAX_VCHANS) +#define SUNIV_NDMA_NR_MAX_CHANNELS 4 +#define SUNIV_DDMA_NR_MAX_CHANNELS 4 +#define SUNIV_NDMA_NR_MAX_VCHANS (24 * 2 - 1) +#define SUNIV_DDMA_NR_MAX_VCHANS 10 + /* This set of SUN4I_DDMA timing parameters were found experimentally while * working with the SPI driver and seem to make it behave correctly */ #define SUN4I_DDMA_MAGIC_SPI_PARAMETERS \ @@ -243,6 +261,16 @@ static void set_src_data_width_a10(u32 *p_cfg, s8 data_width) *p_cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(data_width); } +static void set_dst_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUNIV_DMA_CFG_DST_DATA_WIDTH(data_width); +} + +static void set_src_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUNIV_DMA_CFG_SRC_DATA_WIDTH(data_width); +} + static int convert_burst_a10(u32 maxburst) { if (maxburst > 8) @@ -252,6 +280,15 @@ static int convert_burst_a10(u32 maxburst) return (maxburst >> 2); } +static int convert_burst_f1c100s(u32 maxburst) +{ + if (maxburst > 4) + return -EINVAL; + + /* 1 -> 0, 4 -> 1 */ + return (maxburst >> 2); +} + static int convert_buswidth(enum dma_slave_buswidth addr_width) { if (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) @@ -1379,8 +1416,31 @@ static struct sun4i_dma_config sun4i_a10_dma_cfg = { .has_reset = false, }; +static struct sun4i_dma_config suniv_f1c100s_dma_cfg = { + .ndma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS, + .ndma_nr_max_vchans = SUNIV_NDMA_NR_MAX_VCHANS, + + .ddma_nr_max_channels = SUNIV_DDMA_NR_MAX_CHANNELS, + .ddma_nr_max_vchans = SUNIV_DDMA_NR_MAX_VCHANS, + + .dma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS + + SUNIV_DDMA_NR_MAX_CHANNELS, + + .set_dst_data_width = set_dst_data_width_f1c100s, + .set_src_data_width = set_src_data_width_f1c100s, + .convert_burst = convert_burst_f1c100s, + + .ndma_drq_sdram = SUNIV_NDMA_DRQ_TYPE_SDRAM, + .ddma_drq_sdram = SUNIV_DDMA_DRQ_TYPE_SDRAM, + + .max_burst = SUNIV_MAX_BURST, + .has_reset = true, +}; + static const struct of_device_id sun4i_dma_match[] = { { .compatible = "allwinner,sun4i-a10-dma", .data = &sun4i_a10_dma_cfg }, + { .compatible = "allwinner,suniv-f1c100s-dma", + .data = &suniv_f1c100s_dma_cfg }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun4i_dma_match);