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Documentation is available in NXP i.MX6Q Reference Manual. Implement the hw_reset function in sdhci_ops asserting reset for at least 10us and waiting an extra 300us after deassertion. These particular delays were inspired by sunxi-mmc hw_reset function. Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is still accessible after boot. eMMC extcsd has RST_N_FUNCTION=0x01, i.e. reset input enabled, Linux v5.15. Signed-off-by: Josua Mayer --- drivers/mmc/host/sdhci-esdhc-imx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) --- base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc change-id: 20241027-imx-emmc-reset-7127d311174c Best regards, diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 8f0bc6dca2b0402fd2a0695903cf261a5b4e19dc..ebcfa427cca6cc2791a1701a3515ef6515779aa4 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -33,6 +33,8 @@ #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f #define ESDHC_CTRL_D3CD 0x08 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) +#define ESDHC_SYS_CTRL 0x2c +#define ESDHC_SYS_CTRL_IPP_RST_N BIT(23) /* VENDOR SPEC register */ #define ESDHC_VENDOR_SPEC 0xc0 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) @@ -1402,6 +1404,15 @@ static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) return 0; } +static void esdhc_hw_reset(struct sdhci_host *host) +{ + esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0, ESDHC_SYS_CTRL); + udelay(10); + esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, + ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYS_CTRL); + udelay(300); +} + static struct sdhci_ops sdhci_esdhc_ops = { .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, @@ -1420,6 +1431,7 @@ static struct sdhci_ops sdhci_esdhc_ops = { .reset = esdhc_reset, .irq = esdhc_cqhci_irq, .dump_vendor_regs = esdhc_dump_debug_regs, + .hw_reset = esdhc_hw_reset, }; static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {