From patchwork Tue Mar 12 07:45:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minas Harutyunyan X-Patchwork-Id: 10848689 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 340371669 for ; Tue, 12 Mar 2019 07:45:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1CB72293D8 for ; Tue, 12 Mar 2019 07:45:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 099D6293FF; Tue, 12 Mar 2019 07:45:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 86023293D8 for ; Tue, 12 Mar 2019 07:45:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726717AbfCLHp0 (ORCPT ); Tue, 12 Mar 2019 03:45:26 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:36968 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726614AbfCLHp0 (ORCPT ); Tue, 12 Mar 2019 03:45:26 -0400 Received: from mailhost.synopsys.com (badc-mailhost2.synopsys.com [10.192.0.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtprelay.synopsys.com (Postfix) with ESMTPS id 97E6810C1923; Tue, 12 Mar 2019 00:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1552376725; bh=ayouBfKgRo7vAmr5vPnDjhBTy7giQdzxOyFm/DPCa5o=; h=Date:From:Subject:To:CC:From; b=iCsa9MSvlat58J0SsYs5oNMTBgJNnVBLK7i5l+hW82PxQW4QLO7g3C1RtRg54EyRe NM53LtvxHlpLWw96KkEddKJS9LTANSxIpHT1WR7EyiShMfdU+R1GmZsn+T5/9QLNAJ 9JaAoMMJFMWHCzwcqk4th1fUnA9bILriPk/AuOzxZVF+B4g/knNMAoIaU5CWGEi1Oh GQnP3LmDe8y3UcufTXCa1g4V1EUq8i50hKezLqP4MmtufXdxCyvpWY8hX1FlZaklK6 WIb/zcm89oFte7a5S2lsEK5xBoKo2z6xp5JdUZ9/RMEZhN9zxl+P040a0kX2asC7eB IfQOL60mhO4Fg== Received: from US01WEHTC3.internal.synopsys.com (us01wehtc3.internal.synopsys.com [10.15.84.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPS id 61BFCA0066; Tue, 12 Mar 2019 07:45:25 +0000 (UTC) Received: from US01WEHTC2.internal.synopsys.com (10.12.239.237) by US01WEHTC3.internal.synopsys.com (10.15.84.232) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 12 Mar 2019 00:45:25 -0700 Received: from hminas-z420 (10.13.184.20) by US01WEHTC2.internal.synopsys.com (10.12.239.238) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 12 Mar 2019 00:45:17 -0700 Received: by hminas-z420 (sSMTP sendmail emulation); Tue, 12 Mar 2019 11:45:12 +0400 Date: Tue, 12 Mar 2019 11:45:12 +0400 Message-ID: <28990c019bfb4a16ca992df625a1df040c164321.1552376546.git.hminas@synopsys.com> From: Minas Harutyunyan Subject: [PATCH] usb: dwc2: Delayed status support To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , CC: John Youn MIME-Version: 1.0 X-Originating-IP: [10.13.184.20] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added delayed status support for Control transfers. Tested in all 3 modes: Slave, BDMA and DDMA. Performed tests: USB CV (Ch9 and MSC), Control Read/Write tests using Synopsys USB test environment function driver. Signed-off-by: Minas Harutyunyan --- drivers/usb/dwc2/core.h | 2 ++ drivers/usb/dwc2/gadget.c | 31 +++++++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 30bab8463c96..b4071d9bfbc8 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -991,6 +991,7 @@ struct dwc2_hregs_backup { * @ctrl_buff: Buffer for EP0 control requests. * @ctrl_req: Request for EP0 control packets. * @ep0_state: EP0 control transfers state + * @delayed_status: true when gadget driver asks for delayed status * @test_mode: USB test mode requested by the host * @remote_wakeup_allowed: True if device is allowed to wake-up host by * remote-wakeup signalling @@ -1172,6 +1173,7 @@ struct dwc2_hsotg { void *ep0_buff; void *ctrl_buff; enum dwc2_ep0_state ep0_state; + unsigned delayed_status : 1; u8 test_mode; dma_addr_t setup_desc_dma[2]; diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index 6812a8a3a98b..8bc44071bb9b 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -27,6 +27,8 @@ #include #include #include +#include + #include "core.h" #include "hw.h" @@ -1446,6 +1448,11 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, return 0; } + /* Change EP direction if status phase request is after data out */ + if (!hs_ep->index && !req->length && !hs_ep->dir_in && + hs->ep0_state == DWC2_EP0_DATA_OUT) + hs_ep->dir_in = 1; + if (first) { if (!hs_ep->isochronous) { dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); @@ -1938,6 +1945,10 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); } + hsotg->delayed_status = false; + if (ret == USB_GADGET_DELAYED_STATUS) + hsotg->delayed_status = true; + /* * the request is either unhandlable, or is not formatted correctly * so respond with a STALL for the status stage to indicate failure. @@ -2387,8 +2398,8 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) if (!using_desc_dma(hsotg) && epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { /* Move to STATUS IN */ - dwc2_hsotg_ep0_zlp(hsotg, true); - return; + if (!hsotg->delayed_status) + dwc2_hsotg_ep0_zlp(hsotg, true); } /* @@ -3053,8 +3064,20 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, /* Safety check EP0 state when STSPHSERCVD asserted */ if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { /* Move to STATUS IN for DDMA */ - if (using_desc_dma(hsotg)) - dwc2_hsotg_ep0_zlp(hsotg, true); + if (using_desc_dma(hsotg)) { + if (!hsotg->delayed_status) + dwc2_hsotg_ep0_zlp(hsotg, true); + else + /* In case of 3 stage Control Write with delayed + * status, when Status IN transfer started + * before STSPHSERCVD asserted, NAKSTS bit not + * cleared by CNAK in dwc2_hsotg_start_req() + * function. Clear now NAKSTS to allow complete + * transfer. + */ + dwc2_set_bit(hsotg, DIEPCTL(0), + DXEPCTL_CNAK); + } } }