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[34.38.134.32]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bdafsm15356836f8f.30.2024.10.30.06.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 06:26:51 -0700 (PDT) From: Tudor Ambarus To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com Cc: krzk@kernel.org, linux-scsi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 1/2] scsi: ufs: exynos: remove unused tx_linereset_n/tx_dif_n_nsec fields Date: Wed, 30 Oct 2024 13:26:48 +0000 Message-ID: <20241030132649.3575865-1-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.47.0.199.ga7371fff76-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241030_062654_521112_479D3F61 X-CRM114-Status: GOOD ( 12.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org tx_dif_n_nsec was used to compute tx_linereset_n, but the later is not used afterwards. Remove both. Signed-off-by: Tudor Ambarus --- drivers/ufs/host/ufs-exynos.c | 5 ----- drivers/ufs/host/ufs-exynos.h | 2 -- 2 files changed, 7 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 9ec318ef52bf..91c09309c1c1 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -548,8 +548,6 @@ static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) t_cfg->tx_linereset_p = exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); - t_cfg->tx_linereset_n = - exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); t_cfg->tx_high_z_cnt = exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); t_cfg->tx_base_n_val = @@ -1970,7 +1968,6 @@ static void exynos_ufs_remove(struct platform_device *pdev) static struct exynos_ufs_uic_attr exynos7_uic_attr = { .tx_trailingclks = 0x10, .tx_dif_p_nsec = 3000000, /* unit: ns */ - .tx_dif_n_nsec = 1000000, /* unit: ns */ .tx_high_z_cnt_nsec = 20000, /* unit: ns */ .tx_base_unit_nsec = 100000, /* unit: ns */ .tx_gran_unit_nsec = 4000, /* unit: ns */ @@ -2046,7 +2043,6 @@ static const struct exynos_ufs_drv_data exynos_ufs_drvs = { static struct exynos_ufs_uic_attr gs101_uic_attr = { .tx_trailingclks = 0xff, .tx_dif_p_nsec = 3000000, /* unit: ns */ - .tx_dif_n_nsec = 1000000, /* unit: ns */ .tx_high_z_cnt_nsec = 20000, /* unit: ns */ .tx_base_unit_nsec = 100000, /* unit: ns */ .tx_gran_unit_nsec = 4000, /* unit: ns */ @@ -2074,7 +2070,6 @@ static struct exynos_ufs_uic_attr gs101_uic_attr = { static struct exynos_ufs_uic_attr fsd_uic_attr = { .tx_trailingclks = 0x10, .tx_dif_p_nsec = 3000000, /* unit: ns */ - .tx_dif_n_nsec = 1000000, /* unit: ns */ .tx_high_z_cnt_nsec = 20000, /* unit: ns */ .tx_base_unit_nsec = 100000, /* unit: ns */ .tx_gran_unit_nsec = 4000, /* unit: ns */ diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index 1646c4a9bb08..e64fe20d50c1 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -136,7 +136,6 @@ struct exynos_ufs_uic_attr { /* TX Attributes */ unsigned int tx_trailingclks; unsigned int tx_dif_p_nsec; - unsigned int tx_dif_n_nsec; unsigned int tx_high_z_cnt_nsec; unsigned int tx_base_unit_nsec; unsigned int tx_gran_unit_nsec; @@ -195,7 +194,6 @@ struct exynos_ufs_drv_data { struct ufs_phy_time_cfg { u32 tx_linereset_p; - u32 tx_linereset_n; u32 tx_high_z_cnt; u32 tx_base_n_val; u32 tx_gran_n_val; From patchwork Wed Oct 30 13:26:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13856528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0A97D5CCAF for ; Wed, 30 Oct 2024 13:38:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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[34.38.134.32]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bdafsm15356836f8f.30.2024.10.30.06.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 06:26:52 -0700 (PDT) From: Tudor Ambarus To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com Cc: krzk@kernel.org, linux-scsi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH 2/2] scsi: ufs: exynos: remove unused rx_hibern8_wait(_nsec) fields Date: Wed, 30 Oct 2024 13:26:49 +0000 Message-ID: <20241030132649.3575865-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.47.0.199.ga7371fff76-goog In-Reply-To: <20241030132649.3575865-1-tudor.ambarus@linaro.org> References: <20241030132649.3575865-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241030_062654_709596_F3D2AF07 X-CRM114-Status: GOOD ( 11.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org rx_hibern8_wait_nsec was used to compute rx_hibern8_wait, but the later is not used afterwards. Remove both. Signed-off-by: Tudor Ambarus --- drivers/ufs/host/ufs-exynos.c | 5 ----- drivers/ufs/host/ufs-exynos.h | 2 -- 2 files changed, 7 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 91c09309c1c1..fd86252ab2ba 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -559,8 +559,6 @@ static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) t_cfg->rx_linereset = exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); - t_cfg->rx_hibern8_wait = - exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); t_cfg->rx_base_n_val = exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); t_cfg->rx_gran_n_val = @@ -1975,7 +1973,6 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = { .tx_min_activatetime = 0xa, .rx_filler_enable = 0x2, .rx_dif_p_nsec = 1000000, /* unit: ns */ - .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ .rx_base_unit_nsec = 100000, /* unit: ns */ .rx_gran_unit_nsec = 4000, /* unit: ns */ .rx_sleep_cnt = 1280, /* unit: ns */ @@ -2050,7 +2047,6 @@ static struct exynos_ufs_uic_attr gs101_uic_attr = { .tx_min_activatetime = 0xa, .rx_filler_enable = 0x2, .rx_dif_p_nsec = 1000000, /* unit: ns */ - .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ .rx_base_unit_nsec = 100000, /* unit: ns */ .rx_gran_unit_nsec = 4000, /* unit: ns */ .rx_sleep_cnt = 1280, /* unit: ns */ @@ -2077,7 +2073,6 @@ static struct exynos_ufs_uic_attr fsd_uic_attr = { .tx_min_activatetime = 0xa, .rx_filler_enable = 0x2, .rx_dif_p_nsec = 1000000, /* unit: ns */ - .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ .rx_base_unit_nsec = 100000, /* unit: ns */ .rx_gran_unit_nsec = 4000, /* unit: ns */ .rx_sleep_cnt = 1280, /* unit: ns */ diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index e64fe20d50c1..b7fe725c7f8e 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -144,7 +144,6 @@ struct exynos_ufs_uic_attr { /* RX Attributes */ unsigned int rx_filler_enable; unsigned int rx_dif_p_nsec; - unsigned int rx_hibern8_wait_nsec; unsigned int rx_base_unit_nsec; unsigned int rx_gran_unit_nsec; unsigned int rx_sleep_cnt; @@ -199,7 +198,6 @@ struct ufs_phy_time_cfg { u32 tx_gran_n_val; u32 tx_sleep_cnt; u32 rx_linereset; - u32 rx_hibern8_wait; u32 rx_base_n_val; u32 rx_gran_n_val; u32 rx_sleep_cnt;