From patchwork Wed Oct 30 14:34:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 13856638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D19C8D5CCB3 for ; Wed, 30 Oct 2024 14:34:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EA8910E7B5; Wed, 30 Oct 2024 14:34:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eV9pBPvB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id B94D110E7AA for ; Wed, 30 Oct 2024 14:34:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730298891; x=1761834891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aUDIjg2Cie8rcgrnDatWDP+h75UQv4JQLbeuKB8Xy4E=; b=eV9pBPvByft4WrUIQbBbeTk81ZSvcRdlp+fQLDsucQvF72IljkLB3HZT duMbLoPTqwik6w1Nl9ajfzHGLs9ofkBrMtG0i40UZJYbANgzvudHI8LY1 4+MZlom2ynKLWKuoEUzpg3bc5aHCRjbcUJQfR4M2RjCZQeKg6CQiY4ptx o+a+rQr+jNHfyAIuKSvjtyCyTZbhinv6/MJ6+Uw4bpGGAJRq8S2+CJU1y K+J51OnHCEGe2oqDQIKOy7VDxcBimwnVYFgLbAIUaNDzxjQO+gJoTLVZo qSNo4cm7YGwmGJ2S1DlT5m2qZ2MXTH7AIFO08Cf9/b/8Gwb2xM7FDW5cv g==; X-CSE-ConnectionGUID: la9zlKbxRV6ikpCqGqL5Cg== X-CSE-MsgGUID: vbpQ51/3TEaJX65lr4fkGA== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="55407438" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="55407438" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 07:34:51 -0700 X-CSE-ConnectionGUID: 13rc3P5XRua1USku6kNHog== X-CSE-MsgGUID: j/QARihfRYyWJBF9EAXcjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="113180431" Received: from jraag-nuc8i7beh.iind.intel.com ([10.145.169.79]) by fmviesa001.fm.intel.com with ESMTP; 30 Oct 2024 07:34:48 -0700 From: Raag Jadav To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, matthew.d.roper@intel.com, andi.shyti@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com, badal.nilawar@intel.com, riana.tauro@intel.com, Raag Jadav Subject: [PATCH v3 1/4] drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges Date: Wed, 30 Oct 2024 20:04:15 +0530 Message-Id: <20241030143418.410406-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241030143418.410406-1-raag.jadav@intel.com> References: <20241030143418.410406-1-raag.jadav@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Refactor DG2 PCI IDs into D, E and M ranges which will be useful for segment specific features. v3: Rework subplatform naming (Jani) Signed-off-by: Raag Jadav --- include/drm/intel/pciids.h | 55 +++++++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 13 deletions(-) diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h index 7632507af166..83aac9f17372 100644 --- a/include/drm/intel/pciids.h +++ b/include/drm/intel/pciids.h @@ -717,37 +717,66 @@ MACRO__(0xA7AB, ## __VA_ARGS__) /* DG2 */ -#define INTEL_DG2_G10_IDS(MACRO__, ...) \ - MACRO__(0x5690, ## __VA_ARGS__), \ - MACRO__(0x5691, ## __VA_ARGS__), \ - MACRO__(0x5692, ## __VA_ARGS__), \ +#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \ MACRO__(0x56A0, ## __VA_ARGS__), \ MACRO__(0x56A1, ## __VA_ARGS__), \ - MACRO__(0x56A2, ## __VA_ARGS__), \ + MACRO__(0x56A2, ## __VA_ARGS__) + +#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \ MACRO__(0x56BE, ## __VA_ARGS__), \ MACRO__(0x56BF, ## __VA_ARGS__) -#define INTEL_DG2_G11_IDS(MACRO__, ...) \ - MACRO__(0x5693, ## __VA_ARGS__), \ - MACRO__(0x5694, ## __VA_ARGS__), \ - MACRO__(0x5695, ## __VA_ARGS__), \ +#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \ + MACRO__(0x5690, ## __VA_ARGS__), \ + MACRO__(0x5691, ## __VA_ARGS__), \ + MACRO__(0x5692, ## __VA_ARGS__) + +#define INTEL_DG2_G10_IDS(MACRO__, ...) \ + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \ MACRO__(0x56A5, ## __VA_ARGS__), \ MACRO__(0x56A6, ## __VA_ARGS__), \ MACRO__(0x56B0, ## __VA_ARGS__), \ - MACRO__(0x56B1, ## __VA_ARGS__), \ + MACRO__(0x56B1, ## __VA_ARGS__) + +#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \ MACRO__(0x56BA, ## __VA_ARGS__), \ MACRO__(0x56BB, ## __VA_ARGS__), \ MACRO__(0x56BC, ## __VA_ARGS__), \ MACRO__(0x56BD, ## __VA_ARGS__) -#define INTEL_DG2_G12_IDS(MACRO__, ...) \ - MACRO__(0x5696, ## __VA_ARGS__), \ - MACRO__(0x5697, ## __VA_ARGS__), \ +#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \ + MACRO__(0x5693, ## __VA_ARGS__), \ + MACRO__(0x5694, ## __VA_ARGS__), \ + MACRO__(0x5695, ## __VA_ARGS__) + +#define INTEL_DG2_G11_IDS(MACRO__, ...) \ + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \ MACRO__(0x56A3, ## __VA_ARGS__), \ MACRO__(0x56A4, ## __VA_ARGS__), \ MACRO__(0x56B2, ## __VA_ARGS__), \ MACRO__(0x56B3, ## __VA_ARGS__) +#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \ + MACRO__(0x5696, ## __VA_ARGS__), \ + MACRO__(0x5697, ## __VA_ARGS__) + +#define INTEL_DG2_G12_IDS(MACRO__, ...) \ + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_DG2_D_IDS(MACRO__, ...) \ + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__) + #define INTEL_DG2_IDS(MACRO__, ...) \ INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \ INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \ From patchwork Wed Oct 30 14:34:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 13856639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00A73D5CCB3 for ; Wed, 30 Oct 2024 14:34:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A25210E7A8; Wed, 30 Oct 2024 14:34:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U34aQuzd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A43510E7AA for ; Wed, 30 Oct 2024 14:34:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730298895; x=1761834895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GDAWlgzbvUn3Av1f1W3Skz88LIW5CsL7hFzJXWx7jNU=; b=U34aQuzdKPRhlAOpM2k+M7Xt7SvMmviHlherMhud4W3/7stB0JAqkTLm /r19FaLFBFwGRvlViv5Yfu32hGr6NkIfgQO6gkDMEo8mwf4bcYqBr4VNs QDYh99jh2okFz1E3MnDZUaC9qqqBPeDVOF0aDJYJ6V98P63vonygIX/IR meLfoe8tRNG5qBsXKOkrcxOtizeZTt2UF7UHh/nVAEN4re41tBmEkaBu2 vBk9mNnJBLmD/aEnMqKTN7zlDhvDm0yp/qc5R2vN606aeB33gFlj3Gwt7 7X0Y813drTD32WLLtCf6O7cg9ckvHZLFe70Edq95Cr2EvoM+0eg+dBctl A==; X-CSE-ConnectionGUID: o7svraEDRNip44Y/mB/yNg== X-CSE-MsgGUID: MSGg4bhbQTSGKC030xM4mQ== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="55407444" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="55407444" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 07:34:55 -0700 X-CSE-ConnectionGUID: 0pGeQUG2Q3SBTBmtm1cJJQ== X-CSE-MsgGUID: w2FjH1PbR2CdY6SnWnmq4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="113180452" Received: from jraag-nuc8i7beh.iind.intel.com ([10.145.169.79]) by fmviesa001.fm.intel.com with ESMTP; 30 Oct 2024 07:34:52 -0700 From: Raag Jadav To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, matthew.d.roper@intel.com, andi.shyti@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com, badal.nilawar@intel.com, riana.tauro@intel.com, Raag Jadav Subject: [PATCH v3 2/4] drm/i915/dg2: Introduce DG2_D subplatform Date: Wed, 30 Oct 2024 20:04:16 +0530 Message-Id: <20241030143418.410406-3-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241030143418.410406-1-raag.jadav@intel.com> References: <20241030143418.410406-1-raag.jadav@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduce DG2_D subplatform for the devices that span across multiple DG2 subplatforms but are within same segment and will be useful for segment specific features. v3: Rework subplatform naming (Jani) Split subplatform check into separate case (Jani) Signed-off-by: Raag Jadav --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_device_info.c | 9 +++++++++ drivers/gpu/drm/i915/intel_device_info.h | 5 ++++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f19cbd36829..fdb7158c7c1a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -546,6 +546,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define IS_DG2_G12(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) +#define IS_DG2_D(i915) \ + IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D) #define IS_RAPTORLAKE_S(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) #define IS_ALDERLAKE_P_N(i915) \ diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index ff9500194d15..89d1549a83ae 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -200,6 +200,10 @@ static const u16 subplatform_g12_ids[] = { INTEL_DG2_G12_IDS(ID), }; +static const u16 subplatform_dg2_d_ids[] = { + INTEL_DG2_D_IDS(ID), +}; + static const u16 subplatform_arl_ids[] = { INTEL_ARL_IDS(ID), }; @@ -266,6 +270,11 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915) mask = BIT(INTEL_SUBPLATFORM_ARL); } + /* DG2_D ids span across multiple DG2 subplatforms */ + if (find_devid(devid, subplatform_dg2_d_ids, + ARRAY_SIZE(subplatform_dg2_d_ids))) + mask |= BIT(INTEL_SUBPLATFORM_D); + GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); RUNTIME_INFO(i915)->platform_mask[pi] |= mask; diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 4f4aa4ff9963..7f1f84b1d0e3 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -95,9 +95,11 @@ enum intel_platform { /* * Subplatform bits share the same namespace per parent platform. In other words * it is fine for the same bit to be used on multiple parent platforms. + * Devices can belong to multiple subplatforms if needed, so it's possible to set + * multiple bits for same device. */ -#define INTEL_SUBPLATFORM_BITS (3) +#define INTEL_SUBPLATFORM_BITS (4) #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) /* HSW/BDW/SKL/KBL/CFL */ @@ -114,6 +116,7 @@ enum intel_platform { #define INTEL_SUBPLATFORM_G10 0 #define INTEL_SUBPLATFORM_G11 1 #define INTEL_SUBPLATFORM_G12 2 +#define INTEL_SUBPLATFORM_D 3 /* ADL */ #define INTEL_SUBPLATFORM_RPL 0 From patchwork Wed Oct 30 14:34:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 13856640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A353ED5CCB3 for ; Wed, 30 Oct 2024 14:35:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 231FE10E7B2; Wed, 30 Oct 2024 14:35:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="R82fWjPk"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id A516810E7AD for ; Wed, 30 Oct 2024 14:34:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730298898; x=1761834898; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DQx0VWVm2AKE4wEWs7QCvnTds132OqRVKzptLoozOS4=; b=R82fWjPkyn44STdsxu2uoDW/iAzS/1aE1giXSLWAmJhkezNXAMHFmxeF 42ghIj5a+0dItl+k97IrwKzH1BLwap8jrBTRYYeMhpwPzT7ZYeQrAJrfC l3FLy0IHVgqmh5KMH6hKPs10PG+y8U61l3GDchKA7Acf+HiIBB62kF5qA u+ROS1EIfuFek/DZ9YNL+uewp7ov7sBPRSH78VtlSa5pDRkzt9/nKlwb7 M81x2ttoDrK8ZEOrNZrFy5MWpx6Jomln8xs2oT4tBqWye4b95GdWeOf2z 3RJ/H/j9Si22EPTWj4bVCC7gFokQ9I/TCPKRsweRtshAdYX3g+ATK4pif g==; X-CSE-ConnectionGUID: QhtZQEj5R8ar/F8Kd0IMDg== X-CSE-MsgGUID: niI76AtsRCOZK1ByX6BoRw== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="55407447" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="55407447" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 07:34:58 -0700 X-CSE-ConnectionGUID: EPT5CNf5T9O3l9GVOv+qjQ== X-CSE-MsgGUID: ohT5XYZ5SimnRQh/MGBG2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="113180492" Received: from jraag-nuc8i7beh.iind.intel.com ([10.145.169.79]) by fmviesa001.fm.intel.com with ESMTP; 30 Oct 2024 07:34:55 -0700 From: Raag Jadav To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, matthew.d.roper@intel.com, andi.shyti@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com, badal.nilawar@intel.com, riana.tauro@intel.com, Raag Jadav Subject: [PATCH v3 3/4] drm/i915: Introduce intel_cpu_info.c for CPU IDs Date: Wed, 30 Oct 2024 20:04:17 +0530 Message-Id: <20241030143418.410406-4-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241030143418.410406-1-raag.jadav@intel.com> References: <20241030143418.410406-1-raag.jadav@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Having similar naming convention in intel-family.h and intel_device_info.h results in redefinition of a few platforms. Define CPU IDs in its own file to avoid this. v3: Move file out of gt directory, add kernel doc (Riana) Rephrase file description (Jani) Signed-off-by: Raag Jadav --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/intel_cpu_info.c | 42 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_cpu_info.h | 13 +++++++++ 3 files changed, 56 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_cpu_info.c create mode 100644 drivers/gpu/drm/i915/intel_cpu_info.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 31710d98cad5..208929358b25 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -35,6 +35,7 @@ i915-y += \ i915_sysfs.o \ i915_utils.o \ intel_clock_gating.o \ + intel_cpu_info.o \ intel_device_info.o \ intel_memory_region.o \ intel_pcode.o \ diff --git a/drivers/gpu/drm/i915/intel_cpu_info.c b/drivers/gpu/drm/i915/intel_cpu_info.c new file mode 100644 index 000000000000..9a1bfff4be7d --- /dev/null +++ b/drivers/gpu/drm/i915/intel_cpu_info.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + * + * Avoid INTEL_ name collisions between asm/intel-family.h and + * intel_device_info.h by having a separate file. + */ + +#include "intel_cpu_info.h" + +#ifdef CONFIG_X86 +#include +#include + +static const struct x86_cpu_id g8_cpu_ids[] = { + X86_MATCH_VFM(INTEL_ALDERLAKE, NULL), + X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL), + X86_MATCH_VFM(INTEL_COMETLAKE, NULL), + X86_MATCH_VFM(INTEL_KABYLAKE, NULL), + X86_MATCH_VFM(INTEL_KABYLAKE_L, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL), + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, NULL), + X86_MATCH_VFM(INTEL_ROCKETLAKE, NULL), + {} +}; + +/** + * intel_match_g8_cpu - match current CPU against g8_cpu_ids[] + * + * This matches current CPU against g8_cpu_ids[], which are applicable + * for G8 workaround. + * + * Returns: %true if matches, %false otherwise. + */ +bool intel_match_g8_cpu(void) +{ + return x86_match_cpu(g8_cpu_ids); +} +#else +bool intel_match_g8_cpu(void) { return false; } +#endif diff --git a/drivers/gpu/drm/i915/intel_cpu_info.h b/drivers/gpu/drm/i915/intel_cpu_info.h new file mode 100644 index 000000000000..dd0c5e784b97 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_cpu_info.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef _INTEL_CPU_INFO_H_ +#define _INTEL_CPU_INFO_H_ + +#include + +bool intel_match_g8_cpu(void); + +#endif From patchwork Wed Oct 30 14:34:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 13856641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F4E4D5CCB3 for ; Wed, 30 Oct 2024 14:35:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A833A10E7A9; Wed, 30 Oct 2024 14:35:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BEZEtgEZ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1D44910E7A9 for ; Wed, 30 Oct 2024 14:35:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730298902; x=1761834902; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6mdfcWPqytIQSl1UvX0X7hYdfY6N1+RM2OSHPnZvS20=; b=BEZEtgEZ9HMfoXrJ8DJvJ7+RzIaGVDAwyw2C2ENwH+oXyNQPZ4oZt5mY vHKIwwWfoF8TlFiQZhuu31FKIZ7X6XSrWxpl2OTM+jHeJhL97XWSVPztt 6r5Y0CiCcQKn98Bv5GCwZtDDwBLH1oETYrPygOA6CEqgpHTFy8ngzHUSI 2s+kmYaboCsUEQmD2v1AXijUQ5GkXcRumf5Vd/UN09otzEU40J5YurrRP C3uHKdbkfjyvH3/GHJ1D3lZR+WzKfG4FfI4g9tM93/EQ27JzZcbkffv3W 3u2hSyGTdY4cl3gI1PNaxVqqMob+RcQsjaZut1FIVkpocN235cA3jU0zF Q==; X-CSE-ConnectionGUID: VN5QHMtTSYa8SSn4Xu0yMQ== X-CSE-MsgGUID: lFOTQJZgSuCeLek+mi8uJQ== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="55407452" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="55407452" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 07:35:02 -0700 X-CSE-ConnectionGUID: JAikp6d/SCeZvmMT7LokiA== X-CSE-MsgGUID: sI5Ll0otRPe38rW9RoMFQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="113180529" Received: from jraag-nuc8i7beh.iind.intel.com ([10.145.169.79]) by fmviesa001.fm.intel.com with ESMTP; 30 Oct 2024 07:34:59 -0700 From: Raag Jadav To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, matthew.d.roper@intel.com, andi.shyti@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, anshuman.gupta@intel.com, badal.nilawar@intel.com, riana.tauro@intel.com, Raag Jadav Subject: [PATCH v3 4/4] drm/i915/dg2: Implement Wa_14022698537 Date: Wed, 30 Oct 2024 20:04:18 +0530 Message-Id: <20241030143418.410406-5-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241030143418.410406-1-raag.jadav@intel.com> References: <20241030143418.410406-1-raag.jadav@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" G8 power state entry is disabled due to a limitation on DG2, so we enable it from driver with Wa_14022698537. For now we enable it for all DG2 devices with the exception of a few, for which, we enable only when paired with whitelisted CPU models. This works with Native ASMP and reduces idle power consumption. $ echo powersave > /sys/module/pcie_aspm/parameters/policy $ lspci -s 0000:03:00.0 -vvv LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk- v2: Fix Wa_ID and include it in subject (Badal) Rephrase commit message (Jani) v3: Move workaround to i915_pcode_init() (Badal, Anshuman) Re-order macro (Riana) Signed-off-by: Raag Jadav --- drivers/gpu/drm/i915/i915_driver.c | 15 +++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 365329ff8a07..59c6124c9bc2 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -93,12 +93,14 @@ #include "i915_memcpy.h" #include "i915_perf.h" #include "i915_query.h" +#include "i915_reg.h" #include "i915_suspend.h" #include "i915_switcheroo.h" #include "i915_sysfs.h" #include "i915_utils.h" #include "i915_vgpu.h" #include "intel_clock_gating.h" +#include "intel_cpu_info.h" #include "intel_gvt.h" #include "intel_memory_region.h" #include "intel_pci_config.h" @@ -415,6 +417,18 @@ static int i915_set_dma_info(struct drm_i915_private *i915) return ret; } +/* Wa_14022698537:dg2 */ +static void i915_enable_g8(struct drm_i915_private *i915) +{ + if (IS_DG2(i915)) { + if (IS_DG2_D(i915) && !intel_match_g8_cpu()) + return; + + snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, + POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0); + } +} + static int i915_pcode_init(struct drm_i915_private *i915) { struct intel_gt *gt; @@ -428,6 +442,7 @@ static int i915_pcode_init(struct drm_i915_private *i915) } } + i915_enable_g8(i915); return 0; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 89e4381f8baa..d400c77423a5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3617,6 +3617,7 @@ #define POWER_SETUP_I1_WATTS REG_BIT(31) #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) +#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */ /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */