From patchwork Fri Nov 1 09:57:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859052 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 838DB15A85A for ; Fri, 1 Nov 2024 09:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455062; cv=none; b=MMsgY6iiVwiHCMgx770YA/RDv6InjDy9L3ZlpkmzhCqcdHtTP8A+nMCDOUT7cuK7PsKiQU3b8NNTOMID0bg38hBbiwKLWog6Hq6Bikli6Av8DOI1jD/uT4cUKPa+uuLIgoipv1ftO4VcbI4BzTvu2rTCZ+BaDplvvpIkMv1XPgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455062; c=relaxed/simple; bh=0m638leyhUhtaUAaN9ZlkjBSdE7urTd8c85y7al5QAc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nu7nNNFKR1XYrbIvv79+9bcP/UxiD8IAopG6b35oR2uVE+VmCm8REefEpQ2TzYEnb8YdU/zGTY/BQjUBeuj+0naHh8ovbVeTHBCYeHpQ+JqCCqhvMr3nFF8jKvFDvhJgA0gguUS16qckuOf5m5zMU8qJ5yldS2s2/S3sgFAtFaY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=KrzDpIGZ; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="KrzDpIGZ" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-5cb74434bc5so2143210a12.0 for ; Fri, 01 Nov 2024 02:57:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455058; x=1731059858; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gfm06b4hKMdHLkWB/4M6o/0esEDQBJdzAKRNLmWwPQA=; b=KrzDpIGZiNf4O1/dgZanHHSM9VXmUYkDiJy7JnafAMbD5ThirU+KdAIRzuTBfPtLUe mI3BLQPQuew8NmANe9MTRRuy/EHzwu1uWY6NPEnfNMOklGuM23hxcvy/sebdjVBOYQSL +fdQX9Is/B2uWZhUl9czRZRIEG2OrrXsD8rL4FhMYDo7MA9sYMN+nlLo9T0a9ekHNtz+ pL7RUNWda+MjmkRnNnOIWkOdqbmA/sq6AFIF8Khf6KcGokyC9mn3ksvxPP8rMRZ4qc6L RJoOjjOf/cZE5aPzVsykXZPq/dktirMhdbukw292vl0FlDYjHvBunnOR6uBhWqnfThfF TbtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455058; x=1731059858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gfm06b4hKMdHLkWB/4M6o/0esEDQBJdzAKRNLmWwPQA=; b=rSbvFkRwsej1bHcbYjs2a0I1C0XidxUrXymYG3DCRgiCdQZh2VQxXmO/4HYgkzX7YQ cgev27hMzjz/p2jqITdK4hNDyhMdvx8Iet35NkKihYWqjn62ZWH2V6K+4wK3m5vsvQM4 P+ujdcb0eMTdXmODaIT8qW+93FpFCIDmky9mPr3lyuJrNk6VGcyPMYg6xiHeHU81cdRT zTtGXhm+btO9BA0LW/zgOWD/g0DDl7uEKpu3itn84Cqa9JxX5JCPx1LpMhCRrGZHjVkJ J/3Xd5U0I1kKW2F9rruMvhDP1/QRbk03EvqZHtSZOAJ8ytY5UXZX45bOi80tyKgs6kXC Nofw== X-Forwarded-Encrypted: i=1; AJvYcCUBY3ParopnkaOBPaNQk06jpIRi5AKz77jVf24ZmtbrObHiiSlUUqb7qOcv/B7sx7BRzRv1jGd0e9k=@vger.kernel.org X-Gm-Message-State: AOJu0YxKKmcyKk7w8N5fSMdefeXG0l+suP3XzqhyIzwml/4T1qHxnIby WaaQjujK6Z+FtVXVIz6U/a5UebfhaErW+/plLcIDlWz2SZ66ArV04qWw6+rCink= X-Google-Smtp-Source: AGHT+IEb89p86xoYXu3JKTNPryZg3y3CDRh6iFfjnC4NPmIs9ROG2Yx148IwXpRj1QPZZK99u/gJwg== X-Received: by 2002:a05:6402:1d4e:b0:5cb:7443:27d4 with SMTP id 4fb4d7f45d1cf-5ceb9343488mr2308264a12.25.1730455057897; Fri, 01 Nov 2024 02:57:37 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:37 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea , Krzysztof Kozlowski Subject: [PATCH v6 1/9] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Date: Fri, 1 Nov 2024 11:57:12 +0200 Message-Id: <20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - used spaces in the diagram from the patch description - added "This is board specific" in the board description to emphasize the usage of the assigned-clocks in the example - added default for quartz-load-femtofarads - collected tags Changes in v4: - squashed with patch "Add clock IDs for the VBATTB controller" from v3 - removed "oscillator" word from commit description - added assigned-clocks, assigned-clock-parents to the documentation example - used clock-controller for the node name - used "quartz-load-femtofarads" property for the load capacitance - renamed include/dt-bindings/clock/r9a08g045-vbattb.h to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h Changes in v3: - moved the file to clock dt bindings directory as it is the only functionality supported at the moment; the other functionalities (tamper detector, SRAM) are offered though register spreaded though the address space of the VBATTB IP and not actually individual devices; the other functionalities are not planned to be supported soon and if they will be I think they fit better on auxiliary bus than MFD - dropped interrupt names as requested in the review process - dropped the inner node for clock controller - added #clock-cells - added rtx clock - updated description for renesas,vbattb-load-nanofarads - included dt-bindings/interrupt-controller/irq.h in examples section Changes in v2: - changed file name and compatible - updated title, description sections - added clock controller part documentation and drop dedicated file for it included in v1 - used items to describe interrupts, interrupt-names, clocks, clock-names, resets - dropped node labels and status - updated clock-names for clock controller to cope with the new logic on detecting the necessity to setup bypass .../clock/renesas,r9a08g045-vbattb.yaml | 84 +++++++++++++++++++ .../clock/renesas,r9a08g045-vbattb.h | 13 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a08g045-vbattb.h diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads = <12500>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h new file mode 100644 index 000000000000..67774eafad06 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ + +#define VBATTB_XC 0 +#define VBATTB_XBYP 1 +#define VBATTB_MUX 2 +#define VBATTB_VBATTCLK 3 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ From patchwork Fri Nov 1 09:57:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859053 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF1141607B7 for ; Fri, 1 Nov 2024 09:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455065; cv=none; b=O90Vb0zozY5KL/P23fndcUgarbEP10KG9iSSxpQzD2MTX9pS9WOysN9qWOl9YFNtGK/1P7qk/xekIyz3+ecyXfcu91ZNLV78e+yTveEfgpzepKAvVwWs1yh7+0TL+w7bzrim5o5lhI3/IzzyWU3DPpnjTA8Zhm4kooizN0/0ZCU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455065; c=relaxed/simple; bh=S+F2FkEdi2w5OLkb2FF8IDO/kgC5BfFXc48xK0PQxEU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sjqTBtDi8hNfyLFVNa9onyL3dq0psmg92bRsX5GQYBSzCU2y5oinriyPxwNOmOnF9ODvpPcY9jNLf7MgndRlmJogwbA4ZV+6McKKgRKETZK4VTt7OreHcy/wF1HZlf1/KYbAEErWSNOj02UwKk5VaiaVubWAuz1/4o9pkzSMknc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=YrXWyvte; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="YrXWyvte" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5c9150f9ed4so2448994a12.0 for ; Fri, 01 Nov 2024 02:57:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455061; x=1731059861; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ewtg0K16I6vEI9VCro/VP2IXg7P8FX0BQ2vY0LS22pU=; b=YrXWyvtemX2WGnv5ubtRDUhTK7QTIqTHAEEtO37tJi3TGtO5qMEHccZZIU4b1rRixV 5KMAy1JPN1GjnLBcAEam6x/+cNejTDUnRnO09cQ+9A+LmSzfFX5DYoYXnCHiS/t713ZU 4s1mfJxgD/VtMt6DC88DOmF3HLSRnG7uvnHW3goK7tqKhfhQkBY8kL34Obu4iMFgHgQm Md3YxmL6GNYahpg7tlG83y/vP3vKFIxeKrRZF2kQ62l0qJdk9+6xscRMU8+R9DsgxqfF kQvnKTrzUP9Qu45hBJzBL31OQXGynjYBW9aQXwmicpExEbWPb4WMuf0A5DeG6KC4N6P4 0wGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455061; x=1731059861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ewtg0K16I6vEI9VCro/VP2IXg7P8FX0BQ2vY0LS22pU=; b=UOxB8QEU0f4++zV7OYBEYbdEsObPBSHgRYX+YdEtM0XZvYqun4QHwlH0XWkkP7BRUs ANVoR82NP6HG2YKlBcqOGlR9fiAbvw/f/KlM13Am6469nySWkH3vL+j6MWurD5L7a9vo Xm79qAYV5STzZ8Plphz5tg4T9q9aJQDZRNk5jp0Y4V1PP8wtVYyC3C9rgeXICYobNK3k PZLtQWK6vHrcUIkWH9hKnQlQHh5jOLmnW5Uoc9VP0U8IpuDUsyy4FXHWQkAkiJBuTWbB vQ0PQCCRtoVqkBtEW9KKKZqbSJbEiFxdATklVdGm1gRR5gcstTaQSCwg4ji2ZyI1iZ8h E53g== X-Forwarded-Encrypted: i=1; AJvYcCXH6nUe6f52spnRZ9Bmnw/2AAkkL6JZio31fnHGU9kDZ2X0T7r5Plk6g2bYKY66vJCT0XHIt07TKCE=@vger.kernel.org X-Gm-Message-State: AOJu0Yzu3MvX847OJaG/NOC8uUudFeScAPFCCL5C/jA6DeCeyIgykN2r Hb1FuX1eX/gLSNaWeid79QsmW79r6tGlW56d7jqZ+25WC0ur77S1AttTUjPHyjE= X-Google-Smtp-Source: AGHT+IEFGiN/u4W5r9i6MtaqopU2l9fL1FFrDwTz4s8iqC4tcmgZL2qm6/VdNeHlxydCj5OuRaUwEA== X-Received: by 2002:a05:6402:350c:b0:5cb:69bb:ba8e with SMTP id 4fb4d7f45d1cf-5cbbfa78a8fmr13489266a12.34.1730455061093; Fri, 01 Nov 2024 02:57:41 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 2/9] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Date: Fri, 1 Nov 2024 11:57:13 +0200 Message-Id: <20241101095720.2247815-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add devm_clk_hw_register_gate_parent_hw() macro to allow registering devres managed gate clocks providing struct clk_hw object as parent. Reviewed-by: Geert Uytterhoeven Acked-by: Stephen Boyd Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - none Changes in v4: - collected tags Changes in v3: - none; this patch is new include/linux/clk-provider.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 75444e250a78..a49859ef3304 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -622,6 +622,24 @@ struct clk *clk_register_gate(struct device *dev, const char *name, __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ NULL, (flags), (reg), (bit_idx), \ (clk_gate_flags), (lock)) +/** + * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock + * framework + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_hw: pointer to parent clk + * @flags: framework-specific flags for this clock + * @reg: register address to control gating of this clock + * @bit_idx: which bit in the register controls gating of this clock + * @clk_gate_flags: gate-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, \ + reg, bit_idx, clk_gate_flags, \ + lock) \ + __devm_clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ + NULL, (flags), (reg), (bit_idx), \ + (clk_gate_flags), (lock)) /** * devm_clk_hw_register_gate_parent_data - register a gate clock with the * clock framework From patchwork Fri Nov 1 09:57:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859054 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB2DF1922CA for ; Fri, 1 Nov 2024 09:57:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455068; cv=none; b=mYnkCLnF+Fx23bGPejaK5RZCQWX1Gdwubic3Biej17sUUdbjw6iy7PI9FcM2P4PO8ocLl/UxlhslS0pxziKV3R143L8cquiIAS7M2ozTwhk+FqaVGGjsth+MlzYa5HDAUq5TQ+9TJSAEpGPoNqNoObHoc0LmK49+mTmy1JlcRwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455068; c=relaxed/simple; bh=5VS7huQJEKAhHcQEm7NCYAYokBuq27sIXf/SS0O/M04=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eUId1EapuGL+62xDloWAa+L7wpLh/Tx+2prYGU/bR7ygXvfAt1isb19QhDBa8eX05K2u6QJVOI0NgyHWCxIyN+KG15A9V0cu2N0Qa0Z/VuKXYH14cBx8Yb98zbBwJ49VoFbGvT4I0DjCvUIhE57eAKSp6AmQCPv/xGzEZ475fz4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=kJjlrQcz; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="kJjlrQcz" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-5c9404c0d50so1958248a12.3 for ; Fri, 01 Nov 2024 02:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455064; x=1731059864; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P3ThccVles5w9h5xpm4pKe/Bf3Vhlh9BHbKUv1nFK9g=; b=kJjlrQczAITkOJnoD3IalfJKzMgvhJrJUZwZ+VkwbQF8LnO2yzPMNMr39YKOemF3Pb kxRyNGiMWi/m6tGQQ2K1nqNDUU6DRrA/JHkTJNhENI3cA6RvsorPLgI2Sibp9WVWsIIY r/qAgUlZClXKCpvKkDikr8tqg0sFro0nPMb/QrCXKWE4pU8rANKS3ts1vnyTeHQ0x4ZI XI2eazukVTU25UEr56pzUgDXd6ebFFPUVjc/7euaXvhAm3tSWDRx5PN76g0dZbP2uurT xvR8219jNxgKh5lmXOPs9IFr6wzsCXOueybd1iPQETbKojv/lAZBf9kQASlJu2z7Sye3 xwQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455064; x=1731059864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P3ThccVles5w9h5xpm4pKe/Bf3Vhlh9BHbKUv1nFK9g=; b=Fr2AwBMd+JptazuvvDnL5jQeStpfjIA9sTBboEKhpq8ese0yhc0yarnOBUySwbKEpO TuR78jtsLjEaRM9SdjplsBnSahtK39GheizzRVI1Kzse6B9Xsw0shzmGBKDjLD3kUmd2 KfocZS2BepNExfNSbh1cA1uQniyE47oCOc63tE6UYEetEn5L6vhxNRxMylX9qzQEg1/f tJl9WwxAj6J0qn3FWvcoG/OkQ77nkjaSvcBCzZ9pW4REsJcAnFnfrJFcLwfb7arBmZrM glhr5Ko4oQRtMBn+uZI5J1aCz4CTPoqDyxc96GXi9s7Ex3ZWu8J890/z3ln6B4HzG0KE JQYQ== X-Forwarded-Encrypted: i=1; AJvYcCXyxTv+lilTww5FKcNqyc2O6T/rsrmkSFJ8sjDUZOkBOt4jyUi93ZCak1QjMS0cUtf8Nb/6N2V+WA0=@vger.kernel.org X-Gm-Message-State: AOJu0YylYn9eJtvr6Vz8UWMSkzRCWqzboVRmkU9xBlEPLDBopY4jS+AV Qfgegast9cPW6/y/eAkdfKbtxvHVi82pyGW/x1tVjIzlERHkNeSa9gFhJVFZpSw= X-Google-Smtp-Source: AGHT+IGUlhOCwH2fmBWL8ZNb53+BHcSpXdIr+V/UM4VkSvZJ7t8FyZkdKsmNGaJmF573TUlMHtoPSw== X-Received: by 2002:a05:6402:13c9:b0:5c9:6eea:8e06 with SMTP id 4fb4d7f45d1cf-5cbbf947c0cmr18513608a12.24.1730455064181; Fri, 01 Nov 2024 02:57:44 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 3/9] clk: renesas: clk-vbattb: Add VBATTB clock driver Date: Fri, 1 Nov 2024 11:57:14 +0200 Message-Id: <20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - used tristate - added depends ARCH_RENESAS || COMPILE_TEST Changes in v5: - collected tags Changes in v4: - dropped oscillator from patch description - s/on-board/internal in patch description - updated dt-binding included file name in the driver as it has been renamed to include/dt-bindings/clock/renesas,r9a08g045-vbattb.h - dropped the "_BIT" from driver macros - used "quartz-load-femtofarads" dt property instead of adding a new one - register the "vbattclk" as critical clock as this feeds the RTC counter logic and it needs to stay on from the moment the RTC is configured; along with it, added a comment to express this. Changes in v3: - updated patch description - dropped dependency on MFD_RENESAS_VBATTB as now there is no driver built under this flag - dropped include/clk.h - added pm_runtime and reset control support - updated register offsets - registered 4 clocks: xc, xbyp, mux, vbattclk using generic clock drivers - added MODULE_DEVICE_TABLE() Changes in v2: - updated patch description - added vendor name in Kconfig flag - used cleanup.h lock helpers - dropped the MFD code - updated registers offsets - added vbattb_clk_update_bits() and used it where possible - added vbattb_clk_need_bypass() to detect the bypass setup necessity - changed the compatible and driver names drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-vbattb.c | 205 +++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+) create mode 100644 drivers/clk/renesas/clk-vbattb.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 76791a1c50ac..ff01f5f0ed20 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -237,6 +237,11 @@ config CLK_RZV2H bool "RZ/V2H(P) family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_RENESAS_VBATTB + tristate "Renesas VBATTB clock controller" + depends on ARCH_RZG2L || COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 23d2e26051c8..82efaa835ac7 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_CLK_RZV2H) += rzv2h-cpg.o obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o +obj-$(CONFIG_CLK_RENESAS_VBATTB) += clk-vbattb.o diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c new file mode 100644 index 000000000000..ff9d1ead455c --- /dev/null +++ b/drivers/clk/renesas/clk-vbattb.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * VBATTB clock driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define VBATTB_BKSCCR 0x1c +#define VBATTB_BKSCCR_SOSEL 6 +#define VBATTB_SOSCCR2 0x24 +#define VBATTB_SOSCCR2_SOSTP2 0 +#define VBATTB_XOSCCR 0x30 +#define VBATTB_XOSCCR_OUTEN 16 +#define VBATTB_XOSCCR_XSEL GENMASK(1, 0) +#define VBATTB_XOSCCR_XSEL_4_PF 0x0 +#define VBATTB_XOSCCR_XSEL_7_PF 0x1 +#define VBATTB_XOSCCR_XSEL_9_PF 0x2 +#define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 + +/** + * struct vbattb_clk - VBATTB clock data structure + * @base: base address + * @lock: lock + */ +struct vbattb_clk { + void __iomem *base; + spinlock_t lock; +}; + +static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) +{ + switch (of_lc) { + case 4000: + *reg_lc = VBATTB_XOSCCR_XSEL_4_PF; + break; + case 7000: + *reg_lc = VBATTB_XOSCCR_XSEL_7_PF; + break; + case 9000: + *reg_lc = VBATTB_XOSCCR_XSEL_9_PF; + break; + case 12500: + *reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void vbattb_clk_action(void *data) +{ + struct device *dev = data; + struct reset_control *rstc = dev_get_drvdata(dev); + int ret; + + ret = reset_control_assert(rstc); + if (ret) + dev_err(dev, "Failed to de-assert reset!"); + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_err(dev, "Failed to runtime suspend!"); + + of_clk_del_provider(dev->of_node); +} + +static int vbattb_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_parent_data parent_data = {}; + struct clk_hw_onecell_data *clk_data; + const struct clk_hw *parent_hws[2]; + struct device *dev = &pdev->dev; + struct reset_control *rstc; + struct vbattb_clk *vbclk; + u32 of_lc, reg_lc; + struct clk_hw *hw; + /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */ + u8 num_clks = 4; + int ret; + + /* Default to 4pF as this is not needed if external clock device is connected. */ + of_lc = 4000; + of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); + + ret = vbattb_clk_validate_load_capacitance(®_lc, of_lc); + if (ret) + return ret; + + vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); + if (!vbclk) + return -ENOMEM; + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + clk_data->num = num_clks; + + vbclk->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vbclk->base)) + return PTR_ERR(vbclk->base); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + rstc = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret = reset_control_deassert(rstc); + if (ret) { + pm_runtime_put_sync(dev); + return ret; + } + + dev_set_drvdata(dev, rstc); + ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev); + if (ret) + return ret; + + spin_lock_init(&vbclk->lock); + + parent_data.fw_name = "rtx"; + hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, + vbclk->base + VBATTB_SOSCCR2, + VBATTB_SOSCCR2_SOSTP2, + CLK_GATE_SET_TO_DISABLE, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XC] = hw; + + hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_XBYP] = hw; + + parent_hws[0] = clk_data->hws[VBATTB_XC]; + parent_hws[1] = clk_data->hws[VBATTB_XBYP]; + hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, + vbclk->base + VBATTB_BKSCCR, + VBATTB_BKSCCR_SOSEL, + 1, 0, &vbclk->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_MUX] = hw; + + /* Set load capacitance before registering the VBATTCLK clock. */ + scoped_guard(spinlock, &vbclk->lock) { + u32 val = readl_relaxed(vbclk->base + VBATTB_XOSCCR); + + val &= ~VBATTB_XOSCCR_XSEL; + val |= reg_lc; + writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); + } + + /* This feeds the RTC counter clock and it needs to stay on. */ + hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL, + vbclk->base + VBATTB_XOSCCR, + VBATTB_XOSCCR_OUTEN, 0, + &vbclk->lock); + + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[VBATTB_VBATTCLK] = hw; + + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id vbattb_clk_match[] = { + { .compatible = "renesas,r9a08g045-vbattb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vbattb_clk_match); + +static struct platform_driver vbattb_clk_driver = { + .driver = { + .name = "renesas-vbattb-clk", + .of_match_table = vbattb_clk_match, + }, + .probe = vbattb_clk_probe, +}; +module_platform_driver(vbattb_clk_driver); + +MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); From patchwork Fri Nov 1 09:57:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859055 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24FBD198A0E for ; Fri, 1 Nov 2024 09:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455070; cv=none; b=TI9OGgIgCczuftuNJkh8Z8r+wpX65S4FTb+wyvn1IV4+8KKrcBrhv2J1YnErkT9yl4GqxtYe9NL1w2cOIfM3rHUFoxNk4yVLH8iS4G/N2NA0LUoF/iYQJIB6jF2Uehf1+P5QrIyJyg+EqjqrqdOm1zjSHPXBmmfqPQ4ucgEkMsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455070; c=relaxed/simple; bh=TpRf+IPzzflEYM2PIdEujWQYh9I90S6kiE0QI6bogDE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NKLaiPbym/FR+Tv1LXLuXhCEbJOzxq9uQnNL61zG0LAX3VH7g6XgDCwTGljV4VlM1/XBW22wJ5NNAD0JM68/3EdlHDTPyD+AYjPrONJNMn+OQY8zRjEBwpCb9QTG/WQp8fDylizN34AQ8vvyOj7HpAmTSdy76Mo0BRJ1VjKYIv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=aBdNrrCJ; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="aBdNrrCJ" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5ceb75f9631so1318083a12.0 for ; Fri, 01 Nov 2024 02:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455067; x=1731059867; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1RfCSiRKPCnvU8GbAS6ruNWu/VWU6I+MnOUaUXq52C0=; b=aBdNrrCJfTFIK+HV8864JZzIMfP4dUOPfNn6eRj6ZmMDsQ1Jo7BVt4uXgXHUNX4W35 QC+utTY/FaojQdD4/1tbcRv+XZa2wV6P0nwLHOu5TYgO4PqDxvY2yq62wFubq+04jKlN +8J0Adpaoj6fZ3xPV85aIzqkie+9UtwbehF/I0XXoRnLib3/EcI9OAHQk5VKhUFFwQ5Z oNXjvVjNLxUj7plvIpRivudAq9nL81XJOWGUng4zUIvTSJjKuIfAaQucHqrXvKI6Zo2G aK3xrMwrt4mGe6LKbIyx4fRTGRtUJWcryVqgc3cAx+hW8fCdwL7yxjfGnOmY5A1gWUEV 8Fpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455067; x=1731059867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1RfCSiRKPCnvU8GbAS6ruNWu/VWU6I+MnOUaUXq52C0=; b=Z4ynABswnTXxAoOajXd0JZTHjMG2GDyc01rbTDNlwZzDO1nbHACRirGYIzH0BTCcMM ZTbPa2pU8enT4Nz1PMaSE1rLMto3kobOOULAGNe+4cTJwT23rDsZUHSFh4rJqBdaWAXg FvB4XAuFMBZE+AnIcTpbOK6cCJqMoSWd2DBOJElEYKN01vxvAvVQqE/r9TKOkH5BkSCi kkpCT35qUw84dc0eQ0SRzz9nuXhoND+BhGSsTRF4BURqt/hfahpwS+548mG9pY8NO+7X +sBcw6zii2kS6Y3PpL/hDyVDn1E1lbR46onoVDT/Jm4zvd6qVvfSIGD3i00MqjkQ6qVb ncvA== X-Forwarded-Encrypted: i=1; AJvYcCUwU8cLoMYzAvKWybfErphpQFP2aULnO07OVNSo92S1kGmqNg1ni3vH3KOr26+U8PKY7plTGwkp+0g=@vger.kernel.org X-Gm-Message-State: AOJu0YwP3IS593Vyd/+2LPv0SFljEOaSvUq5LXU6fO3lsqM8LOfnyToI gdqrwAK9whgZnaC0cYAtH55ymQteh4ObW8fEkeBgrBQdDi/e7ZgFuGMdEzdaIXI= X-Google-Smtp-Source: AGHT+IESf07+Ty6d+mR8h6jLvICrJWZMLVl4M5/vp52FC/zlmrG1YxQrK8z4XTkLNQ78LoV1FRPc3A== X-Received: by 2002:a05:6402:518d:b0:5c9:5701:f79e with SMTP id 4fb4d7f45d1cf-5cbbf947bf6mr17732684a12.27.1730455066464; Fri, 01 Nov 2024 02:57:46 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 4/9] rtc: renesas-rtca3: Fix compilation error on RISC-V Date: Fri, 1 Nov 2024 11:57:15 +0200 Message-Id: <20241101095720.2247815-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Fix the following compilation errors when building the RTCA3 for RISCV: ../drivers/rtc/rtc-renesas-rtca3.c:270:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 270 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:369:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 369 | tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:476:11: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 476 | cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:523:9: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 523 | radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); | ^ ../drivers/rtc/rtc-renesas-rtca3.c:658:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 658 | val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); | ^ Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v6: - none; this patch is new drivers/rtc/rtc-renesas-rtca3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c index abb0f6f73906..d127933bfc8a 100644 --- a/drivers/rtc/rtc-renesas-rtca3.c +++ b/drivers/rtc/rtc-renesas-rtca3.c @@ -5,6 +5,7 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ #include +#include #include #include #include From patchwork Fri Nov 1 09:57:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859056 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E9A19924F for ; Fri, 1 Nov 2024 09:57:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455072; cv=none; b=g57GxRvX6ulPeTJBM7LZM8/qKTYUsF1DVBKfApITNEirZMzOHnZ6yXHIsIyfeV4GFXcaiHUxLYZG4U8ZQxQuNmMrxlZ8aanJ4nEQBoXFD93U+bpaqI9bfgJRU+DBrIQXoX22ECp8TKRCSYSzRgSUQetvLDpkEmyY1A1f6oXdMnY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455072; c=relaxed/simple; bh=9vzGrsVvgREwZzqZVmo/G/4tjM4k1gZZ+XTtE75S2Jc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pWZWj0UFX4RPpe07hIRJkhDjjG6yY1l6lK7Wa/kOLjyD1WdFkhrDBiqXl7iZOE8ueLl22Jhbc7xVGmLAlwr86YlovN2RJLPOdT0H1TLluBmth6gAT99ZjbZkCrQFCbL27wx38MICJBH+QxI2a5TiFCkUiT+phLw+NvELHAgkKjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=n+rGkGc6; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="n+rGkGc6" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-5cb6ca2a776so2542236a12.0 for ; Fri, 01 Nov 2024 02:57:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455069; x=1731059869; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dQzVdoqdvqgLOFlu8gMxMsd1xizkEdv4aj8iXiXRzjU=; b=n+rGkGc637y6e0GNhWQc/89NJe+yfbBpnf2g2WBStJP3iItMcm7ZYC2dqg4GHrBehf 4fLIOcQQLmLHObghcHFFHZ5wBAT6U0bYffyfqx0L/YQJ2ygjqXtfG6nw7tA991f+QgUg dHfGW+AZ5SGheECcKwn6xTJrle5AHkG7vJS+QTVKfkFyUeBlyjRu/iUfUNx8pA9PG8By Gv/bR8Ppv82n9aMAdkwj54usEURj6RJ+3bjGNCUnws53ZJtYUKmL7oq/qJ8sS1ntwD5M RZf0pZSZRc8gGe6O6zXpnNvL4URdliE6rYun77m0TeXg9nDu2e7K/QFT3avoJYBswubV Zr0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455069; x=1731059869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dQzVdoqdvqgLOFlu8gMxMsd1xizkEdv4aj8iXiXRzjU=; b=dGPVJXgofw42pzvmaBhX9FLF4nDy+11D2/MKP4H/VTYfYWh7ED8Zd32qIT5hacKPIv xUfQRiKzBGuL3SZcS5sUQqqsXXVcm0pvrrwto7CtFZok2VOUM5CCb5/9TnFSqnLLBMeT d7Yh1XXCkrOAFGFaY6yr5ADviQhQoveMK4uwVD+cm6ahkUllMkxrdyVtzAkgBRBmkMrA C8lt1Swmvm1jobaz+ywAz6cBbfxs74P9ST1fU9cfFhwfsv823h4JSFp4c10fU5efNq3I a4FdalctD/7iNS9gN78MtR/2rpA84ssbCfBkhSI7Ze1SzHNytrSvje0TYcmi7I9aHQdJ hqGA== X-Forwarded-Encrypted: i=1; AJvYcCXQDNEp7k0ysP4ct5fRgLgKAefErjqCIRw2goGJQmet1WiKfqUGQDSuekub8DUVjj70cVTOJpej4eI=@vger.kernel.org X-Gm-Message-State: AOJu0YwUGLFc5/TlfeRE5IVz7CMPyNT10ZAgs71+aiW13Ptvl7YkC62P 8ZnGPLeseOzCiAhchvSKOinXsAFEgTkRILDzFBRJJ73AFN+hdm7JBzbnINRMhx4= X-Google-Smtp-Source: AGHT+IGfg1jB9Gr5SknKQmj654bdZhqMhBEbjNXW8PNX7wmtbus6/mYgJoy7Q69k4vfLF7Q0z4tBwQ== X-Received: by 2002:a05:6402:4307:b0:5ce:af01:6317 with SMTP id 4fb4d7f45d1cf-5ceaf016b07mr3408111a12.15.1730455068835; Fri, 01 Nov 2024 02:57:48 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 5/9] arm64: dts: renesas: r9a08g045: Add VBATTB node Date: Fri, 1 Nov 2024 11:57:16 +0200 Message-Id: <20241101095720.2247815-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add the DT node for the VBATTB IP along with DT bindings for the clock it provides. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - dropped the status = "disabled"; for the vbattb-xtal node Changes in v4: - used clock-controller for the vbattb node name - move the node near scif0 for ordering - set the vbattb_xtal status as disabled to avoid having it exported in linux with frequency = 0 in boards that don't use it - collected tags Changes in v3: - dropped the child nodes of vbattb; along with this dropped ranges, interrupt-names, #address-cells, #size-cells - added vbattb_xtal as input clock for vbattb Changes in v2: - update compatibles - updated clocks and clock-names for clock-controller node - removed the power domain from the clock-controller as this is controlled by parent node in v2 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 067a26a66c24..a1d5084b074a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,18 @@ scif0: serial@1004b800 { status = "disabled"; }; + vbattb: clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0 0x1005c000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + i2c0: i2c@10090000 { compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; reg = <0 0x10090000 0 0x400>; @@ -425,4 +437,11 @@ timer { interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + + vbattb_xtal: vbattb-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From patchwork Fri Nov 1 09:57:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859057 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F4E819B5A7 for ; Fri, 1 Nov 2024 09:57:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455074; cv=none; b=jbDkfIjwlVSwGYdQZCgiUYaKl0b34FF3HImq+LU4NDjEykpv4caaNI0IQ1UXL9/IQPSqC4rb3yhbBnjlaT9N7pn92grc3Cs5Y7cB89zGzveSr4v4mo/Hjf3z9iutz9wYNd8qe70wSCskkBegZ2lUB2FSLCsEZrg75KT0N4WiKcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455074; c=relaxed/simple; bh=yYP16zEPx37dhW8+zaOISLjIJmbRtcBg1hLt5dlVY3E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ITjFX4c52TdXk/bu/hP8sfsycmcKSHTbqoL01Rlw6YZopv9/tyecAJs2zJGYgwwqHJOVDU6i6+D1phzsc8BHGTVKZib/vG0mwINem6KFZkvMUvoI0F3sEMClezY295AZH8WLp84veCjsWbGIphiKA2K1Uy4dzw0gQPh917E0F1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=IPfmRM/w; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="IPfmRM/w" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-5c948c41edeso2191919a12.1 for ; Fri, 01 Nov 2024 02:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455071; x=1731059871; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tfW7W38u73oXDY58ExSVjQCRIYrMmZQTfpbBo08M7pQ=; b=IPfmRM/wztKMJUm8ACyqj3S6WT9GBWFyM/hsajp6AbUFzqhNIN19B1zb3MDDlrWVNG 0BiagiavrNGcicUaNdAOMObAIe4Kw6ABB4Jzw5yjVIsut0uYaVBKD80E4fGRoDO3E+hN ZbkdFFcy43kwDVCjTxNmHdd1BE/4EE0NHxBQJXGGmtQRmozzO7q1J131KYDHiw90K30D zr7xsq5YUslit+4cIoyYa706URXy/zyJmaDntaNyV1Rhnee/dSoPWHBJP/9akFAS9kBw a4deFpwE+QXzaVT3aV3AybTqmRFtPSUYTW6G4zh664bjvwwxJZOlnlIWNq/ECrnjtdH8 o6OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455071; x=1731059871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tfW7W38u73oXDY58ExSVjQCRIYrMmZQTfpbBo08M7pQ=; b=C5keNL8j4laQbVXMzvjXxfn+wJw8yaNNDD2R3LmZe+CLFOpf2dsGrk8IPP4gWVaLKR fRTLkQAxXrXIj+4YNyiZIoLGEMoAGkfZq0T9oMjtTxM0xlwUXCuphGT0PgjuEm8Fi/Zj SnQzs51ukZbPK8ZvuuBZEVrVboh31K00QghGig0p/QZvVczaUJM+NJR2xy8gSfqkn8gh 8zXCTVuAB2Q+j7h0w+hXD+/hUEnlAL0O1nBSGrkuF6E75tcg8wVyjpAZezyAEJXsXNjD 5y4M2nf3H0DolmXUPLcpQh+nuvg9oSWL2Ip5iJTI3q/grTnuWpg/aRK4pdYyffVCg7rg mVAQ== X-Forwarded-Encrypted: i=1; AJvYcCVN9JqxIMcUFjiZkBWS+5aipU7+mX5taQjcZDjTI8nMIgHwq/AoE3+mHbs+T8PKTlLe1bq1gAkDPGo=@vger.kernel.org X-Gm-Message-State: AOJu0YxcbqEVUwPPELl96dyALXkiGcljjftLvLQYp0LRH1iBFUTVEpw8 eeTtNKakxqdg2CZr2lAHpw1HFcYRMPwgoo9UVzvs5PaWDv1L2ZYRsR0oSiQf44g= X-Google-Smtp-Source: AGHT+IFE0JHqlkVDmb2/TxlqXR6484r4+5y4byueSe80U+33dxBrQC5ZdYOn6F1eecNFW0u/e9w1Bw== X-Received: by 2002:a17:907:97ce:b0:a9a:e91:68c5 with SMTP id a640c23a62f3a-a9e5093efccmr607271566b.33.1730455070606; Fri, 01 Nov 2024 02:57:50 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 6/9] arm64: dts: renesas: r9a08g045: Add RTC node Date: Fri, 1 Nov 2024 11:57:17 +0200 Message-Id: <20241101095720.2247815-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - collected tags Changes in v4: - dropped the assigned-clocks, assigned-clock-parents properties as they fit better on vbattb node - moved the RTC close to serial node for ordering Changes in v3: - added CPG clock, power domain, reset - and assigned-clocks, assigned-clock-parents to configure the VBATTCLK - included dt-bindings/clock/r9a08g045-vbattb.h Changes in v2: - updated compatibles arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index a1d5084b074a..be8a0a768c65 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "renesas,r9a08g045"; @@ -72,6 +73,20 @@ scif0: serial@1004b800 { status = "disabled"; }; + rtc: rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0 0x1004ec00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + status = "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From patchwork Fri Nov 1 09:57:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859058 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5774719CD1B for ; Fri, 1 Nov 2024 09:57:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455077; cv=none; b=HlN1ComWNnHX8DQhip1IpLTzN8YEFxsXKepC/hZ0e1OBhgC8SZTr/stZt3yhU6XOV41spys/ltSvFGKLkps0hzuV+dEiR9K/1fdsVsVSNDR+2sbRKmaBzKO6Yjh9E73t5mhFXfyr1PjXaG0xsq/4d8hcgTkqp8YY/MUtZD4yorM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455077; c=relaxed/simple; bh=pfMUh0nCTx4HqI28z1w+eIfG9KaFRT2lAZq9NXKFrTQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gog5o2OfavWH0IJmhBcGUUV7BC2ahbcD6wz4v4jQlUrosZ/+pVXrt0MRWabZ0fo0B3hWKfeONqjnEih+BOLjg8gSJ4/+G/VWv/afE249lpIgOd+ZYdlVHuDi27itXrGcLIJAyJ/Gq9B14IzJLd7KHGJLsYG+wL8fgcbGUK0UynE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=qHXvMC+Q; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="qHXvMC+Q" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a9a5f555cfbso121392666b.1 for ; Fri, 01 Nov 2024 02:57:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455074; x=1731059874; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RPAiWzbcwfO/oeR5F4JHaOzCtAZr+PBDQTIr9NKTt98=; b=qHXvMC+QqUTqrbCnwIVLMQKxqencNzmWE8/ocVP/YfCssl6XQiNFjs94hGCYSgZkYI UTRVrfUpNSTzkKKlB4qBUIS8+Nmx8DEa1zB7bQTCARHMJk1kEK7wUCGf6SsXCEi5c6o3 jznc1rBRO/lLt/161w/PF/WObBV3F3/H+Ovwi7wj21nlNVM0YZaZD/LZzUXnYHj+NpWX 6Z1qeO+KlSSIntiAsm9M6l2/2/0jKodSOyidPZ9Fz7j5Xebh8QnbPVoxkDLtdmxxLrQi r4MCM86h//NWGMDD9z8TDayZ/RFRlmueQMvhcv2gVogULX2PVYgqsi4VBqONdgxgnl+T hrxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455074; x=1731059874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RPAiWzbcwfO/oeR5F4JHaOzCtAZr+PBDQTIr9NKTt98=; b=wX/rOHA5kf39Pq4jybXw+4E20vN86CNJtGAaSriayLfVOOdYHgE2HNPW4ChiE5uZE2 Ea2Asy7m5ZAM2h1HTfmQAzHvWrk5ikk96sTWEBI6T6lQEFa6VIGW/a6EsvFg9nnU9OkO HPIqgFUjXsh2usg6gmGi5YVstp+SKwqA6Dm/9shMliEOjY+HZ4dMgBXFYnQCHzg71E4P +eJyxz+cwjQMNcsd+bVAQf5Hapj9P4ZXhm8UQJVWO8ItQ3BHiVkuQQ3cEdmKV2EI7A21 2DdNtTWd29pUk+k8tCt8E8cj9e7Oc0iIAJKZ3wQ8v0iJMijN6EgGN9YTjj692lHM/EIA G3EA== X-Forwarded-Encrypted: i=1; AJvYcCUIDFolUfQJpFSPJTbuw6hgeXqDc/NLzECxVLM5XlDoTmihDpFNRq4pLMWuR8AXSMWNO6l4eP8I96Y=@vger.kernel.org X-Gm-Message-State: AOJu0Yz4DKZFSkxQHB+5GT/+rjLgU1VaaiCQEOqFf1uQtD60jsqG1P2V QMu5vo8sLeWwfo1NubvMp/iaVc3MVkT5eGxPNUbyD9gcGiFrdf/15q868CFfLK4= X-Google-Smtp-Source: AGHT+IHrP9FP8fHD/OSWluh8tapezeAqFQ+YzxBMlbpTwIN/za5gGLBDUt6ZXq57lFavCwyaNAz2qw== X-Received: by 2002:a05:6402:51ca:b0:5cb:728e:926b with SMTP id 4fb4d7f45d1cf-5ceb92a38f5mr2691588a12.17.1730455073635; Fri, 01 Nov 2024 02:57:53 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 7/9] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Date: Fri, 1 Nov 2024 11:57:18 +0200 Message-Id: <20241101095720.2247815-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable the VBATTB controller. It provides the clock for RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - dropped the status = "okay"; from vbattb_xtal node Changes in v4: - added assigned-clocks, assigned-clock-parents properties - set vbattb_xtal status = "okay" - collected tags Changes in v3: - updated patch description - dropped vbattclk - added renesas,vbattb-load-nanofarads on vbattb - moved vbattb before vbattb_xtal Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 71424e69939e..30bb4f5a7dfd 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ +#include #include #include @@ -344,6 +345,17 @@ mux { }; }; +&vbattb { + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + quartz-load-femtofarads = <12500>; + status = "okay"; +}; + +&vbattb_xtal { + clock-frequency = <32768>; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From patchwork Fri Nov 1 09:57:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859059 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9776719EEBD for ; Fri, 1 Nov 2024 09:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455079; cv=none; b=s5MXVbct0G1x/VbrDbjKcU7/gONUZRVjr6qP1oYot3Hl/f9APLq7bZCKgHqBYpDga9Ei8PfmaLJk/7xSLtz1BbzGIJbmYWMAeJ1lb6ywkf9IS9qgw9myzW2QBn9s+OdcjC+mDpkeEPAZ2Kj+q2gwoQVFtCtKxN1pjnhXK0jNmiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455079; c=relaxed/simple; bh=Pf9k322Noul/AUoZF1lcvPKEcxZYOYxw5S5eT2YDnXg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=M/UrndwWq38c+9rHtKFhBUGaiWFx9T4i4VHwa/5mlfYKGz+kxVmB55eUz5DfMsHR/06NLINbQ+ke2081/XMTyMhYwNQzppAZhWFUfzmu8BkEVD/izjX10DP+SFFKHHdtaYYf0XoNVQ9UcEP1ePu1mGo8aqrHmnlvZMGcVeSICPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=DfXQFLSs; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="DfXQFLSs" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5c9709c9b0cso2666259a12.1 for ; Fri, 01 Nov 2024 02:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455076; x=1731059876; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CsdPZF9emf18XQgtgS7Xp71XPblYsQ7NBPKTENRn3uQ=; b=DfXQFLSsrbMNA5VOknfWfhySdFrCjvu0tDgwrTEWF1sUtGqbT8H2o/gCGINS0nfl7j nouq6LwZH23a9x2wml4xQCO7kR5XuND8zx1qG4+OwTqPart8LGYYvU///slPG0xfhNRz 3iGfjI65SIjGdrP6opiRuR27K2hWE3QtrLCR6ZdSmbeKwAVCGhYio8n4rqw9VdZCHmJc SbCp6ML4isJAZ4q0w80/ROUfyOvxpRSM+mZwYUVUxnWEf2Za4rbFiVXnZO/X2SiJmFRV lKCrJsV+lA9gi1SEv1bh8fr+HWB1HJOU5aSTYsUeATkfWePam0hr28Fg989jaizKmSfM WDyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455076; x=1731059876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CsdPZF9emf18XQgtgS7Xp71XPblYsQ7NBPKTENRn3uQ=; b=Ohq/2VxFlkLEU7J/rM/3KJYQkaTNePQ8IHNUDaQQX9htThcevP4AuTefGidsPfEJyu btOPI1bwcDho4ALi3DyE24W3BiaEL7e3Cq5yITHwmM+ZrS49I3AdIDVb5UvUutKyLvVK 0mLIlx11FOe8exb/ZjwyjfFf9WJLkORiXy4SO0ke0QnBpKicE2RwLk+2mlpMzvL90LsM LclLl9GQRW/bFRcsrj4leYxi/rlYE681cCjImXo6R1pPdbKpunpR7/do2AlEKAo6vpKM nLyhkQUvxWWB5XkR1JWH/0N9pJSN5K4juN4cqdRsb1KS+Qz2Y746b1BWC7n1k32NuoXB Laqw== X-Forwarded-Encrypted: i=1; AJvYcCVqLmL+6qvsWYWDQLO5cr+/T1HKt6JSOSGgDBMk5eOUXJrLck0cJ7ANHn2UWY1y/tmi5wm1chnQ77Y=@vger.kernel.org X-Gm-Message-State: AOJu0YwTsknbWa5zGmrZUyvALLkHO6Jnchu+S1hvrMGnXUwB1eKobrJY EWHioFVHmCP7J4uIf0Ktlrh0Jt08FaIFsbQlE9GrCNJGnpk5QDCu2t+HLHF+XK8= X-Google-Smtp-Source: AGHT+IHIInFyvvZ21N4w9XKZUzECowUn+aG9F5+oWwykmTnOmG6gYMfAOXIH3hB+PUh/16T6BdSrwQ== X-Received: by 2002:a05:6402:518a:b0:5c9:76ca:705b with SMTP id 4fb4d7f45d1cf-5cd54afde73mr7392400a12.34.1730455075953; Fri, 01 Nov 2024 02:57:55 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:54 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 8/9] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Date: Fri, 1 Nov 2024 11:57:19 +0200 Message-Id: <20241101095720.2247815-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable RTC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - none Changes in v5: - none Changes in v4: - collected tags Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 30bb4f5a7dfd..2ed01d391554 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -345,6 +345,10 @@ mux { }; }; +&rtc { + status = "okay"; +}; + &vbattb { assigned-clocks = <&vbattb VBATTB_MUX>; assigned-clock-parents = <&vbattb VBATTB_XC>; From patchwork Fri Nov 1 09:57:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13859060 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7288F19F438 for ; Fri, 1 Nov 2024 09:58:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455082; cv=none; b=ePJQWuDRTc9qFSwZuf4pclvZI/8i+xk1mqKVi0dUPlIg6lM4+zAS6JFX2azJqonrA14GPNylVJlPkSCxKYo2utEoRTwp/2lP/N4gW5QNzBl/+g3IA07mQgFP8mWIB/a60ZG04EsijiKYqsupohzn4ftMx36VvUaXQm7e6nrQUjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730455082; c=relaxed/simple; bh=5q3sZ67C/C9aXpvq5Ph2rdpLI36199ziQrN6XfaKdN8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AvSyBiV0JfI2P4QCYoe1n34h5Myk5aTBDEAdY0FErFe1S8L+VEJIMYwqqzzZJRnvvLH2+fpEUgyTF60yUTWSOdlOxdztqVP2/+SOtd7S54mYKOZtnByFTEMf25E+554AxoaY+5eR246omoLx6WHQi7T/99WepAX8lDJv6jVRV2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=rCrJOyjE; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="rCrJOyjE" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-5c99be0a4bbso2534515a12.2 for ; Fri, 01 Nov 2024 02:58:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730455079; x=1731059879; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uDVeB7Y+VIp/FplukcEJ+LJ4Vz9niC4RyWfPRl3XIfk=; b=rCrJOyjEbqtAfGFSmF9fitisxGo6N/aRbGgwTYNNlDFTUVgrFwiO+alJUk5H/vdHTT ADRy0YSjkVKM5qnrf4cULKAzriMFJlEiPQ7i5oulnl7meAjB0/Astm4gms3dMMi9dQnE ygqQ+HDq/YfLeSgj7sfW5TbOAUMhoGiPurgD2px1kMBInsyFE7qkoQs/yNCNiO/FVdpK 8K+bwlrA/I9xyeany5P9TJSqC0OyyrqOoCU6uq9ipyX8ex+O0o4/LrSxfMMlxA51SBxp ZtOzksRmPQZLtLEEqhXsdKAbBtszq/9ju79/9Aw7IAIivTyzv2XAD3JPM90NVLl/dZvc OQXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730455079; x=1731059879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uDVeB7Y+VIp/FplukcEJ+LJ4Vz9niC4RyWfPRl3XIfk=; b=skOKowj29WrApC3+jZmiU0Rp6TANrsWxxX7Ms9RRYnwUbLxSQuMUi+sdIINzGNjQyB igOapgwPv7lKa8Vtprx/d+IwqHwsyF6HLrqjQPt6M8Eu2D+ZH+OflkE0hdkT8yrVYqCb DnJfirmOVk+aBeTzqxrc3wQFtHeO0+lrjsopJu+u11sghvFBtFfxIgLOaX9yvaSAwTXo 1QrppKx47/6U3SqZ218F7/NEPEVPrTbc23cZOdFZa8FMCXZEGgWG4bOedOsdx9O8+Ifm l6CGXDcIb74kRx6RW87TI/JIy2O6YsgJWEHBh9mHrKflTWHQ0+PmHMQaq7o2d2h2aY7s g0yQ== X-Forwarded-Encrypted: i=1; AJvYcCVxgmBqUd1H8/GeyeZo+Bt1kFVtorglvTs+eqU96w9eaTIl6bu8S/tS9/RSwT7qUFUNP1NVLflx9MM=@vger.kernel.org X-Gm-Message-State: AOJu0YxpKxji62Wko9Km5IPmmjPiBan2acsgS3lAbkQFFaotGRUEH07g +LrelrrFII5xrNIHkoYUVDbqAopMJTDmC/Bwj5z5339wNw0bPomIdvE8vBcxxEw= X-Google-Smtp-Source: AGHT+IFm5mOqj3B/Gyi2brvekA2DF+HNO4SlxfDE0BQcyiDTfbNWcuu/umQTldMEOxZlW5iJz8fSBQ== X-Received: by 2002:a05:6402:3585:b0:5ce:bb37:c2e1 with SMTP id 4fb4d7f45d1cf-5cebb37c36emr1662850a12.19.1730455078849; Fri, 01 Nov 2024 02:57:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ceac7c8d87sm1364136a12.76.2024.11.01.02.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 02:57:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v6 9/9] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Date: Fri, 1 Nov 2024 11:57:20 +0200 Message-Id: <20241101095720.2247815-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> References: <20241101095720.2247815-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable the Renesas VBATTB clock and RTCA-3 RTC drivers. These are available on the Renesas RZ/G3S SoC. VBATTB is the clock provider for the RTC counter. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v6: - enabled as modules - Geert: I kept your tag, let me know if you consider otherwise Changes in v5: - none Changes in v4: - squashed w/ patch "arm64: defconfig: Enable Renesas RTCA-3 flag" from v3 - updated patch description - collected tags Changes in v3: - update patch title and description - dropped CONFIG_MFD_RENESAS_VBATTB Changes in v2: - added CONFIG_MFD_RENESAS_VBATTB - added vendor name in the VBATTB clock flag arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0fad83642034..c62831e61586 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1222,6 +1222,7 @@ CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y CONFIG_RTC_DRV_TI_K3=m +CONFIG_RTC_DRV_RENESAS_RTCA3=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m @@ -1371,6 +1372,7 @@ CONFIG_SM_VIDEOCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_CLK_RENESAS_VBATTB=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_TEGRA186_TIMER=y