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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:14 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Ilya Leoshkevich , qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 01/67] target/ppc: Set ctx->opcode for decode_insn32() Date: Mon, 4 Nov 2024 10:17:50 +1000 Message-ID: <20241104001900.682660-2-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=npiggin@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ilya Leoshkevich divdu (without a dot) sometimes updates cr0, even though it shouldn't. The reason is that gen_op_arith_divd() checks Rc(ctx->opcode), which is not initialized. This field is initialized only for instructions that go through decode_legacy(), and not decodetree. There already was a similar issue fixed in commit 86e6202a57b1 ("target/ppc: Make divw[u] handler method decodetree compatible."). It's not immediately clear what else may access the uninitialized ctx->opcode, so instead of playing whack-a-mole and changing the check to compute_rc0, simply initialize ctx->opcode. Cc: qemu-stable@nongnu.org Fixes: 99082815f17f ("target/ppc: Add infrastructure for prefixed insns") Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Ilya Leoshkevich Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7689b2ac2e..be93777cf6 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6423,8 +6423,6 @@ static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) opc_handler_t **table, *handler; uint32_t inval; - ctx->opcode = insn; - LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), ctx->le_mode ? "little" : "big"); @@ -6558,6 +6556,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->base.pc_next = pc += 4; if (!is_prefix_insn(ctx, insn)) { + ctx->opcode = insn; ok = (decode_insn32(ctx, insn) || decode_legacy(cpu, ctx, insn)); } else if ((pc & 63) == 0) { From patchwork Mon Nov 4 00:17:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6244D11186 for ; Mon, 4 Nov 2024 00:20:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kob-00075Z-JT; Sun, 03 Nov 2024 19:19:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7koV-00073Z-Gr; Sun, 03 Nov 2024 19:19:23 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7koT-0002EF-Mu; Sun, 03 Nov 2024 19:19:22 -0500 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-720be27db74so2257357b3a.1; Sun, 03 Nov 2024 16:19:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679559; x=1731284359; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hZKVJSe3jvXud7zLkI4v01kv3KA+r8AleeOvAHmR7uQ=; b=GYBNb+a/l+NsDHPwSWBGojIlsdAL/MAqweNL8ILWSziOxwX4Pfg0h1VFy/+2lEq7jJ TPhBsGDz5aTsSDRJPKRwD6Mu413UF+OY69Twi+bE+x1OesJpHjc3waKXePQpkcLvC0lp Cc+g5FY1DiN5byPekwpnMGCe2qOtU1cJpMo5KrtXwFcb1gr3bHAuz85AcmRgVq3KvOEc cE/laRQhLMxB4uindkGL39QEOftLybUKRSzhmDszGm6zW1XqFxFhS5bV1n1n4+k9m0Xf FL7lkHZHBR/dJYnEtFnL14QQ7FO7Hw0hrp1hPViI9RK/RETn7Uoz5k7/foOtj1ppZnw5 xOpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679559; x=1731284359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hZKVJSe3jvXud7zLkI4v01kv3KA+r8AleeOvAHmR7uQ=; b=lhOR2jkcbbxmgEqjmXeQKF5A1E3L7r8G7Yx502/5iMOQP/T+D7u1YVoM1ajCoom6Ik bEkBa75BfP3efrawmvnb7zbVDau/gCNQmXlpwQWhfQ/HVm5MQuM4JEGpanf2tFVek/Zi p/duv0PhlOVmb3k8osiIJtnRUuzbbilJ94a072QSWbt5rbOJ1FaMKbfdglxhcjSOyUUF DnRu6hl++WbMs6TpQlqU3WGWPns3Av4Pl++hMt+1hfBsxacXYpudeM01V3tW/+LMaJhC fEut2krjBirttQQvsLzM1Z+IaA4sAVcJEkj3nCQ27ZDdmIxzIu73uYsojY46jUuMrXAC La6A== X-Forwarded-Encrypted: i=1; AJvYcCV9gydnn2YdpnA+HkEqVm5stR+b+Vrim8W/Br5vmPXJyd2AO5r2nBOU66OLZqZe6zZ1T3eQKYCniCMEv48=@nongnu.org, AJvYcCXWVMoC1h0EAXQe2vsv5+VdjoepOu9ALBBh6+7yNtvlh7IMRFVqcWu+NK0kzVHxlYbhkBguJOdTtw==@nongnu.org X-Gm-Message-State: AOJu0Yws/p2Fc0PAjrAnpze6g5eMH1+8096BXSX7Fgb6BAzDbnTuLVFn fu2+fIKVMjW954uI0rYfcTmfxiio5K2U1C9aL1cW7EwQHuGh3NCrQg5qsw== X-Google-Smtp-Source: AGHT+IEQ+PEWCEXyrIa9y1S2r8KUkAPNi6SymkbfKzOKlmQU1IJk69KuKdX6augBqlh/ugNL57+V+g== X-Received: by 2002:a05:6a20:e20:b0:1d8:f97e:b402 with SMTP id adf61e73a8af0-1db94fc412amr18813899637.13.1730679559533; Sun, 03 Nov 2024 16:19:19 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:19 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Ilya Leoshkevich , qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 02/67] target/ppc: Make divd[u] handler method decodetree compatible Date: Mon, 4 Nov 2024 10:17:51 +1000 Message-ID: <20241104001900.682660-3-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=npiggin@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ilya Leoshkevich This is like commit 86e6202a57b1 ("target/ppc: Make divw[u] handler method decodetree compatible."), but for gen_op_arith_divd(). Cc: qemu-stable@nongnu.org Suggested-by: Richard Henderson Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index be93777cf6..47ca50a064 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1820,7 +1820,7 @@ static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); } - if (unlikely(Rc(ctx->opcode) != 0)) { + if (unlikely(compute_rc0)) { gen_set_Rc0(ctx, ret); } } From patchwork Mon Nov 4 00:17:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E0A1D11194 for ; Mon, 4 Nov 2024 00:20:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7koc-00076B-L2; Sun, 03 Nov 2024 19:19:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7koa-00074z-Ea; Sun, 03 Nov 2024 19:19:28 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7koY-0002F2-Gj; Sun, 03 Nov 2024 19:19:28 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-71e8235f0b6so3171172b3a.3; Sun, 03 Nov 2024 16:19:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679563; x=1731284363; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZqpqSjhDlR0KKOwKpuJzD0Sk7j1XMBWO2P6fYwp7tiY=; b=Be+oU7wYANy+A7XdBjU1USzy4P/GOUk8yaUqpcYcntE8TvpelzHAB3qdGzWUCWxyt8 v3sGMP8Oda3XOVcu7iXXURQJUY46LP/ZsGZAx4sZtuPdGkR/Gib4MjjVywW31Xl9yrat EFbRXEceDhkhfXBZY+XbAg0rw6KGE22sHWTNRra38bibzxmWepw49ISSatAtEZeQVh91 3l5xMkwTmU9L5wkJwcpKUEtl2eM2INtVsv1AnprBfkZizL2dct9QlRO+t0TjZrCPKJBu GkEKHl/WntCqxmV76nHAyuwY+WVnMP4VFjjNe81aVzToA6VhwTiZiht2oN+lgGC8Imux dDkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679563; x=1731284363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZqpqSjhDlR0KKOwKpuJzD0Sk7j1XMBWO2P6fYwp7tiY=; b=HK26RYsIrU5Hcl600NEY6+sXcsF4dht2Uce28ZAhgNUSBC/Qc9U22X77DyURbntn+d ni4p0N/hGK8IredOx/jHbONkXvSie2cOXTjSgIfA7IsEfYmo94+pdLQgrVei68RgZLUB Nx6f5n0MUOBlI67RYehBFNs8/ovhJfK4CL+AdnltbPzJwxhRoQ9a6+aeDyBfUvxqPBzl oEHSyZs2qUeT1H2/9Cv+5Xd+O9zQlRDylmswGUNSeVDSLpl0A3NkBjD0euLNZYlZdlkL ZRs2bNhDBiLrYHbWJrAoDO6jnZvUOIiSIINzOGRQTH/15/YqlKsijRG3cEnONF5N2AOc sApA== X-Forwarded-Encrypted: i=1; AJvYcCUiGKKrPHcpy0MCMEP+NRBYLMCNOhKmKmM5erleow/f56ADWL/QK17yo2Y4hUOANjuiS1o2w+6ycQRMfWQ=@nongnu.org, AJvYcCX97hg8vSthGqKq+fOjkx3dld8GKiJtRkF23qoFBUWeSI0FmBMkS+mnwxhDUHps8RV9JEsHonxBQQ==@nongnu.org X-Gm-Message-State: AOJu0Yw5JVDa18yy1lBnP1w8940aoh7R0jR2Qz75nLWdVuw/Kxlphbbe U+sOkycYrSdGSCe7hDj6FqRbqXkJidUwGkXy8nOgI+5JgyejFUFjohsJtg== X-Google-Smtp-Source: AGHT+IGcGQYzgmsuMRDc2LVhOvirDpy9UtjXc4h4NdNmHRzW7i4XpkwRLUyJEqVzTLIp7n8398y6RQ== X-Received: by 2002:a05:6a20:d493:b0:1d9:111f:4b46 with SMTP id adf61e73a8af0-1db91d86c41mr20656991637.12.1730679563177; Sun, 03 Nov 2024 16:19:23 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:22 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, qemu-stable@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , Richard Henderson Subject: [PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation Date: Mon, 4 Nov 2024 10:17:52 +1000 Message-ID: <20241104001900.682660-4-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The serirq routing table is split over two registers, the calculation for the high irqs in the second register did not subtract the irq offset. This was spotted by Coverity as a shift-by-negative. Fix this and change the open-coded shifting and masking to use extract32() function so it's less error-prone. This went unnoticed because irqs >= 14 are not used in a standard QEMU/OPAL boot, changing the first QEMU serial-isa irq to 14 to test does demonstrate serial irqs aren't received, and that this change fixes that. Cc: qemu-stable@nongnu.org Reported-by: Cédric Le Goater Resolves: Coverity CID 1558829 (partially) Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_lpc.c | 10 ++++++++-- target/ppc/cpu.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index f8aad955b5..80b79dfbbc 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -435,13 +435,19 @@ static void pnv_lpc_eval_serirq_routes(PnvLpcController *lpc) return; } + /* + * Each of the ISA irqs is routed to one of the 4 SERIRQ irqs with 2 + * bits, split across 2 OPB registers. + */ for (irq = 0; irq <= 13; irq++) { - int serirq = (lpc->opb_irq_route1 >> (31 - 5 - (irq * 2))) & 0x3; + int serirq = extract32(lpc->opb_irq_route1, + PPC_BIT32_NR(5 + irq * 2), 2); lpc->irq_to_serirq_route[irq] = serirq; } for (irq = 14; irq < ISA_NUM_IRQS; irq++) { - int serirq = (lpc->opb_irq_route0 >> (31 - 9 - (irq * 2))) & 0x3; + int serirq = extract32(lpc->opb_irq_route0, + PPC_BIT32_NR(9 + (irq - 14) * 2), 2); lpc->irq_to_serirq_route[irq] = serirq; } } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 321ed2da75..bd32a1a5f8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -40,6 +40,7 @@ #define PPC_BIT_NR(bit) (63 - (bit)) #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) +#define PPC_BIT32_NR(bit) (31 - (bit)) #define PPC_BIT32(bit) (0x80000000 >> (bit)) #define PPC_BIT8(bit) (0x80 >> (bit)) #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) From patchwork Mon Nov 4 00:17:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 772B5D11194 for ; Mon, 4 Nov 2024 00:20:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7koe-00077y-RQ; Sun, 03 Nov 2024 19:19:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7koc-00076W-QK; Sun, 03 Nov 2024 19:19:30 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kob-0002FM-7i; Sun, 03 Nov 2024 19:19:30 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-720d01caa66so1916223b3a.2; Sun, 03 Nov 2024 16:19:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679567; x=1731284367; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QZ1z/XmFIN2JVjOsuU+EgbLKz3lUKwqpU7/B+luzQLU=; b=hYCnW4LUR8ie6C60ZRK/idHEya/dYjZl179kDNnWaSd0hSS6IZWdKb+gS9k+o3izni OGW5EZUQayS1EJKni2A8ePE0G4Bx0lCM8g7WUNPYc14+7MjU6BjyJkf+6IqoxEjj0pR8 7qDOmeXzWuzdt+aRSwg0XyqZBF0S/Asex1S5KI0nxM84XpDCemG2re9UsjfPGh/yGf2S IZRbFCROVuemkhegL2Ji0SA6v+5OJd+MvXxphfK0uwtcaskUo5TL/frevFUxAPnDnwEl dFyvfTzUFR6lWGtlkAu+loU4sAr1Xal8cicsZKE96GY33ALPKVnVxqKXuKjSFgIVvT9B tn0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679567; x=1731284367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QZ1z/XmFIN2JVjOsuU+EgbLKz3lUKwqpU7/B+luzQLU=; b=oTwtg3uNfwBx4nXadCg5vwYB7XCpw6P9HX70Ju/VgyPCmxqhwctwrflQiqdzx+Qorx /JckGq2STTpJXQPd7fjVO3SwjoHOjxWtQZps65W0MdVkUMLBOXKlzkB6odu91Xb3P4vF Ds1lkQHig852MQgRCYGtt+YAH0yPNraKNYS5j43tTeM0BdC4wqUucn0zGk3IXZq0ziY7 3aWzFNZvMERlGZKDjdZ8hWhT51EsgNz3utOtinKFM7CJRHAoknPvhIc6d6GpiPPb14Ud bZt2rld3+YaeQ7kuABUD5I516NmwCYyahqTvR1pK9ktMJVzmT0AzdhagKg4xjqbGFbCJ ZxKg== X-Forwarded-Encrypted: i=1; AJvYcCUxDT4P9p28FbSq9Ur7woVGyJGzkd2RFwefDkUR2CXK0uY/u8WRnTrtnaneu1MXzutrw3jXdn4AfhRfL9I=@nongnu.org, AJvYcCVEI2qTDKH7LyXIfJtMcn26p/TBAxhd9NfiBNkkROhBTqD7dKV73AyIHnFX0WCLwACnJVbET99i+Q==@nongnu.org X-Gm-Message-State: AOJu0YxS2b88pFQLU2JbexeGWvloiqow/rnMLiRKDxSSE0qKnu1YmlEc E5n/9on6OYhRmsBKD7Qvjk6CED2FZtj+hG5K14TUZdQ+cHPwkgD9aR+Abw== X-Google-Smtp-Source: AGHT+IGoI4wHUNYirAtppX4AkD8+OrBlgOIJMJhZDWn8oidp5uGWB8yW3rmgzgOu4Q0zWyYPS/WLZg== X-Received: by 2002:a05:6a20:a10b:b0:1db:dce8:c26f with SMTP id adf61e73a8af0-1dbdce8c29emr1648643637.33.1730679566857; Sun, 03 Nov 2024 16:19:26 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:26 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, qemu-stable@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , Richard Henderson Subject: [PULL 04/67] ppc/pnv: Fix LPC POWER8 register sanity check Date: Mon, 4 Nov 2024 10:17:53 +1000 Message-ID: <20241104001900.682660-5-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org POWER8 does not have the ISA IRQ -> SERIRQ routing system of later CPUs, instead all ISA IRQs are sent to the CPU via a single PSI interrupt. There is a sanity check in the POWER8 case to ensure the routing bits have not been set, because that would indicate a programming error. Those bits were incorrectly specified because of ppc bit numbering fun. Coverity detected this as an always-zero expression. Cc: qemu-stable@nongnu.org Reported-by: Cédric Le Goater Resolves: Coverity CID 1558829 (partially) Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 80b79dfbbc..8c203d2059 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -427,8 +427,8 @@ static void pnv_lpc_eval_serirq_routes(PnvLpcController *lpc) int irq; if (!lpc->psi_has_serirq) { - if ((lpc->opb_irq_route0 & PPC_BITMASK(8, 13)) || - (lpc->opb_irq_route1 & PPC_BITMASK(4, 31))) { + if ((lpc->opb_irq_route0 & PPC_BITMASK32(8, 13)) || + (lpc->opb_irq_route1 & PPC_BITMASK32(4, 31))) { qemu_log_mask(LOG_GUEST_ERROR, "OPB: setting serirq routing on POWER8 system, ignoring.\n"); } From patchwork Mon Nov 4 00:17:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25BF6D11194 for ; Mon, 4 Nov 2024 00:21:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7koj-00078i-83; Sun, 03 Nov 2024 19:19:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7koh-00078Q-Lu; Sun, 03 Nov 2024 19:19:35 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kog-0002G5-78; Sun, 03 Nov 2024 19:19:35 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-72061bfec2dso3400875b3a.2; Sun, 03 Nov 2024 16:19:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679571; x=1731284371; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YRtDdUtAOQ8hbWJDgTNy6ROc/6VA9Q2cPv4bY78jXvQ=; b=Y3PSFh2PLeI4YXXXfzq4y+S57WjxxAZpNneVdcBQS6UhLV9m53DmHAkPh7fhOYV0/b N1tHDJ8kgzdgKAiH10hTPW7FtjONfGD57ci04ezI73QAJsvpATmAAh8ZH5rikKLm0RZg EfimqEVh4L25zeCZMw2u0BG9v8869kx4M4RS13im+DtK6n2eLuKmPauTBADOgspYNJyx RX0KIo98FPTiK0kWGpLZVjfLNgDlCg+82ZSVIDV9ojrslq3HjLmcWXOReRU6A0X2DtGc +9K2QJXPjAXpvx5OVprKwsFOnRPHPtHQ9b/Id8BbD513gs5kk8d2uAkhOxOjXBbk+1Ux /7WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679571; x=1731284371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YRtDdUtAOQ8hbWJDgTNy6ROc/6VA9Q2cPv4bY78jXvQ=; b=wgeeSZr89/gnZQc7W7LooD60vKh45wq7bMp2IVZlU79vKOF4WICX7qYAsWPnRR6hWU q2XQXrwpnJ+t6zo4J5kmr68a76StK5aDf6KcfdppCZ+WVLgJF4ujYU6+mKV2a2gO/oxH OJZLZArYQS3/Dt/6pnpdt8QvPIqFpAdqX+7LKfJ4aTzdAK4aJYy3SMO4IqqXiqKFxQjZ 3AxWck3XAa6/TWsYGCESzdKiJYeId+6Bji6mpMdDvZkWbbqy8IkiY7D02AXQoQIEPcj0 /a6tGbNxXebEKUwsfVRZ9DxNrQoKb/sOgy4EcOXy1gQ4LMKVighPgCKztnJ7rIr1pRD0 +goQ== X-Forwarded-Encrypted: i=1; AJvYcCWcCzL5CiWjUklAnv6ywNOUCnOPZEzqx7gm05vXlvaxDbyCEePxyRRJowxuU738VtP0WpsvWFA1/g==@nongnu.org, AJvYcCWpopvkQiHv33O99aPZVZJtGzemXsxxd2fv8vejQRxqWwQZMM9EedkLfaFdlsu1VAlMbfDNi2S1FN4Q5U8=@nongnu.org X-Gm-Message-State: AOJu0YwE7XQliDhrsCVOAwvWCnyQbPESHSZEIThryqsZU2WzUd5yJ7w+ SmXcBZ28V9BGWpRIGkPKI/6D1jIpe90QMSY/Rb5PbawujM3+7+WiukSN6w== X-Google-Smtp-Source: AGHT+IEYPUgF/yuVF6HC9OqFpJJti0BFo84aY+nmCP39Pt56CW1TWjaQTHKNO2JifwZ+2LNa1caG4Q== X-Received: by 2002:a05:6a00:4fc4:b0:720:36c5:b53b with SMTP id d2e1a72fcca58-720c99b5c7fmr14477718b3a.17.1730679570929; Sun, 03 Nov 2024 16:19:30 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:30 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, qemu-stable@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 05/67] target/ppc: Fix mtDPDES targeting SMT siblings Date: Mon, 4 Nov 2024 10:17:54 +1000 Message-ID: <20241104001900.682660-6-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=npiggin@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org A typo in the loop over SMT threads to set irq level for doorbells when storing to DPDES meant everything was aimed at the CPU executing the instruction. Cc: qemu-stable@nongnu.org Fixes: d24e80b2ae ("target/ppc: Add msgsnd/p and DPDES SMT support") Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/misc_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 1b83971375..f0ca80153b 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -288,7 +288,7 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val) PowerPCCPU *ccpu = POWERPC_CPU(ccs); uint32_t thread_id = ppc_cpu_tir(ccpu); - ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & (0x1 << thread_id)); + ppc_set_irq(ccpu, PPC_INTERRUPT_DOORBELL, val & (0x1 << thread_id)); } bql_unlock(); } From patchwork Mon Nov 4 00:17:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C665D11198 for ; Mon, 4 Nov 2024 00:20:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kok-00079x-Rr; Sun, 03 Nov 2024 19:19:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7koj-00079S-Nw; Sun, 03 Nov 2024 19:19:37 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7koi-0002GV-7V; Sun, 03 Nov 2024 19:19:37 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-71e592d7f6eso2831456b3a.3; Sun, 03 Nov 2024 16:19:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679574; x=1731284374; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OjJKXaqs1iegzxz1bDudDPZPn8CH5RdfS7pWj3NCT6c=; b=mdwhBkTX9bdupTqil03ICE++p36e34Kxmw1X0eYY+bGSK6cQw1NTlBzWzp4JeEEW6Q a/6Vf44aCVXz3PWx6f0xQYJgUH+iF+4W07IF9ne62qvh0QqBcs5sAMzcmCYBUVdGhXIF SuerSkZEZzm76lSyvTisO3IuirfYkbbWSbgqZJGnQJ5Opm+DMAZrO6TV4RruUKxCSWz5 GWKFi9iaZ1OLFRvN6Qn4+5rDxV1R4TjqCNW8MGkdhHz43b6tutPZk6jP21nogizPAUbq xi++zfY8rv6+pwceqZ1EZfqvo6vrJGXWnDi7hOcQqIFf047TkfvGr3EVAGFYqRJ9piYE FYAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679574; x=1731284374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OjJKXaqs1iegzxz1bDudDPZPn8CH5RdfS7pWj3NCT6c=; b=P7uu7PzT5Kq6P5+Cz5wpY5/o5d4Jn4SKAKPasqGSL4B1fQC53exlGUItGSuytD0fhq OQkjIdN2GS0l9jQ7MjbqATh9CCpyAHGCFQusXEDNVApIS4A2kAdG31o1Fnqlq2s0AP29 bn+raIdXexmtHMKwZd8y3nn+yxr3NZmkXI/JGNsE5ysMjxneSfjbBJLQJzRblu117crV evjecgpK1C/MpfLuF3FsoCE8xb91wo+eWjCE2V3Ebo2Lhlb9QNxzOJYZZ5nbFFcNotwZ zRvFTOKqz7QrQ2ZrY/RhHDPoRWDo+kXIt2jNvPPy5JkRKHZQANvDL6kjfCBwrmZkNGBW EqVw== X-Forwarded-Encrypted: i=1; AJvYcCUoI1ADHwffNO2pZ+FuumlCyMz7vOlRB7UBXp4hDsAhKUMWGjDt048O8nc8yZidvZgBRXYVtQpzyA==@nongnu.org X-Gm-Message-State: AOJu0YzIcOR/dB3tq0Z9LXtIPQxspPKBVQW5vpPHNqgnwpfWHtvIgrGm Ri0U8JTJAI8XIz6KdIsGnHmKYwyrj+PT2pR73Z85mOI3qiYrbW1n5BOPOg== X-Google-Smtp-Source: AGHT+IEoVzhlMMyBp9YZXRbcCvsLDWNK9jeXh/6O4VQJBpgF+hfJUUBI9y7GWCoYMVqhF9oEq7HOeA== X-Received: by 2002:a05:6a21:78d:b0:1d8:aca7:912 with SMTP id adf61e73a8af0-1dba5409a21mr15403489637.28.1730679574367; Sun, 03 Nov 2024 16:19:34 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:33 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Richard Henderson Subject: [PULL 06/67] target/ppc: PMIs are level triggered Date: Mon, 4 Nov 2024 10:17:55 +1000 Message-ID: <20241104001900.682660-7-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In Book-S / Power processors, the performance monitor interrupts are driven by the MMCR0[PMAO] bit, which is level triggered and not cleared by the interrupt. Others may have different performance monitor architecture, but none of those are implemented by QEMU. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f33fc36db2..701abe1b6d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2187,7 +2187,6 @@ static void p7_deliver_interrupt(CPUPPCState *env, int interrupt) powerpc_excp(cpu, POWERPC_EXCP_DECR); break; case PPC_INTERRUPT_PERFM: - env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; powerpc_excp(cpu, POWERPC_EXCP_PERFM); break; case 0: @@ -2250,7 +2249,6 @@ static void p8_deliver_interrupt(CPUPPCState *env, int interrupt) powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); break; case PPC_INTERRUPT_PERFM: - env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; powerpc_excp(cpu, POWERPC_EXCP_PERFM); break; case PPC_INTERRUPT_EBB: /* EBB exception */ @@ -2330,7 +2328,6 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt) powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); break; case PPC_INTERRUPT_PERFM: - env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; powerpc_excp(cpu, POWERPC_EXCP_PERFM); break; case PPC_INTERRUPT_EBB: /* EBB exception */ @@ -2444,7 +2441,6 @@ static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt) powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); break; case PPC_INTERRUPT_PERFM: - env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; powerpc_excp(cpu, POWERPC_EXCP_PERFM); break; case PPC_INTERRUPT_THERM: /* Thermal interrupt */ From patchwork Mon Nov 4 00:17:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 893EFD11194 for ; Mon, 4 Nov 2024 00:27:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7koq-0007BZ-8f; Sun, 03 Nov 2024 19:19:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kon-0007Ag-Mo; Sun, 03 Nov 2024 19:19:41 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kol-0002HI-Bw; Sun, 03 Nov 2024 19:19:41 -0500 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-71e592d7f6eso2831471b3a.3; Sun, 03 Nov 2024 16:19:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679577; x=1731284377; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J1xac5W5zKwCyt+Affs+nBDH85dTqE+Fj+UGOQD6hfU=; b=E8E5I7/C7EKp9MtANFskQdcq9eUInc1v8z8V0YbbObyDPAub3lMJXtzP9i+oTCGlV9 o1O1+ZMrI6ZclHHiL1PPfqSAEzLqspbpuPSmc3xA4s0KuPKeb39UT79FUWSYDCnMSuvx qFdyvvTdmsTPrS+xsWKta10ofqh6BWtOIiv5aBILySJPKVtBZPeDqyXZxyYRtnpYrNwH lde/sOentJwsrPon53Yl1Mp+RXMTS9Gvn6f9D2sygvcCwPCX280w8fwIIBmgqj5KwTTf cnRAR6i/dnHnW/cBQ7C5olsviwT6u5tlOvSOMGxrhRJUi3A4FWHmeU4oP+KEBboCUOrQ ifFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679577; x=1731284377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J1xac5W5zKwCyt+Affs+nBDH85dTqE+Fj+UGOQD6hfU=; b=m1+gSmrg4zDhU+Id2uSrnhMKIKIlmUrejC5M9abvBQgJs/oAMpbIXoO1lArb8q3H6f 7iIYrC0OYTcv/cELZMCL9eUOKhfLe2JRdEZVysHWQENE1Nsi2mcWVUpmEyZz+FmfB/Ct Oc26ciTshJ+Zyv1DypAORN8xRtpH017iWTcmLDPpRCl1OTSCCIsIDFnxDAqgAvxhea5N w/sSyWjl54n7RHQfRvYMcFH1gMHUucfvsYsEXxb9x16BP4FWpS0DNfLJlBdiavaPgGU7 b851s2CW8RMnoyeiAyDTtRUP/jt0kE3/QdOsKhrEmG8gKAQCDMJC0UxQRiBGUeJtbYx6 sFNw== X-Forwarded-Encrypted: i=1; AJvYcCUyOrgBqDW6IHp+ibsSM+IJmJSpdvvF2XdVt9/ixX8owNF3SQXJQq4LP0Oo06G5XV+p7ybO2HVEjA==@nongnu.org X-Gm-Message-State: AOJu0YzB+dRoeEFdBx8parjmhkxp0rzevVAU6kz82Uy1VwT8bsMAVpnf KiXBmG2dhzbkTHz537ubpo2kdXwECN366ppoDFYF/1Mmx0cZHp0EdxxYuw== X-Google-Smtp-Source: AGHT+IH5cHPj72ksc9koh0cETtaxNbETBrj+9kfbgW9UZ2hzjdvV39jCmtTagZVgromXuWKTVmjQXg== X-Received: by 2002:a05:6a00:3d4d:b0:71e:108e:9c16 with SMTP id d2e1a72fcca58-720c98d51ffmr16913733b3a.12.1730679577430; Sun, 03 Nov 2024 16:19:37 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:37 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Richard Henderson Subject: [PULL 07/67] target/ppc: Fix doorbell delivery to threads in powersave Date: Mon, 4 Nov 2024 10:17:56 +1000 Message-ID: <20241104001900.682660-8-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=npiggin@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Doorbell exceptions are not not cleared when they cause a wake from powersave state, only when they take the corresponding interrupt. The sreset-on-wake logic must avoid clearing the interrupt in this case. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 701abe1b6d..b619a6adde 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2237,7 +2237,9 @@ static void p8_deliver_interrupt(CPUPPCState *env, int interrupt) powerpc_excp(cpu, POWERPC_EXCP_DECR); break; case PPC_INTERRUPT_DOORBELL: - env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; + if (!env->resume_as_sreset) { + env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; + } if (is_book3s_arch2x(env)) { powerpc_excp(cpu, POWERPC_EXCP_SDOOR); } else { @@ -2245,7 +2247,9 @@ static void p8_deliver_interrupt(CPUPPCState *env, int interrupt) } break; case PPC_INTERRUPT_HDOORBELL: - env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; + if (!env->resume_as_sreset) { + env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; + } powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); break; case PPC_INTERRUPT_PERFM: @@ -2301,6 +2305,7 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt) case PPC_INTERRUPT_HDECR: /* Hypervisor decrementer exception */ /* HDEC clears on delivery */ + /* XXX: should not see an HDEC if resume_as_sreset. assert? */ env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; powerpc_excp(cpu, POWERPC_EXCP_HDECR); break; @@ -2320,11 +2325,15 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt) powerpc_excp(cpu, POWERPC_EXCP_DECR); break; case PPC_INTERRUPT_DOORBELL: - env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; + if (!env->resume_as_sreset) { + env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; + } powerpc_excp(cpu, POWERPC_EXCP_SDOOR); break; case PPC_INTERRUPT_HDOORBELL: - env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; + if (!env->resume_as_sreset) { + env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; + } powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); break; case PPC_INTERRUPT_PERFM: From patchwork Mon Nov 4 00:17:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61645D11194 for ; Mon, 4 Nov 2024 00:24:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kot-0007Cd-9g; Sun, 03 Nov 2024 19:19:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7koq-0007Bc-O1; Sun, 03 Nov 2024 19:19:44 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kop-0002Hu-8H; Sun, 03 Nov 2024 19:19:44 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-20c70abba48so30758655ad.0; Sun, 03 Nov 2024 16:19:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679581; x=1731284381; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ySL/GEMA+MP1Yc5YuF/O92O+3rYMxrud3tBnxWGFNSs=; b=I58PWUHvaX9fCGTtvsCR0/ZWikENWj6VqbYKTl+DIL52my7jQTwLq4LIy7Mpm+mwVt bwIOZnpq5C/bQDxqX5bGptmsshKkCFuXxJFr+MyR/KzNqDYDqQTJ3Oj1Xw1GHtPDXII3 M/Wtt6f7qzyZsoo2PODQz3zq1jLiUCeun54is37A77gRP2juHQXjKOYBx5OxGXZu+hS1 79mg0w87z8N8z9sJ6h0S5SUgfsZtRds2ZqW3tflSIfBHBuWxxre8PHbgvnOR3ch5Rr5q kv33r27whi2XsgU3aCsz+X1fYUNKCIYP5K6tE4LQqvqxpyhMDZnY53v24ohaLvOkAR9w idlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679581; x=1731284381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ySL/GEMA+MP1Yc5YuF/O92O+3rYMxrud3tBnxWGFNSs=; b=vEG/8xBhXV7+WZ9nrvLmAWLi5BJaSKXf2e8xQ7sILPYjuyQLrM+/wvakBGlgDTUcpA HKBOhuccAjwqZUZ2zsVoQLzmLmoBq1M4QOHnTgpoIOLVKOni8xhgHPuEieIDmoJpjzhE 9w3WHKeeyz+NnSPiZyvsidB2bc4XHuyw2QJt2fl3Kzz+B+UY7SOjGaPUo6cxDqFp0XN2 VW9am6vtiyCX68uMfnzLagQHfm3USwZIjtCnPAbolXZFdKpFrvgpiuZlLKf6+KYmpfeu SMSP4V7tB642drDYTNIy+v8BQFNroYbKxgQ20CikjfLLmL18yqUiF4hxcN+vERvcUelp Znow== X-Forwarded-Encrypted: i=1; AJvYcCUy7ZxHQqoM91+dPkkTAdogHabO3gsjUvFQzVmDc1xn3AmWZu1mQCbVTNzkDLc0UtQENr76MyCCZ7jNP4A=@nongnu.org, AJvYcCWfIInAqEv7Rjevm6kKIC43nLCzvJoMBtXkTeC4qPXUk2VueK8ybO6qE3FSCHVlSOfm4zYn8FYXYQ==@nongnu.org X-Gm-Message-State: AOJu0YyvmLG1QP0XQYMMGdSnV/ALujCjq08PhQ6fuhnjc7O77RTUCRZX jVWM6Pxj/6lU7b03cy5ilUk0pmuqpgmCJrn7A3nCRHIlocB0t/sAHdaaFg== X-Google-Smtp-Source: AGHT+IF4hphWS1zO/m1NDCH3FoiaVrS423NwVH0O4CwT3O33NhwFddjw26NzSmqzfmErcumezLnvDw== X-Received: by 2002:a17:902:cec7:b0:20c:8763:b3f7 with SMTP id d9443c01a7336-2111af3bc88mr148502475ad.17.1730679580849; Sun, 03 Nov 2024 16:19:40 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:40 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, qemu-stable@nongnu.org, Richard Henderson Subject: [PULL 08/67] target/ppc: Fix HFSCR facility checks Date: Mon, 4 Nov 2024 10:17:57 +1000 Message-ID: <20241104001900.682660-9-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The HFSCR defines were being encoded as bit masks, but the users expect (and analogous FSCR defines are) bit numbers. Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bd32a1a5f8..f7a2da2bbe 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -635,8 +635,8 @@ FIELD(MSR, LE, MSR_LE, 1) #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ /* HFSCR bits */ -#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */ -#define HFSCR_BHRB PPC_BIT(59) /* BHRB Instructions */ +#define HFSCR_MSGP PPC_BIT_NR(53) /* Privileged Message Send Facilities */ +#define HFSCR_BHRB PPC_BIT_NR(59) /* BHRB Instructions */ #define HFSCR_IC_MSGP 0xA #define DBCR0_ICMP (1 << 27) From patchwork Mon Nov 4 00:17:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91BDCD11198 for ; Mon, 4 Nov 2024 00:22:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kou-0007D2-U7; Sun, 03 Nov 2024 19:19:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kot-0007Ci-Hs; Sun, 03 Nov 2024 19:19:47 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kos-0002IV-2h; Sun, 03 Nov 2024 19:19:47 -0500 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-71e681bc315so2510155b3a.0; Sun, 03 Nov 2024 16:19:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679584; x=1731284384; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9T3Tbj+pHEEP02l1LsK9eDXYECtrkXHZOnBNH9gxVPk=; b=ZFx5K70HVZHIETKbDE1loK+rOh73VzvGt1NeF+INIw99LV+kJ5nunl/GjstSNoPU/M XbzIfxBYeHGil6dUXLycyJCQFOHxSwOdKzshk0zNWsdwCgYm8nDIAEnVKclKqUuZYZbJ CYXnp6vw8nZ8JbycisFjv0jbbxcuPmhLogF2pwoi2/cZLAI4sFzWiDdaCiLGNFUgzagB EaW52Iu58f48WQcdcHEXjNg6iWubMx/rx1bdPC2NofuXfwEfEpacCj/DOHcLoxbTdRcw YhA0hTns3m9DmtRglfNh6iHI9cY//ASqBi1uZI05BzXn9ecz4smfh2nIDf5pWbJdjXX7 eO4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679584; x=1731284384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9T3Tbj+pHEEP02l1LsK9eDXYECtrkXHZOnBNH9gxVPk=; b=kXejCDrgRX1Z/fVe3b7Ze6g5wijgh2aGa/weqRBot/5M20qjHbj/thhVsdCIpxaxer jU8nvyUQpbqTatSmKOv4jNslZKmOF060Us+0G2HJWKW9J8iRFv6i7q2nuxQj/u2a1IZJ JJz5PTeiE+eHIMUVszGjhErPJb08KWjtE7UhGEhwlWB013ckcLXP5PEdoHH3EEfx39pH kKfnjCE3vUvgR2CmIHN+7VfsEyFkN7wFQ2qjgFvcKh0GBdHK5yfyyS1468NjFy2y+Rm1 yTYCgB2eQXbbLa4jP+rfSzj30FVXVbcoEZdEx/QBgRV4x+glhB2o9L3ujML8sWZCWnQE 40vA== X-Forwarded-Encrypted: i=1; AJvYcCUwLA4R7QYmWJ+lIx2kqWB3d50/MbxTeKebXzIjCHFLgIoQmxjk24TArNh4Wq5tBbCRf4UUHDkC7w==@nongnu.org X-Gm-Message-State: AOJu0YxJ75635ycBTiqt10Q+d2jxYVOYyWaD0vG/dMIB1PQ/qhJpksTX pvuZadQI1LHn03QUWWygD6lubuksZ4EIEGm7GAxE+2LOiaQxxLqFkLtU2Q== X-Google-Smtp-Source: AGHT+IGwgM3gcD0dWNMCJXK9PxJFqQ0d+gB71Fgy3IqSVaEzcXGQNbMf/xNqVmmGUZNiyNIha9POPg== X-Received: by 2002:a05:6a21:999f:b0:1d4:f7b7:f20 with SMTP id adf61e73a8af0-1dba4232b33mr15011102637.21.1730679584183; Sun, 03 Nov 2024 16:19:44 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:43 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Richard Henderson Subject: [PULL 09/67] target/ppc: Fix VRMA to not check virtual page class key protection Date: Mon, 4 Nov 2024 10:17:58 +1000 Message-ID: <20241104001900.682660-10-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hash virtual real mode addressing is defined by the architecture to not perform virtual page class key protection checks. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/mmu-hash64.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 5e1983e334..c8c2f8910a 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -993,6 +993,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, int exec_prot, pp_prot, amr_prot, prot; int need_prot; hwaddr raddr; + bool vrma = false; /* * Note on LPCR usage: 970 uses HID4, but our special variant of @@ -1022,6 +1023,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, } } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ + vrma = true; slb = &vrma_slbe; if (build_vrma_slbe(cpu, slb) != 0) { /* Invalid VRMA setup, machine check */ @@ -1136,7 +1138,12 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte); pp_prot = ppc_hash64_pte_prot(mmu_idx, slb, pte); - amr_prot = ppc_hash64_amr_prot(cpu, pte); + if (vrma) { + /* VRMA does not check keys */ + amr_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + } else { + amr_prot = ppc_hash64_amr_prot(cpu, pte); + } prot = exec_prot & pp_prot & amr_prot; need_prot = check_prot_access_type(PAGE_RWX, access_type); From patchwork Mon Nov 4 00:17:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87EE6D11198 for ; Mon, 4 Nov 2024 00:22:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kp0-0007He-Al; Sun, 03 Nov 2024 19:19:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kox-0007Dc-Ow; Sun, 03 Nov 2024 19:19:51 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kow-0002J8-7a; Sun, 03 Nov 2024 19:19:51 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-720e94d36c8so635865b3a.1; Sun, 03 Nov 2024 16:19:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679588; x=1731284388; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J6g3+OIAh+PgGQYF5KfEAWhRtddu1l04lD2/5ytpiIU=; b=eMpcGYm0rBWie635C9dNeBPIISQ7zLqdushKQeY31HpWl3ftDZhWHLREeiMm3Nf+0g lKVD3XQpCagaWVDMW/ln5Pzj8WrJxRP7R7b+lw2VGz2HoRzfNBiBq0K0nVPyOnH8Jq6h /qxza2OgWvtuY80UHiJzmDNsHd6z7g6sx3j/BJv52kwGn4KddXs4ql/c66k+5zCNG+9r baR46Bp2b/BlWTo3fi99SAcxnLloKC9lLNVPbV+ngExgot03Y3QC0ZWobsyMhT9jrpX8 9cy/38UZ3Q0BKBDMaFXsKi2PBZAv8SbDvVqd1krom2ulp2p9Ye9Po+huMCB52zhqInKP P4zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679588; x=1731284388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J6g3+OIAh+PgGQYF5KfEAWhRtddu1l04lD2/5ytpiIU=; b=lLiZ1r6Dhn/a7tVzwmv1mmjhMEXPzQIqt8lwoRQeS1h4M/R2eBSQHm2rrn2zV4em25 DgD+LOaAWQqsGPYJ1/R8duvU+YEeDWTH2dHIZTgOUEbdHeE5m1Ze5ErHxj4gdu75FoCA Apvnrz/jRZBGNRhx+hpqPRz6FYsKT4jv0wRKyu4xLgERXyrspGu/Hag+mEE6h2Ivtn4L pBN0CMMnsqTwS8/yy7GiiCpBizZiCAgeiapxFirU9m81w2Txj7DOTIQ/uL+uLXECclb1 FI5yHDuEFqZmUv5nTcfQdGVsVcmawgyVh5kmjp3V7T8/A/Nfec36VVUDGJf2PpGNg1c1 oBWg== X-Forwarded-Encrypted: i=1; AJvYcCUFSp89Fbtjy7jdM4V+OnBHzDn7ninO6ygfpVlwR+6gwIVGG+nKJeQ6A5K9MJDjoUQCREDZGOYjgA==@nongnu.org, AJvYcCV9nxLJmcdwKrJnpbPvOzZCQ6DXYYbzVQMgduaa1mR850n9RQ4hsQQQjJRlZ5/whGcK4niQKUgOcUo/EYg=@nongnu.org X-Gm-Message-State: AOJu0YyNxPJf8jHKWCsWfgkhsdW1h0DG+S4OHMlW++7zAVKUuD4oOh7L CMqL9UNOGfNU38NsOJotWaQpsIFwbgPpcMUR8H2Q+REk9rxZtMpbui2Wqw== X-Google-Smtp-Source: AGHT+IEW4g0BjDK8+LUYHDNNgIMaUw8Y2VXNoJ507p2NlP9/6oCFG05PviGm/g1OFFMgy+ZTJj3kPg== X-Received: by 2002:a05:6a21:3296:b0:1db:d736:9429 with SMTP id adf61e73a8af0-1dbd736943amr3793070637.4.1730679587721; Sun, 03 Nov 2024 16:19:47 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:47 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, qemu-stable@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 10/67] ppc/pnv: ADU fix possible buffer overrun with invalid size Date: Mon, 4 Nov 2024 10:17:59 +1000 Message-ID: <20241104001900.682660-11-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The ADU LPC transfer-size field is 7 bits, but the supported sizes for LPC access via ADU appear to be 1, 2, 4, 8. The data buffer could overrun if firmware set an invalid size field, so add checks to reject them with a message. Cc: qemu-stable@nongnu.org Reported-by: Cédric Le Goater Resolves: Coverity CID 1558830 Fixes: 24bd283bccb33 ("ppc/pnv: Implement ADU access to LPC space") Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_adu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/ppc/pnv_adu.c b/hw/ppc/pnv_adu.c index 81b7d6e526..f636dedf79 100644 --- a/hw/ppc/pnv_adu.c +++ b/hw/ppc/pnv_adu.c @@ -116,6 +116,12 @@ static void pnv_adu_xscom_write(void *opaque, hwaddr addr, uint64_t val, uint32_t lpc_size = lpc_cmd_size(adu); uint64_t data = 0; + if (!is_power_of_2(lpc_size) || lpc_size > sizeof(data)) { + qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " + "size:%" PRId32 "\n", lpc_size); + break; + } + pnv_lpc_opb_read(adu->lpc, lpc_addr, (void *)&data, lpc_size); /* @@ -135,6 +141,12 @@ static void pnv_adu_xscom_write(void *opaque, hwaddr addr, uint64_t val, uint32_t lpc_size = lpc_cmd_size(adu); uint64_t data; + if (!is_power_of_2(lpc_size) || lpc_size > sizeof(data)) { + qemu_log_mask(LOG_GUEST_ERROR, "ADU: Unsupported LPC access " + "size:%" PRId32 "\n", lpc_size); + break; + } + data = cpu_to_be64(val) >> ((lpc_addr & 7) * 8); /* See above */ pnv_lpc_opb_write(adu->lpc, lpc_addr, (void *)&data, lpc_size); } From patchwork Mon Nov 4 00:18:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4348DD11198 for ; Mon, 4 Nov 2024 00:24:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kp2-0007Ke-9w; Sun, 03 Nov 2024 19:19:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kp0-0007Ip-HF; Sun, 03 Nov 2024 19:19:54 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7koy-0002Ji-TO; Sun, 03 Nov 2024 19:19:54 -0500 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-71e467c3996so3013871b3a.2; Sun, 03 Nov 2024 16:19:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679591; x=1731284391; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r8AvT/FnW3aX5+LIUAhqePEJ/QWevxFxm8Hw+y35nEs=; b=IEq1C9J3Ar2vDg/6/EPH7fu9nQ0ixl29ogpayZJhCPAD2ZmXs4723K8St1naRkJKbI PFlSXmVg+ehmduC8AuFNSUXKHcA94xaQnL+sPTYTy2GNY8g5jZ3Jyvi8Dq8pzJ5RJks2 WW0i61JuLlesrj9tEXfgBk4zD3iUSUwzQJq19KTrCG1W62cyxjdJ7h12LeIwa+8XopY+ /WeuUvAOk3BAlonFmRo9UFfAUv32AwauIYCOIfad0ePGylMdw+9HB64QN3HzxWEhS6S+ S0IJ53yAsvZo0++U2Ese1CqIrgF4V9LttcgUR/eH/IDxV4N3xksB1JhR8+Ce7fPbObTN c6iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679591; x=1731284391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8AvT/FnW3aX5+LIUAhqePEJ/QWevxFxm8Hw+y35nEs=; b=bDqwb7uHMhWt6I5G/aFGLTW7MaCmJow0jo5bKysehYgHqL2XPlnURKpMmS4uvn+45J /P7Bq1tjLxtdYkpiBTGu6z9ElC2PBDrb53OTV38zr3LVUa5Jyi41kXf4XJrrI4/nLGx2 q7vAV9ALRZIthq+eiXfcb0iRolX259SI+ScIcV8t0rpa+PRzg1YNTBfvC4HVkW55dm8h rM1Ai97DtMYysq95DG09Pc9WtoS7w8HwfEIym15dO18edZVOsnlLZPmBYqyU9cbuCCv8 FwB41FtMiq89P/iW1gLQqBYVaBrEDiP5X2eynMUe5tF8j0Dl+6jSoVKRYc27QH3g1gF1 ScqA== X-Forwarded-Encrypted: i=1; AJvYcCWlENpfzqO9b28ZZbtMNi5vgrw4xgC6PODracQPDHa3ogDmX8oeZGmuLmq3N+y4qjdPrzyjr1RKYA==@nongnu.org X-Gm-Message-State: AOJu0YyllIBWC9h5Pk0t2IaQIcQe4ohIPXUE+06pbWNKl/vjPgG5AWzO 4QKQ6cP6aPVt0nxcjLAcaBXL7rDsmonbui3v7PMnoo3FtVRQ39dhtUSufw== X-Google-Smtp-Source: AGHT+IFQSYNsZB2s0veQmbJmGelb6Jh6JBFQWQmm3zie2qMit4AoaOo1F5r8pbg2y/4QgykPIZ5CxA== X-Received: by 2002:a05:6a20:2d1f:b0:1d9:18af:d150 with SMTP id adf61e73a8af0-1d9a840a299mr42497310637.21.1730679590897; Sun, 03 Nov 2024 16:19:50 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:50 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PULL 11/67] MAINTAINERS: Cover PowerPC SPI model in PowerNV section Date: Mon, 4 Nov 2024 10:18:00 +1000 Message-ID: <20241104001900.682660-12-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé It is unfair to let the PowerNV SPI model to the SSI maintainers. Also include the PowerNV ones. Fixes: 29318db133 ("hw/ssi: Add SPI model") Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1e88b5738c..cf39ad4b7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1505,8 +1505,10 @@ F: hw/ppc/pnv* F: hw/intc/pnv* F: hw/intc/xics_pnv.c F: hw/pci-host/pnv* +F: hw/ssi/pnv_spi.c F: include/hw/ppc/pnv* F: include/hw/pci-host/pnv* +F: include/hw/ssi/pnv_spi* F: pc-bios/skiboot.lid F: tests/qtest/pnv* F: tests/functional/test_ppc64_powernv.py From patchwork Mon Nov 4 00:18:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C1FCD11198 for ; Mon, 4 Nov 2024 00:29:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kp7-0007Ns-6h; Sun, 03 Nov 2024 19:20:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kp5-0007Ms-5R; Sun, 03 Nov 2024 19:19:59 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kp3-0002KN-Oq; Sun, 03 Nov 2024 19:19:58 -0500 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-71e4244fdc6so2800537b3a.0; Sun, 03 Nov 2024 16:19:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679595; x=1731284395; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vP9Pv6akJ9wvw7JMuu+7UGFu2Y8Q3rLCweqIbGkYo8w=; b=F3mH+JPiETqE28cN7BS9xoA3Z6Djv5obgzYy5hvte1gyf2I5cG52yVpjaXkVz28p6a iYAf2/Da7O2f1CINPTpYnK2uWH8WAS9uV/VCfKgW1AeWA2V3pYgyn+TXXyKgghfSq+w7 zJzznobSzNyoCLgFSgWr/dEtD8b1wst9HgHM8L/J/bxZK8ZmXFvPEkbfQ0p3jhrzjb/L SLdb/OZHBsAL9SmM1z6IXEd56TZfy0nCIa0G6ANxHIHa94TDexlvTAliWPSPv+2n4Yyy vWJel5+9JplDtGKFKSiMUWUApSKPVE4it9P57PXrLexi2T/jjupeN6cEJb4GkUKFpV8i hvQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679595; x=1731284395; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vP9Pv6akJ9wvw7JMuu+7UGFu2Y8Q3rLCweqIbGkYo8w=; b=lh20I3GGuZuTNmP5DN6NQ1HnGLRXFWzY1UjhUe/L6AxEwPkiRpniEUNBwRbV/R+MlV iQFQ4BVo/a65UDhi9jNS1HAGUTs7pORufs06fePPjbFzH8VwY3w9310cBI8zDBODmW1B z1kMOAJgGMO2d0UJJmKJZ3b7Y0BU2DPeQ1cwTTIJ+YvtTWJAhexZ/kRyhmLBrYu1hZtq 1h42S1HfNHPTxoOSLFbZ56sNaMA0EjZ7JtEpoqw3tUbluYpjVi4ypF4Fp1lUWbA0X6uP Q95tGUoYwGIZqO9QJASbZMWoMJFd6jirWZETnwlo2KZqiX0EtRRlPNQvBZ0N3FDhCVv5 2hlA== X-Forwarded-Encrypted: i=1; AJvYcCUbSJlTudbu5AdlFOqvu6s92t1jeJ87INnKx117Qc1k+ZyGJUGeCs2TI1brGsuoVFA+y57+YkMGwWgZTOY=@nongnu.org, AJvYcCXBg3hEJnWyZVSEbqEZoLCzfZrdY2JO45RHIwwvstnAu1jccD941Pbt6TyNomHcKq4kmkBWwQ011w==@nongnu.org X-Gm-Message-State: AOJu0Ywj1FSFXr5DsXSMubTFDLqT7iauuJLbzPziv5ozxpTkfo3HG8yQ +Ss3JAXV3sUogGnRZVDRSkwInDN7TbgeAYzcg3v7GlrAWlNDDUIz+/nN6w== X-Google-Smtp-Source: AGHT+IHoskG9t740LaqJsduWGHY7u4himZXqnYPo8/hOXH3ClDh4aelVld8CREyNo5l5v3Lf/Y3ACQ== X-Received: by 2002:a05:6a21:670f:b0:1d9:266e:8216 with SMTP id adf61e73a8af0-1dba53bf472mr16052635637.22.1730679594691; Sun, 03 Nov 2024 16:19:54 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:54 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Richard Henderson Subject: [PULL 12/67] hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new() Date: Mon, 4 Nov 2024 10:18:01 +1000 Message-ID: <20241104001900.682660-13-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=npiggin@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé pnv_spi_xfer_buffer_new() allocates %payload using g_malloc0(), and pnv_spi_xfer_buffer_write_ptr() allocates %payload->data using g_realloc(). Use the API equivalent g_free() to release the buffers. Cc: qemu-stable@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- hw/ssi/pnv_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c index 9e7207bf7c..d15a5970b4 100644 --- a/hw/ssi/pnv_spi.c +++ b/hw/ssi/pnv_spi.c @@ -53,8 +53,8 @@ static PnvXferBuffer *pnv_spi_xfer_buffer_new(void) static void pnv_spi_xfer_buffer_free(PnvXferBuffer *payload) { - free(payload->data); - free(payload); + g_free(payload->data); + g_free(payload); } static uint8_t *pnv_spi_xfer_buffer_write_ptr(PnvXferBuffer *payload, From patchwork Mon Nov 4 00:18:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 518FAD11194 for ; Mon, 4 Nov 2024 00:21:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kp8-0007Pv-Ur; Sun, 03 Nov 2024 19:20:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kp7-0007Oq-M9; Sun, 03 Nov 2024 19:20:01 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kp6-0002Kt-B4; Sun, 03 Nov 2024 19:20:01 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-720c2db824eso3318139b3a.0; Sun, 03 Nov 2024 16:19:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679598; x=1731284398; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e0I9TDQdpQOkKI2wo1rQADwX0izZZzX4pvBbiiFX/Hg=; b=lrz6IIsI6AamTuWkD0epBhUl65hAHgeAmRTIj2FXkh8tR85HHsQvOjsnNn5dyjUFAP xTH2MgdsbrvRSuPXY2zbyEVsgyXJIls5RxO8N1Nf1MYUfeX6pEgebjPBvfgBqRohu/OU VHbi4b1ojR7iCO5mfFn1+hgC2+xwbz347atBcYcp9kkoDMLUsC+ToIC6V8h2V2YXgOhD lPbU1AmaQn/TBBlxHXJb6km3QfXks19CE4uHOMO+dNwBUq+hclC5NEXG+WilxHdNPFnB VwWdk9l2m8OmENJq8vC/B8vQvHcHrXThPwnZzpX2SKOaXJDnePB5hel9444Nl7cRWDzY DCqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679598; x=1731284398; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e0I9TDQdpQOkKI2wo1rQADwX0izZZzX4pvBbiiFX/Hg=; b=CPQd2o7YOF2K/6xz+WZOibv1JeYHRYd7jr5NAe7Uxop+ZRAgT4V9knw7tXPCkoGGGc hquQAdFheDT9mA6tycXIqikgjDwCsLsAdJLv3AHsVHYrXQVkgs7MRK8FCKJlhT7bBQ/D fblLA7BL11Xk6YzGLD3sJXiJkkcKZ9HpMwLiPcBWIBGQ9QVv6i39nBIXEzMyqNy9fpFd sGKW7EN/GzXXfMUr9jiGFJ7psrSopBwP3x6piQHxhUS8C9VMzaU1eXJp148Cl7swwuYY c3S6Tv8LkN8ZNOyUbh82Ijtg6Fttx1OKBL72DRfSts9UAywoEAv0+V3FAyzr6/isUI4N unLw== X-Forwarded-Encrypted: i=1; AJvYcCWL4iHkNOyO6gafHV1+QZysqli6JH+7tXr/vZn+TFFTyZ40m54bHYjhEPlvnQcQlWWq32AcGjFaNA==@nongnu.org, AJvYcCXKDi4GaaAG5g6e6YXHiFPwoYl7GdXqKBLTnyp91f5AS8/ZTRtPH+y+C17D9KyIy431peYcHVURjSAqR9U=@nongnu.org X-Gm-Message-State: AOJu0Yz03llt/OLKfO2Xjp2nIFTCY+ntX6jyNBxuOO2XSAO5P/AEqRJq US4nGFzx6nI07D7DV3uFDk3wRrILvc3uqQ7vS8qsK08RDse1QyFOIVeRBA== X-Google-Smtp-Source: AGHT+IHVy08vcndPptgZnO+iB9WVSK8wvvL2gvxOgXb0z+56gZGLg0p0ijxZmc/1BEFTv+EuXliawQ== X-Received: by 2002:a05:6a20:d48e:b0:1d9:ed47:3b52 with SMTP id adf61e73a8af0-1d9ed473c0cmr26597073637.8.1730679598137; Sun, 03 Nov 2024 16:19:58 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:19:57 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org Subject: [PULL 13/67] hw/ssi/pnv_spi: Return early in transfer() Date: Mon, 4 Nov 2024 10:18:02 +1000 Message-ID: <20241104001900.682660-14-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=npiggin@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Return early to simplify next commit. No logical change intended. Cc: qemu-stable@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- hw/ssi/pnv_spi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c index d15a5970b4..72bcc00de7 100644 --- a/hw/ssi/pnv_spi.c +++ b/hw/ssi/pnv_spi.c @@ -217,6 +217,9 @@ static void transfer(PnvSpi *s, PnvXferBuffer *payload) PnvXferBuffer *rsp_payload = NULL; rsp_payload = pnv_spi_xfer_buffer_new(); + if (!rsp_payload) { + return; + } for (int offset = 0; offset < payload->len; offset += s->transfer_len) { tx = 0; for (int i = 0; i < s->transfer_len; i++) { @@ -235,9 +238,7 @@ static void transfer(PnvSpi *s, PnvXferBuffer *payload) (rx >> (8 * (s->transfer_len - 1) - i * 8)) & 0xFF; } } - if (rsp_payload != NULL) { - spi_response(s, s->N1_bits, rsp_payload); - } + spi_response(s, s->N1_bits, rsp_payload); } static inline uint8_t get_seq_index(PnvSpi *s) From patchwork Mon Nov 4 00:18:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A5A2D11194 for ; Mon, 4 Nov 2024 00:21:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpD-0007Xg-1o; Sun, 03 Nov 2024 19:20:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpC-0007Wy-4G; Sun, 03 Nov 2024 19:20:06 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kpA-0002Sa-Jb; Sun, 03 Nov 2024 19:20:05 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-71e7086c231so3039068b3a.0; Sun, 03 Nov 2024 16:20:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679602; x=1731284402; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ph5Kd9QXTfnsJFYyLPHoftiyt4e7iSLYLRytO4VxqSY=; b=BhaUk8AoULzp+ejChfic5yEFgxlSt1hHg3+IOZBHriwf8WMm4TonlpQJs5x7DeQSgM YOKucsLx4DTQK90JTCgPxHn9byXh+H9dPpn4+hHLEzpig/SIOR0uGZXbx14aOw7I/sCc jiAuyqGNaAkB5x0cdd4ZUuSduzd+mplRAAJ8SHqpU5fxPclFaVzRctjoTHPmrH2O1r+J dikrLzBLL302BnG8IChStORGyuneO5c5CuY6CiEQaQUZ0B5uJfCHvRGaE3OhyxL1Dmrd hweNnYLCpn6pBFzUdohexHu57vN0kwov+ZPH3s3JkfTvr/2WxKHvDea8TrpwdQRvnxJo XMwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679602; x=1731284402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ph5Kd9QXTfnsJFYyLPHoftiyt4e7iSLYLRytO4VxqSY=; b=fvqc3LAExbzlj+xLsgJfBJ18cyjAMda0Uo40Mo0tZ6h8ERS5TBW01cbYu1P9bruRnr cJVwomRF290MzwT+5sQk9MI++Patoq51+OPI0r8NZubnp443ZeS8roJYCBbk2icy7vQ6 eUwKas/hWrhJ5MNxluVz0WQGJ0b0l2W8tTf0iRW0MVfb/1IUXjtLwZ1H7ThBEgmbIw+T hj90TbJRo4E6TgOeNlicgR7YaBDjPTv2zuFL9ix1stsNkbcyMfXcoBHuIr3rbutzhRo5 ABQyY1wpCwOV7xVJrPP8AG5yEqUPMBIuqm56z+5faky5ILB1R+dO4lLISRTVePsGDYlr DVlg== X-Forwarded-Encrypted: i=1; AJvYcCWYsCgXGqavrgwIUe7+/KUVABdxEMtI+vdN7vt8Tw9YoafGKBU598Ywxs50/SZmJdB3MT5SrEEfXw==@nongnu.org, AJvYcCXB19V70d3SNl7NuGiYVcCm1QmKBEkEhijRgAfCEwbPexSXq1c1P2kjdaiy1Djm2w7Gc2ilaHYc/yny6K8=@nongnu.org X-Gm-Message-State: AOJu0YzqKtyM7cn2JXDxY20Wka9k1ZfBGws0fMhgmQZcag+VF/m3x/LK KgXdxiZwKdAP2dA/oVrpY14LiIeYgttFUEVuTKvDghKxg/eEgi3GHIHKWw== X-Google-Smtp-Source: AGHT+IFq3yLWRUyEiP8bjW+5GFICSUqSU6tsKjtujyZ35zLB+jgd7wQVXnsjkvmFHFAnaGNyhtynZw== X-Received: by 2002:a17:902:d544:b0:20c:7181:51c7 with SMTP id d9443c01a7336-210c6c8ff93mr422093255ad.52.1730679602160; Sun, 03 Nov 2024 16:20:02 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.19.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:01 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Chalapathi V , qemu-stable@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 14/67] hw/ssi/pnv_spi: Fixes Coverity CID 1558831 Date: Mon, 4 Nov 2024 10:18:03 +1000 Message-ID: <20241104001900.682660-15-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Chalapathi V In this commit the following coverity scan defect has been fixed CID 1558831: Resource leaks (RESOURCE_LEAK) Variable "rsp_payload" going out of scope leaks the storage it points to. Cc: qemu-stable@nongnu.org Fixes: Coverity CID 1558831 Signed-off-by: Chalapathi V Fixes: b4cb930e40 ("hw/ssi: Extend SPI model") [PMD: Rebased on previous commit (returning earlier)] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- hw/ssi/pnv_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c index 72bcc00de7..c21b2ebb3c 100644 --- a/hw/ssi/pnv_spi.c +++ b/hw/ssi/pnv_spi.c @@ -239,6 +239,7 @@ static void transfer(PnvSpi *s, PnvXferBuffer *payload) } } spi_response(s, s->N1_bits, rsp_payload); + pnv_spi_xfer_buffer_free(rsp_payload); } static inline uint8_t get_seq_index(PnvSpi *s) From patchwork Mon Nov 4 00:18:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45F00D11194 for ; Mon, 4 Nov 2024 00:30:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpI-0007eo-UL; Sun, 03 Nov 2024 19:20:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpH-0007dO-1o; Sun, 03 Nov 2024 19:20:11 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kpF-0002Ye-2Y; Sun, 03 Nov 2024 19:20:10 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-7205b6f51f3so3037674b3a.1; Sun, 03 Nov 2024 16:20:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679606; x=1731284406; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=glt8LdjLrhqs+rwJ3qBJ40uDOCd/SYRFndsslvUj3Qo=; b=e7tUrF+Q52uvw7cMVEF5goTVOdowC3ZywFTpgdaIZfC/lkPUIN++YedE93rhNfJJNs NEqbAvxFJ4Oe2eGNwtJvDKC17Aszwx8XF7r19D6PI7ZoPJCMFZmA1hYXkSPhouY1LFOc 8jjqhxEd40pchyOB9z+FsJn1HiIE1RaKHIm+ARH20vh07KY4ZuPgCas/Is7TDNH104HI 68qY3sx3k3LhOqsio6Lu9NH+qll+2WhkyAR0Zxd5hDjLk+Wf6S9WRQ7AHXaKkjjwXtPr 22OAszDqG1C70SMVRDOwaUjC84Dcw4df1bZNEiEU2t584q5thvKf7PIgoXO+GhpiVxSw WPRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679606; x=1731284406; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=glt8LdjLrhqs+rwJ3qBJ40uDOCd/SYRFndsslvUj3Qo=; b=H0aFbNOPJpgfiTjxZRZgsfW/onnPBMdgqbHpiMc0QWmPk68acTEAAXvecTm6QZtuCf 27AqTug9v/7H+X3DAJQXu1XNk3zXyW1A6aAtjzAjniAVLMzJOwRD3gNj2Bs360romgn2 Wn6dsII1Ix6nzLfc/+eJHBKO2vZ9yoKjQmaWrTrnLIdpWeAnnEVyTKDzzrXVQ7Tvu1w4 VPMH1vF8Xp56oUxRh+WX58YtJXchWe7K6h3AIlHfJvX4Vc/Jn7dE1OCqpCrkRLxBBmvb si6PFtd3z0bYQg7oeZ5lrHKs2ilCv2FlgqzmnHeIbyPxGtjkav5NuXNY+PyNCuATymyJ o4IA== X-Forwarded-Encrypted: i=1; AJvYcCWcK0Rh9h4NbBdbuYPGqnPqX3pajVD4c+fwPBV4R7cGM3twgW+/TVFhZwhqOf1g6mk0IvZyLkW13Q==@nongnu.org, AJvYcCX06EVWI8mvvSmWHJAXydET/NqdLTHCi6k/+cTSzT4g5y2aBYi20iZ2bUHUWZ/UFNM+MOpJmPDOHHAeIsM=@nongnu.org X-Gm-Message-State: AOJu0Yw4em0iWPXmJUPiaJjtSXkTAWIlRj7lxgKA1zqMz8UfVPpc4JUA Tt9ZMp5sb9jkN3qSGXWrXg7Q5NYd4uRdxSJNeeVhhRG+Qut9HxYEmqNeCw== X-Google-Smtp-Source: AGHT+IHqBiSv3D12+d9LUbNDUkWhhS8Hs93BFr03tQIpSpdsTFcMYy2wjr6Zxmn9NlsTgi2dk1tUcg== X-Received: by 2002:a05:6a21:478b:b0:1d9:278a:9ab with SMTP id adf61e73a8af0-1dba54a619dmr19411176637.35.1730679606420; Sun, 03 Nov 2024 16:20:06 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:05 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Ilya Leoshkevich , qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= Subject: [PULL 15/67] tests/tcg: Replace -mpower8-vector with -mcpu=power8 Date: Mon, 4 Nov 2024 10:18:04 +1000 Message-ID: <20241104001900.682660-16-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ilya Leoshkevich [1] deprecated -mpower8-vector, resulting in: powerpc64-linux-gnu-gcc: warning: switch '-mpower8-vector' is no longer supported qemu/tests/tcg/ppc64/vsx_f2i_nan.c:4:15: error: expected ';' before 'float' 4 | typedef vector float vsx_float32_vec_t; | ^~~~~~ Use -mcpu=power8 instead. In order to properly verify that this works, one needs a big-endian (the minimum supported CPU for 64-bit little-endian is power8 anyway) GCC configured with --enable-checking (see GCC commit e154242724b0 ("[RS6000] Don't pass -many to the assembler"). [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109987 Cc: qemu-stable@nongnu.org Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Acked-by: Alex Bennée Signed-off-by: Nicholas Piggin --- tests/tcg/ppc64/Makefile.target | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target index 1940886c73..0d058b2600 100644 --- a/tests/tcg/ppc64/Makefile.target +++ b/tests/tcg/ppc64/Makefile.target @@ -6,7 +6,7 @@ VPATH += $(SRC_PATH)/tests/tcg/ppc64 config-cc.mak: Makefile $(quiet-@)( \ - $(call cc-option,-mpower8-vector, CROSS_CC_HAS_POWER8_VECTOR); \ + $(call cc-option,-mcpu=power8, CROSS_CC_HAS_CPU_POWER8); \ $(call cc-option,-mpower10, CROSS_CC_HAS_POWER10)) 3> config-cc.mak -include config-cc.mak @@ -23,15 +23,15 @@ run-threadcount: threadcount run-plugin-threadcount-with-%: $(call skip-test, $<, "BROKEN (flaky with clang) ") -ifneq ($(CROSS_CC_HAS_POWER8_VECTOR),) +ifneq ($(CROSS_CC_HAS_CPU_POWER8),) PPC64_TESTS=bcdsub non_signalling_xscv endif -$(PPC64_TESTS): CFLAGS += -mpower8-vector +$(PPC64_TESTS): CFLAGS += -mcpu=power8 -ifneq ($(CROSS_CC_HAS_POWER8_VECTOR),) +ifneq ($(CROSS_CC_HAS_CPU_POWER8),) PPC64_TESTS += vsx_f2i_nan endif -vsx_f2i_nan: CFLAGS += -mpower8-vector -I$(SRC_PATH)/include +vsx_f2i_nan: CFLAGS += -mcpu=power8 -I$(SRC_PATH)/include PPC64_TESTS += mtfsf PPC64_TESTS += mffsce From patchwork Mon Nov 4 00:18:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBEB9D11198 for ; Mon, 4 Nov 2024 00:25:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpK-0007fx-Vn; Sun, 03 Nov 2024 19:20:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpJ-0007fZ-HV; Sun, 03 Nov 2024 19:20:13 -0500 Received: from mail-il1-x12a.google.com ([2607:f8b0:4864:20::12a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kpI-0002ZD-3a; Sun, 03 Nov 2024 19:20:13 -0500 Received: by mail-il1-x12a.google.com with SMTP id e9e14a558f8ab-3a6af694220so9881845ab.1; Sun, 03 Nov 2024 16:20:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679610; x=1731284410; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dTPOuJL+gEDvzg99HYFtkObHP58qYB3o1L++xvixkVI=; b=akslZIp5P2K3gctEg5ZurbB5cBSIOfDzEtMUXZM0ZtuuswacZO6rKzkSiy3ETt/0Fz f+b7Az8LpG+WKENYWqVmViQo+7NDldnSDaf3o5CbdUbPyiImk2I/fYtD6OqQsFUemIoh ZdOynUbMOcGb26UKDFnbhsHCDUClYpGwM+30JnzyRR6bIIv13HbGUtsDRy1MlJ2d+3ih fgZsj9w90LUFN2A2bJJdSD+yElrrfAWYCSDl8HBL0lSAcQpGGIRrD9x3q7ilKj2mpE1x CctRbH/2LCnuDakDP2SkqEO/BsrGeg468gFsYCHNVim2D0lNrpbNaxzC2Scjbj0hoFNY n7Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679610; x=1731284410; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dTPOuJL+gEDvzg99HYFtkObHP58qYB3o1L++xvixkVI=; b=D1WWb9TihzLjLIuqhE4JZiZoXbKl9/14N0WyFX7fG+YtPl3zm8tlBtcT0kz7ahxrbq nm8eGuZhlbI4zPAuT6wziSnAHJwRwTrndte2PV/2vjcStQGlWh1oWof9+3oaPMdtsS38 olI/AYQ2NuvSdOaAegZj2u49k30ScnDA+CRfGw8O8432PjoDTFJ5yXzCfZftKU5KoP3e aznWnWQwEwPE9vwSMoozMpKuyoA+4sTU01S0Al370b6HY0Em9RFTIH/Og7ibcxTLMeqq m+R6fDQQVR2Sr0BoyLIDERdeH5D+e51o+9eDcW+gGAFYp4m9eJFW3NeOI6Ua/KBE60vn PHeQ== X-Forwarded-Encrypted: i=1; AJvYcCWUaeG3YfyfvTTGbfBKq09RKBqHjg2n014aFaXTNml/6iim+S0hHLCKoAomhoOY0evjwfFOws+N5g==@nongnu.org X-Gm-Message-State: AOJu0Yy2t2TkwqWqj1knW13jHYzLCFATvIPsww9CMKBF4s/msfb6nglI yXptOZRJaMK+F4VxjQ81rcgSy2y5ugxr3W/v9gaKSvb2F0U8oaymQ2oD4A== X-Google-Smtp-Source: AGHT+IEateCgHg4ilbu4YSkbnBLgK+EbtZ3L33Np7kbIZG6OAfQu3BBu4eeNV/ij7rzWNp1yeOjAAg== X-Received: by 2002:a92:ca4a:0:b0:3a0:9c20:8070 with SMTP id e9e14a558f8ab-3a6b03b0c7emr101783335ab.20.1730679610129; Sun, 03 Nov 2024 16:20:10 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:09 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, =?utf-8?q?Cl?= =?utf-8?q?=C3=A9ment_Chigot?= , =?utf-8?q?C=C3=A9dric_L?= =?utf-8?q?e_Goater?= Subject: [PULL 16/67] hw/ppc: fix decrementer with BookE timers Date: Mon, 4 Nov 2024 10:18:05 +1000 Message-ID: <20241104001900.682660-17-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12a; envelope-from=npiggin@gmail.com; helo=mail-il1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot The BookE decrementer stops at 0, meaning that it won't decremented towards "negative" values. However, the current logic is inverted: decr is updated solely when the resulting value would be negative. Signed-off-by: Clément Chigot Fixes: 8e0a5ac87800 ("hw/ppc: Avoid decrementer rounding errors") Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index fde4619412..b86b5847de 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -728,7 +728,9 @@ static inline int64_t __cpu_ppc_load_decr(CPUPPCState *env, int64_t now, int64_t decr; n = ns_to_tb(tb_env->decr_freq, now); - if (next > n && tb_env->flags & PPC_TIMER_BOOKE) { + + /* BookE timers stop when reaching 0. */ + if (next < n && tb_env->flags & PPC_TIMER_BOOKE) { decr = 0; } else { decr = next - n; From patchwork Mon Nov 4 00:18:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B1D6D11194 for ; Mon, 4 Nov 2024 00:29:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpP-0007pM-Or; Sun, 03 Nov 2024 19:20:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpN-0007ig-DK; Sun, 03 Nov 2024 19:20:17 -0500 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kpL-0002Zr-VL; Sun, 03 Nov 2024 19:20:17 -0500 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-3e600add5dcso1564002b6e.2; Sun, 03 Nov 2024 16:20:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679614; x=1731284414; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I5sPzbUGgSsU4x2ABl9K5sldSfgeOH1YuMonG4CNaHQ=; b=DuJnHZK3JELeRsWnIFALa5Hd+g5mghPsf3HuXRdo7SLccx8mQLu+dhW0F+/Ux6bB0T k/fd4GBQ0YHacz1qHplbqTD40EJaTUGncKP9faKjk5LoedffHIfWPhvr3UwqdexhFEV3 ZdUqE8yapoSn6I1wOlD08Ci6SxoJznHnmds6qb5kj7ZdDzudZYeJaUazWOPVhxNPH0HR pliT/vVcEh3VCgQqYIHdpxGce804pRhn5crO+W4iDZ0W+6KakcPceJSAfdAPYQJoOeUL wwx4aFmMY36xMGIXp071YYJ1W49jUjupiBRCHhYS/+XT+/ASTRAc9eZs5GHGk4nv1hwb SMIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679614; x=1731284414; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I5sPzbUGgSsU4x2ABl9K5sldSfgeOH1YuMonG4CNaHQ=; b=Ck+iAzOOIU7c8D3vPAK5k4bGk9+TVI+YG6mpwQbifIAHotbaHch8OtBz3hACnesjxc a6OPlD6Zp5yvfDTPd4cyrftdrT0Wv+BMgvT/GBWB6k07nEuGf+a8o74IIvb22Sl4faqF SWnlZhv4yct4u1TtZWattmnYGwrCT3+xsN4sTDReFls4c7uF+GUXoHBLQOSPiEnFD4rx vh12rXN6a9qrSHZ9ByKJ4D6+q/Uj9W/M94kHaTVdsWWAwf81Xuo4L/TaLDLjvUirzesg xTMPiVYndiV3IB9bB7MD8GcIDXhH4ciLUzQoi2w/UUfz8/0SVtCmo4waMlWOxj1Wwr5N HnMg== X-Forwarded-Encrypted: i=1; AJvYcCV1FpfHs3gz2ft3FLBevamr+P9lQqWDoG3wi9vsfxN5jZs0G0XALfkWuE6LT1PSIBCnrz5jjLC+2g==@nongnu.org X-Gm-Message-State: AOJu0Yz59jigthWszd2PF+bkLuT8TThq6BSS3xMVLF2/3dc7d1wPFL13 kYoeDntAvO0nM15yhruspO0xCt3e0nEbL0d8ES1uwQpdSs2j5bEtWLf1gA== X-Google-Smtp-Source: AGHT+IH87p294n2CcfhzwQlusQ1FEG2uTgbaXNTUeEZXavl/i6ZNpysioGZhmsFqgSU7Ozel3yqTSQ== X-Received: by 2002:a05:6808:2e8b:b0:3e6:ccc:2d91 with SMTP id 5614622812f47-3e758c9d90amr9372381b6e.29.1730679613649; Sun, 03 Nov 2024 16:20:13 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:13 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 17/67] ppc/spapr: remove deprecated machine pseries-2.1 Date: Mon, 4 Nov 2024 10:18:06 +1000 Message-ID: <20241104001900.682660-18-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=npiggin@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.1 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/core/machine.c | 11 ----------- hw/ppc/spapr.c | 11 ----------- include/hw/boards.h | 3 --- 3 files changed, 25 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index adaba17eba..a41d1dbe26 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -297,17 +297,6 @@ const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); GlobalProperty hw_compat_2_2[] = {}; const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); -GlobalProperty hw_compat_2_1[] = { - { "intel-hda", "old_msi_addr", "on" }, - { "VGA", "qemu-extended-regs", "off" }, - { "secondary-vga", "qemu-extended-regs", "off" }, - { "virtio-scsi-pci", "any_layout", "off" }, - { "usb-mouse", "usb_version", "1" }, - { "usb-kbd", "usb_version", "1" }, - { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, -}; -const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); - MachineState *current_machine; static char *machine_get_kernel(Object *obj, Error **errp) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 2c10a70a48..e9518ff8b3 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5381,17 +5381,6 @@ static void spapr_machine_2_2_class_options(MachineClass *mc) } DEFINE_SPAPR_MACHINE(2, 2); -/* - * pseries-2.1 - */ - -static void spapr_machine_2_1_class_options(MachineClass *mc) -{ - spapr_machine_2_2_class_options(mc); - compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); -} -DEFINE_SPAPR_MACHINE(2, 1); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/include/hw/boards.h b/include/hw/boards.h index 5966069baa..44d19e1ffc 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -828,7 +828,4 @@ extern const size_t hw_compat_2_3_len; extern GlobalProperty hw_compat_2_2[]; extern const size_t hw_compat_2_2_len; -extern GlobalProperty hw_compat_2_1[]; -extern const size_t hw_compat_2_1_len; - #endif From patchwork Mon Nov 4 00:18:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39906D11198 for ; Mon, 4 Nov 2024 00:22:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpi-000830-Tt; Sun, 03 Nov 2024 19:20:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpR-0007qV-30; Sun, 03 Nov 2024 19:20:22 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kpP-0002at-Cp; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:16 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 18/67] ppc/spapr: remove deprecated machine pseries-2.2 Date: Mon, 4 Nov 2024 10:18:07 +1000 Message-ID: <20241104001900.682660-19-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.2 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/core/machine.c | 3 --- hw/ppc/spapr.c | 17 ----------------- include/hw/boards.h | 3 --- 3 files changed, 23 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index a41d1dbe26..2bbfcd1ede 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -294,9 +294,6 @@ GlobalProperty hw_compat_2_3[] = { }; const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); -GlobalProperty hw_compat_2_2[] = {}; -const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); - MachineState *current_machine; static char *machine_get_kernel(Object *obj, Error **errp) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e9518ff8b3..34d655d0b3 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5364,23 +5364,6 @@ static void spapr_machine_2_3_class_options(MachineClass *mc) } DEFINE_SPAPR_MACHINE(2, 3); -/* - * pseries-2.2 - */ - -static void spapr_machine_2_2_class_options(MachineClass *mc) -{ - static GlobalProperty compat[] = { - { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, - }; - - spapr_machine_2_3_class_options(mc); - compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); - mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; -} -DEFINE_SPAPR_MACHINE(2, 2); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/include/hw/boards.h b/include/hw/boards.h index 44d19e1ffc..7e849bb30d 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -825,7 +825,4 @@ extern const size_t hw_compat_2_4_len; extern GlobalProperty hw_compat_2_3[]; extern const size_t hw_compat_2_3_len; -extern GlobalProperty hw_compat_2_2[]; -extern const size_t hw_compat_2_2_len; - #endif From patchwork Mon Nov 4 00:18:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D21FD11194 for ; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:20 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 19/67] ppc/spapr: remove deprecated machine pseries-2.3 Date: Mon, 4 Nov 2024 10:18:08 +1000 Message-ID: <20241104001900.682660-20-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.3 specific code with this patch for now. While at it, also remove the dynamic-reconfiguration option which was introduced to disable it by default for legacy machines until pseries-2.3. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/core/machine.c | 13 ------------- hw/ppc/spapr.c | 15 --------------- hw/ppc/spapr_pci.c | 35 ----------------------------------- include/hw/boards.h | 3 --- include/hw/pci-host/spapr.h | 1 - 5 files changed, 67 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 2bbfcd1ede..0f10b4f992 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -281,19 +281,6 @@ GlobalProperty hw_compat_2_4[] = { }; const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); -GlobalProperty hw_compat_2_3[] = { - { "virtio-blk-pci", "any_layout", "off" }, - { "virtio-balloon-pci", "any_layout", "off" }, - { "virtio-serial-pci", "any_layout", "off" }, - { "virtio-9p-pci", "any_layout", "off" }, - { "virtio-rng-pci", "any_layout", "off" }, - { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, - { "migration", "send-configuration", "off" }, - { "migration", "send-section-footer", "off" }, - { "migration", "store-global-state", "off" }, -}; -const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); - MachineState *current_machine; static char *machine_get_kernel(Object *obj, Error **errp) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 34d655d0b3..599a59910c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5349,21 +5349,6 @@ static void spapr_machine_2_4_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 4); -/* - * pseries-2.3 - */ - -static void spapr_machine_2_3_class_options(MachineClass *mc) -{ - static GlobalProperty compat[] = { - { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, - }; - spapr_machine_2_4_class_options(mc); - compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); -} -DEFINE_SPAPR_MACHINE(2, 3); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 5c0024bef9..8f1964ce52 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1237,10 +1237,6 @@ static void add_drcs(SpaprPhbState *phb, PCIBus *bus) int i; uint8_t chassis; - if (!phb->dr_enabled) { - return; - } - chassis = chassis_from_bus(bus); if (pci_bus_is_root(bus)) { @@ -1260,10 +1256,6 @@ static void remove_drcs(SpaprPhbState *phb, PCIBus *bus) int i; uint8_t chassis; - if (!phb->dr_enabled) { - return; - } - chassis = chassis_from_bus(bus); for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { @@ -1548,17 +1540,6 @@ static void spapr_pci_pre_plug(HotplugHandler *plug_handler, PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); uint32_t slotnr = PCI_SLOT(pdev->devfn); - if (!phb->dr_enabled) { - /* if this is a hotplug operation initiated by the user - * we need to let them know it's not enabled - */ - if (plugged_dev->hotplugged) { - error_setg(errp, "Bus '%s' does not support hotplugging", - phb->parent_obj.bus->qbus.name); - return; - } - } - if (IS_PCI_BRIDGE(plugged_dev)) { if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) { return; @@ -1591,14 +1572,6 @@ static void spapr_pci_plug(HotplugHandler *plug_handler, SpaprDrc *drc = drc_from_dev(phb, pdev); uint32_t slotnr = PCI_SLOT(pdev->devfn); - /* - * If DR is disabled we don't need to do anything in the case of - * hotplug or coldplug callbacks. - */ - if (!phb->dr_enabled) { - return; - } - g_assert(drc); if (IS_PCI_BRIDGE(plugged_dev)) { @@ -1673,12 +1646,6 @@ static void spapr_pci_unplug_request(HotplugHandler *plug_handler, PCIDevice *pdev = PCI_DEVICE(plugged_dev); SpaprDrc *drc = drc_from_dev(phb, pdev); - if (!phb->dr_enabled) { - error_setg(errp, "Bus '%s' does not support hotplugging", - phb->parent_obj.bus->qbus.name); - return; - } - g_assert(drc); g_assert(drc->dev == plugged_dev); @@ -2089,8 +2056,6 @@ static Property spapr_phb_properties[] = { SPAPR_PCI_MEM64_WIN_SIZE), DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, SPAPR_PCI_IO_WIN_SIZE), - DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, - true), /* Default DMA window is 0..1GB */ DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), diff --git a/include/hw/boards.h b/include/hw/boards.h index 7e849bb30d..eea592b720 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -822,7 +822,4 @@ extern const size_t hw_compat_2_5_len; extern GlobalProperty hw_compat_2_4[]; extern const size_t hw_compat_2_4_len; -extern GlobalProperty hw_compat_2_3[]; -extern const size_t hw_compat_2_3_len; - #endif diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 3778aac27b..79187e80fd 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -53,7 +53,6 @@ struct SpaprPhbState { uint32_t index; uint64_t buid; char *dtbusname; - bool dr_enabled; MemoryRegion memspace, iospace; hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size; From patchwork Mon Nov 4 00:18:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03313D11194 for ; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:23 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 20/67] ppc/spapr: remove deprecated machine pseries-2.4 Date: Mon, 4 Nov 2024 10:18:09 +1000 Message-ID: <20241104001900.682660-21-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.4 specific code with this patch for now. While at it, also remove SpaprMachineClass::dr_lmb_enabled which is now turned useless. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 38 ++++---------------------------------- include/hw/ppc/spapr.h | 1 - 2 files changed, 4 insertions(+), 35 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 599a59910c..4d7705c89f 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -682,7 +682,6 @@ static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) { MachineState *machine = MACHINE(spapr); - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); hwaddr mem_start, node_size; int i, nb_nodes = machine->numa_state->num_nodes; NodeInfo *nodes = machine->numa_state->nodes; @@ -724,7 +723,6 @@ static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { int ret; - g_assert(smc->dr_lmb_enabled); ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); if (ret) { return ret; @@ -1307,9 +1305,7 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) spapr_dt_cpus(fdt, spapr); /* ibm,drc-indexes and friends */ - if (smc->dr_lmb_enabled) { - root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; - } + root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; if (smc->dr_phb_enabled) { root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; } @@ -2929,10 +2925,8 @@ static void spapr_machine_init(MachineState *machine) spapr->ov5 = spapr_ovec_new(); spapr->ov5_cas = spapr_ovec_new(); - if (smc->dr_lmb_enabled) { - spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); - spapr_validate_node_memory(machine, &error_fatal); - } + spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); + spapr_validate_node_memory(machine, &error_fatal); spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); @@ -3016,9 +3010,7 @@ static void spapr_machine_init(MachineState *machine) machine_memory_devices_init(machine, device_mem_base, device_mem_size); } - if (smc->dr_lmb_enabled) { - spapr_create_lmb_dr_connectors(spapr); - } + spapr_create_lmb_dr_connectors(spapr); if (mc->nvdimm_supported) { spapr_create_nvdimm_dr_connectors(spapr); @@ -3662,7 +3654,6 @@ static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { - const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); PCDIMMDevice *dimm = PC_DIMM(dev); @@ -3671,11 +3662,6 @@ static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Object *memdev; hwaddr pagesize; - if (!smc->dr_lmb_enabled) { - error_setg(errp, "Memory hotplug not supported for this machine"); - return; - } - size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); if (local_err) { error_propagate(errp, local_err); @@ -4713,7 +4699,6 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) hc->unplug_request = spapr_machine_device_unplug_request; hc->unplug = spapr_machine_device_unplug; - smc->dr_lmb_enabled = true; smc->update_dt_enabled = true; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); mc->has_hotpluggable_cpus = true; @@ -5334,21 +5319,6 @@ static void spapr_machine_2_5_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 5); -/* - * pseries-2.4 - */ - -static void spapr_machine_2_4_class_options(MachineClass *mc) -{ - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - - spapr_machine_2_5_class_options(mc); - smc->dr_lmb_enabled = false; - compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); -} - -DEFINE_SPAPR_MACHINE(2, 4); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index f6de3e9972..1821ef96c7 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -141,7 +141,6 @@ struct SpaprMachineClass { MachineClass parent_class; /*< public >*/ - bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ From patchwork Mon Nov 4 00:18:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51748D11198 for ; Mon, 4 Nov 2024 00:23:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpm-0008Je-Um; Sun, 03 Nov 2024 19:20:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpb-0007up-LR; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:27 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 21/67] ppc/spapr: remove deprecated machine pseries-2.5 Date: Mon, 4 Nov 2024 10:18:10 +1000 Message-ID: <20241104001900.682660-22-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.5 specific code with this patch for now. Also drop sPAPRMachineClass::use_ohci_by_default which is now useless. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 25 +------------------------ include/hw/ppc/spapr.h | 1 - 2 files changed, 1 insertion(+), 25 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 4d7705c89f..f63843d107 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3070,11 +3070,7 @@ static void spapr_machine_init(MachineState *machine) } if (machine->usb) { - if (smc->use_ohci_by_default) { - pci_create_simple(phb->bus, -1, "pci-ohci"); - } else { - pci_create_simple(phb->bus, -1, "nec-usb-xhci"); - } + pci_create_simple(phb->bus, -1, "nec-usb-xhci"); if (has_vga) { USBBus *usb_bus; @@ -5300,25 +5296,6 @@ static void spapr_machine_2_6_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 6); -/* - * pseries-2.5 - */ - -static void spapr_machine_2_5_class_options(MachineClass *mc) -{ - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - static GlobalProperty compat[] = { - { "spapr-vlan", "use-rx-buffer-pools", "off" }, - }; - - spapr_machine_2_6_class_options(mc); - smc->use_ohci_by_default = true; - compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); -} - -DEFINE_SPAPR_MACHINE(2, 5); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 1821ef96c7..6e9e62386c 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -143,7 +143,6 @@ struct SpaprMachineClass { /*< public >*/ bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ - bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ bool pre_2_10_has_unused_icps; bool legacy_irq_allocation; uint32_t nr_xirqs; From patchwork Mon Nov 4 00:18:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3AC36D11194 for ; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:31 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 22/67] ppc/spapr: remove deprecated machine pseries-2.6 Date: Mon, 4 Nov 2024 10:18:11 +1000 Message-ID: <20241104001900.682660-23-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.6 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f63843d107..a9c988b8f6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5278,24 +5278,6 @@ static void spapr_machine_2_7_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 7); -/* - * pseries-2.6 - */ - -static void spapr_machine_2_6_class_options(MachineClass *mc) -{ - static GlobalProperty compat[] = { - { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, - }; - - spapr_machine_2_7_class_options(mc); - mc->has_hotpluggable_cpus = false; - compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); -} - -DEFINE_SPAPR_MACHINE(2, 6); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); From patchwork Mon Nov 4 00:18:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2A23D11199 for ; Mon, 4 Nov 2024 00:31:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpn-0008NJ-Vn; Sun, 03 Nov 2024 19:20:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpj-00089n-Rr; Sun, 03 Nov 2024 19:20:40 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kph-0002cV-O1; Sun, 03 Nov 2024 19:20:39 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-720d5ada03cso2293012b3a.1; Sun, 03 Nov 2024 16:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679636; x=1731284436; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QBKDzu5wBBXzzjomyXMxfzAHh16pPVgxXwJrDHlU3Ok=; b=K5Cq4WCC7d18FL9z8TtH11PGLLJaMdsaim3wxBN2D7wvpSj73omfu7ml4YK2XFxG/o 6xaj6UU+Cdcahm85+1DKAEh/cBTNkDsgabjhQsFZmX++7lLgyxQdziPoFFTjmzgXDpds 6A67otbcvnpmfHHh/6UYYAWlcbJNAAzjH/mEyuRuuk8+TPnPlsSUJIv4ElN4L5dl9+2h YKQu0YTHBnxE8w/c2YrjKIxsZFKWJ0DPwPwGKqSejaY6TNvUKCYV82VhHgl6+fDJLWDl jxt4GuL8rKcQiBFIAeuk1gPmHWoM06hwvJxJnsBFZrMTjc2T1x7H1ulfxGlFEckNxlji h+iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679636; x=1731284436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QBKDzu5wBBXzzjomyXMxfzAHh16pPVgxXwJrDHlU3Ok=; b=sDt9muFEZy7Nxrpo1WxyRjAFAtZhFkn+1csjgBtcqBgeVD8Cs2zGHjU7obAGxVJSH6 JHgTfILL/ZrLd/1OpzIJ6xYsMwrfam2wBDqefFwEYMHyIHU98xLT9KiN5UlPhEEoOSqv itAaTpJwoqd+zwKajM2gepBYx77glDvOFkEEYj4sundTZA4c9tw+14cYiIFhdC2kQl0j c3OYJ/Qqpd894fwGCkoTeYE7N/zGewlvG17UNSA7tCGa5kMS+MCXtPqkfP8fKfuoXgd7 DJwJDYPRkf08VnIDhpAlepfcODx3sFyKTwVm0xWl+XNypBuJc4uzjs6EngaQr+kHlu7P hTaQ== X-Forwarded-Encrypted: i=1; AJvYcCUz+YmBEyC+QtWyaqea+XQZZVvfByfr+HT2IAa+zhChGdRQew+K2kuXoUgri0Y/Uhz8EqFRoxmmQg==@nongnu.org X-Gm-Message-State: AOJu0YwcJw+9i0Cif4dKmaG5nzYKrSmAp7K8TcwJ1a4s1pJN6AkSpUnb TGzYF5/fphb81jDIgUePLHFnShaAVashidyBFFtQrNgJICyqyQFlhROgMg== X-Google-Smtp-Source: AGHT+IEWx7Joryz5xYGwO6gX15/0MeF13f/n1VidfiRjkrXgvXhOXvpKXiyIe3uryht+lKUHEONvOA== X-Received: by 2002:a05:6a00:3d56:b0:71e:5d1d:1aaf with SMTP id d2e1a72fcca58-720b9de1421mr21968644b3a.23.1730679635565; Sun, 03 Nov 2024 16:20:35 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:35 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 23/67] ppc/spapr: remove deprecated machine pseries-2.7 Date: Mon, 4 Nov 2024 10:18:12 +1000 Message-ID: <20241104001900.682660-24-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=npiggin@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.7 specific code with this patch for now. While at it, also remove pre-2.8-migration and pci/mmio hacks introduced for backward compatibility. Suggested-by: Cédric Le Goater Acked-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 75 ------------------------------------- hw/ppc/spapr_pci.c | 57 ++++------------------------ include/hw/pci-host/spapr.h | 4 -- target/ppc/cpu.h | 5 --- target/ppc/cpu_init.c | 1 - target/ppc/machine.c | 52 ------------------------- 6 files changed, 7 insertions(+), 187 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a9c988b8f6..c89ab89b97 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5203,81 +5203,6 @@ static void spapr_machine_2_8_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 8); -/* - * pseries-2.7 - */ - -static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, - uint64_t *buid, hwaddr *pio, - hwaddr *mmio32, hwaddr *mmio64, - unsigned n_dma, uint32_t *liobns, Error **errp) -{ - /* Legacy PHB placement for pseries-2.7 and earlier machine types */ - const uint64_t base_buid = 0x800000020000000ULL; - const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ - const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ - const hwaddr pio_offset = 0x80000000; /* 2 GiB */ - const uint32_t max_index = 255; - const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ - - uint64_t ram_top = MACHINE(spapr)->ram_size; - hwaddr phb0_base, phb_base; - int i; - - /* Do we have device memory? */ - if (MACHINE(spapr)->device_memory) { - /* Can't just use maxram_size, because there may be an - * alignment gap between normal and device memory regions - */ - ram_top = MACHINE(spapr)->device_memory->base + - memory_region_size(&MACHINE(spapr)->device_memory->mr); - } - - phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); - - if (index > max_index) { - error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", - max_index); - return false; - } - - *buid = base_buid + index; - for (i = 0; i < n_dma; ++i) { - liobns[i] = SPAPR_PCI_LIOBN(index, i); - } - - phb_base = phb0_base + index * phb_spacing; - *pio = phb_base + pio_offset; - *mmio32 = phb_base + mmio_offset; - /* - * We don't set the 64-bit MMIO window, relying on the PHB's - * fallback behaviour of automatically splitting a large "32-bit" - * window into contiguous 32-bit and 64-bit windows - */ - - return true; -} - -static void spapr_machine_2_7_class_options(MachineClass *mc) -{ - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - static GlobalProperty compat[] = { - { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, - { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, - { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, - { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, - }; - - spapr_machine_2_8_class_options(mc); - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); - mc->default_machine_opts = "modern-hotplug-events=off"; - compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); - smc->phb_placement = phb_placement_2_7; -} - -DEFINE_SPAPR_MACHINE(2, 7); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 8f1964ce52..7e24084673 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1814,30 +1814,15 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp) assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ - if (sphb->mem64_win_size != 0) { - if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { - error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx - " (max 2 GiB)", sphb->mem_win_size); - return; - } - - /* 64-bit window defaults to identity mapping */ - sphb->mem64_win_pciaddr = sphb->mem64_win_addr; - } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { - /* - * For compatibility with old configuration, if no 64-bit MMIO - * window is specified, but the ordinary (32-bit) memory - * window is specified as > 2GiB, we treat it as a 2GiB 32-bit - * window, with a 64-bit MMIO window following on immediately - * afterwards - */ - sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; - sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; - sphb->mem64_win_pciaddr = - SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; - sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; + if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { + error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx + " (max 2 GiB)", sphb->mem_win_size); + return; } + /* 64-bit window defaults to identity mapping */ + sphb->mem64_win_pciaddr = sphb->mem64_win_addr; + if (spapr_pci_find_phb(spapr, sphb->buid)) { SpaprPhbState *s; @@ -2066,8 +2051,6 @@ static Property spapr_phb_properties[] = { (1ULL << 12) | (1ULL << 16) | (1ULL << 21) | (1ULL << 24)), DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), - DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, - pre_2_8_migration, false), DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, pcie_ecs, true), DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState, @@ -2105,20 +2088,6 @@ static int spapr_pci_pre_save(void *opaque) gpointer key, value; int i; - if (sphb->pre_2_8_migration) { - sphb->mig_liobn = sphb->dma_liobn[0]; - sphb->mig_mem_win_addr = sphb->mem_win_addr; - sphb->mig_mem_win_size = sphb->mem_win_size; - sphb->mig_io_win_addr = sphb->io_win_addr; - sphb->mig_io_win_size = sphb->io_win_size; - - if ((sphb->mem64_win_size != 0) - && (sphb->mem64_win_addr - == (sphb->mem_win_addr + sphb->mem_win_size))) { - sphb->mig_mem_win_size += sphb->mem64_win_size; - } - } - g_free(sphb->msi_devs); sphb->msi_devs = NULL; sphb->msi_devs_num = g_hash_table_size(sphb->msi); @@ -2165,13 +2134,6 @@ static int spapr_pci_post_load(void *opaque, int version_id) return 0; } -static bool pre_2_8_migration(void *opaque, int version_id) -{ - SpaprPhbState *sphb = opaque; - - return sphb->pre_2_8_migration; -} - static const VMStateDescription vmstate_spapr_pci = { .name = "spapr_pci", .version_id = 2, @@ -2181,11 +2143,6 @@ static const VMStateDescription vmstate_spapr_pci = { .post_load = spapr_pci_post_load, .fields = (const VMStateField[]) { VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), - VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), - VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), - VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), - VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), - VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, vmstate_spapr_pci_lsi, SpaprPciLsi), VMSTATE_INT32(msi_devs_num, SpaprPhbState), diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 79187e80fd..0db87f1281 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -83,10 +83,6 @@ struct SpaprPhbState { bool pcie_ecs; /* Allow access to PCIe extended config space? */ /* Fields for migration compatibility hacks */ - bool pre_2_8_migration; - uint32_t mig_liobn; - hwaddr mig_mem_win_addr, mig_mem_win_size; - hwaddr mig_io_win_addr, mig_io_win_size; bool pre_5_1_assoc; }; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f7a2da2bbe..30dba050f6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1457,11 +1457,6 @@ struct ArchCPU { opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; /* Fields related to migration compatibility hacks */ - bool pre_2_8_migration; - target_ulong mig_msr_mask; - uint64_t mig_insns_flags; - uint64_t mig_insns_flags2; - uint32_t mig_nb_BATs; bool pre_2_10_migration; bool pre_3_0_migration; int32_t mig_slb_nr; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23881d09e9..7768392986 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7452,7 +7452,6 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) } static Property ppc_cpu_properties[] = { - DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, false), DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, diff --git a/target/ppc/machine.c b/target/ppc/machine.c index d433fd45fc..21bed7c7c8 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -118,13 +118,6 @@ static const VMStateInfo vmstate_info_vsr = { #define VMSTATE_VSR_ARRAY(_f, _s, _n) \ VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) -static bool cpu_pre_2_8_migration(void *opaque, int version_id) -{ - PowerPCCPU *cpu = opaque; - - return cpu->pre_2_8_migration; -} - #if defined(TARGET_PPC64) static bool cpu_pre_3_0_migration(void *opaque, int version_id) { @@ -139,22 +132,6 @@ static int cpu_pre_save(void *opaque) PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; int i; - uint64_t insns_compat_mask = - PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB - | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES - | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES - | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT - | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ - | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC - | PPC_64B | PPC_64BX | PPC_ALTIVEC - | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; - uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX - | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 - | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 - | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 - | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 - | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM - | PPC2_MEM_LWSYNC; env->spr[SPR_LR] = env->lr; env->spr[SPR_CTR] = env->ctr; @@ -177,29 +154,6 @@ static int cpu_pre_save(void *opaque) env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4]; } - /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ - if (cpu->pre_2_8_migration) { - /* - * Mask out bits that got added to msr_mask since the versions - * which stupidly included it in the migration stream. - */ - target_ulong metamask = 0 -#if defined(TARGET_PPC64) - | (1ULL << MSR_TS0) - | (1ULL << MSR_TS1) -#endif - ; - cpu->mig_msr_mask = env->msr_mask & ~metamask; - cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; - /* - * CPU models supported by old machines all have - * PPC_MEM_TLBIE, so we set it unconditionally to allow - * backward migration from a POWER9 host to a POWER8 host. - */ - cpu->mig_insns_flags |= PPC_MEM_TLBIE; - cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; - cpu->mig_nb_BATs = env->nb_BATs; - } if (cpu->pre_3_0_migration) { if (cpu->hash64_opts) { cpu->mig_slb_nr = cpu->hash64_opts->slb_size; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:39 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 24/67] ppc/spapr: remove deprecated machine pseries-2.8 Date: Mon, 4 Nov 2024 10:18:13 +1000 Message-ID: <20241104001900.682660-25-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.8 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c89ab89b97..93decfcbeb 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5185,24 +5185,6 @@ static void spapr_machine_2_9_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 9); -/* - * pseries-2.8 - */ - -static void spapr_machine_2_8_class_options(MachineClass *mc) -{ - static GlobalProperty compat[] = { - { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, - }; - - spapr_machine_2_9_class_options(mc); - compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); - mc->numa_mem_align_shift = 23; -} - -DEFINE_SPAPR_MACHINE(2, 8); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); From patchwork Mon Nov 4 00:18:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 023F4D11194 for ; Mon, 4 Nov 2024 00:21:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kpu-0000Ly-Ef; Sun, 03 Nov 2024 19:20:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kps-00007t-4R; Sun, 03 Nov 2024 19:20:48 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kpq-0002dO-3f; Sun, 03 Nov 2024 19:20:47 -0500 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-71e953f4e7cso2804492b3a.3; Sun, 03 Nov 2024 16:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679644; x=1731284444; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3YC4UNbx99FP/Gn+VAW1VGpffG3LnH4XLkP7F/WOJjQ=; b=Q5Dk40Ot4JSzRzjurV0MLop63X5mG7/3MEy1428izX665B3QURO0ypAtQYPomzLQ93 BCjJmq1HgocNOO92EQakXgjCUy2CpRqTIUAWjGoPA0kfhPu9kfkf+4uq3EO5fisO3xxw s1Eys2oMs3KJ3mJ25J33klmqalJtFXMhoAScpF1ZHTscodkSWrntGoVOrd37mew5pGPP ChW+e2+EJ5yexHd0YuWlWF8kH9lT2XdAOaLJSSC2zzUzWZo9P7k8EIhpMHyOxIGKCH1i g2rfn8hH1c1ElvaNDBiod54vBB7PxMVhMW8twNdyQOXLROX8yGega546JB3GRnzaQFE6 U1Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679644; x=1731284444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3YC4UNbx99FP/Gn+VAW1VGpffG3LnH4XLkP7F/WOJjQ=; b=IZDfapJrtiUs0VKyJUMuLHjt+Zc0coqX09O3adywBN1L7F7WHGBiKHKNd+Dn7Ev0Lm ByrZALBxdnFahUItjlQI/TAKCAVAmsu0jw9EXXMfXa5bEl2Bh++ZbqkKArv+VbLkoqgA MOFJK2o/ze2O6OYUzwK9p6kM3RG54C+Im8c5aMxx79IARFXktulDtJmZh7j2RF+SDHK3 6ATsr8r3VWWA88MDqgOlV2HEn5M466Om/q8saaVjTOhD0NNQq4GBzYn5zcA/fGYBHQQd 2zHX5e1jti78UioTdCniIzHB27KfPHFd8wDXyTuY1qEXyF5Op1F1fAuJefjGr4zSIobY wYUA== X-Forwarded-Encrypted: i=1; AJvYcCV/qVIKVauD+oA3FEZWwhs+2Ndn8qYgSIzrvpU8i4MFz6ezdmsZ8Z9EGImlMnPyjFQQJQoGnw7TzA==@nongnu.org X-Gm-Message-State: AOJu0Yxi68uLbF6YauIwTgdE2FK5yC0cP4nlMKrAQSkSN8EvCitcknB7 z/ZNc978WtL6YyieO5Hr5WMz3MZtIsCDCHTpuA6OjAewgNniJPEa5Dw5jA== X-Google-Smtp-Source: AGHT+IHEJTNlk853wrnDd7ttSJ2qU7NwMFktQ1slRU4+hm8Z5nGcDAz4c1wfObMRZl46pSZXUGYNmA== X-Received: by 2002:a05:6a21:e92:b0:1d8:fdf8:973c with SMTP id adf61e73a8af0-1dba539790fmr14012577637.29.1730679643720; Sun, 03 Nov 2024 16:20:43 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:43 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 25/67] ppc/spapr: remove deprecated machine pseries-2.9 Date: Mon, 4 Nov 2024 10:18:14 +1000 Message-ID: <20241104001900.682660-26-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.9 specific code with this patch for now. While at it, also remove the pre-2.10 migration hacks which now become obsolete. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/intc/xics.c | 16 ------- hw/ppc/spapr.c | 104 ----------------------------------------- include/hw/ppc/spapr.h | 1 - migration/savevm.c | 19 -------- target/ppc/cpu.h | 1 - target/ppc/cpu_init.c | 2 - target/ppc/machine.c | 2 +- 7 files changed, 1 insertion(+), 144 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 6f4d5271ea..e893363dc9 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -335,22 +335,6 @@ static void icp_realize(DeviceState *dev, Error **errp) return; } } - /* - * The way that pre_2_10_icp is handling is really, really hacky. - * We used to have here this call: - * - * vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp); - * - * But we were doing: - * pre_2_10_vmstate_register_dummy_icp() - * this vmstate_register() - * pre_2_10_vmstate_unregister_dummy_icp() - * - * So for a short amount of time we had to vmstate entries with - * the same name. This fixes it. - */ - vmstate_replace_hack_for_ppc(NULL, icp->cs->cpu_index, - &vmstate_icp_server, icp); } static void icp_unrealize(DeviceState *dev) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 93decfcbeb..14a1314af6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -132,61 +132,6 @@ static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; } -static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) -{ - /* Dummy entries correspond to unused ICPState objects in older QEMUs, - * and newer QEMUs don't even have them. In both cases, we don't want - * to send anything on the wire. - */ - return false; -} - -static const VMStateDescription pre_2_10_vmstate_dummy_icp = { - /* - * Hack ahead. We can't have two devices with the same name and - * instance id. So I rename this to pass make check. - * Real help from people who knows the hardware is needed. - */ - .name = "icp/server", - .version_id = 1, - .minimum_version_id = 1, - .needed = pre_2_10_vmstate_dummy_icp_needed, - .fields = (const VMStateField[]) { - VMSTATE_UNUSED(4), /* uint32_t xirr */ - VMSTATE_UNUSED(1), /* uint8_t pending_priority */ - VMSTATE_UNUSED(1), /* uint8_t mfrr */ - VMSTATE_END_OF_LIST() - }, -}; - -/* - * See comment in hw/intc/xics.c:icp_realize() - * - * You have to remove vmstate_replace_hack_for_ppc() when you remove - * the machine types that need the following function. - */ -static void pre_2_10_vmstate_register_dummy_icp(int i) -{ - vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, - (void *)(uintptr_t) i); -} - -/* - * See comment in hw/intc/xics.c:icp_realize() - * - * You have to remove vmstate_replace_hack_for_ppc() when you remove - * the machine types that need the following function. - */ -static void pre_2_10_vmstate_unregister_dummy_icp(int i) -{ - /* - * This used to be: - * - * vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, - * (void *)(uintptr_t) i); - */ -} - int spapr_max_server_number(SpaprMachineState *spapr) { MachineState *ms = MACHINE(spapr); @@ -2711,7 +2656,6 @@ static void spapr_init_cpus(SpaprMachineState *spapr) { MachineState *machine = MACHINE(spapr); MachineClass *mc = MACHINE_GET_CLASS(machine); - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); const char *type = spapr_get_cpu_core_type(machine->cpu_type); const CPUArchIdList *possible_cpus; unsigned int smp_cpus = machine->smp.cpus; @@ -2740,15 +2684,6 @@ static void spapr_init_cpus(SpaprMachineState *spapr) boot_cores_nr = possible_cpus->len; } - if (smc->pre_2_10_has_unused_icps) { - for (i = 0; i < spapr_max_server_number(spapr); i++) { - /* Dummy entries get deregistered when real ICPState objects - * are registered during CPU core hotplug. - */ - pre_2_10_vmstate_register_dummy_icp(i); - } - } - for (i = 0; i < possible_cpus->len; i++) { int core_id = i * smp_threads; @@ -3914,21 +3849,9 @@ void spapr_core_release(DeviceState *dev) static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) { MachineState *ms = MACHINE(hotplug_dev); - SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); CPUCore *cc = CPU_CORE(dev); CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); - if (smc->pre_2_10_has_unused_icps) { - SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); - int i; - - for (i = 0; i < cc->nr_threads; i++) { - CPUState *cs = CPU(sc->threads[i]); - - pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); - } - } - assert(core_slot); core_slot->cpu = NULL; qdev_unrealize(dev); @@ -4009,7 +3932,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) { SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); MachineClass *mc = MACHINE_GET_CLASS(spapr); - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); CPUCore *cc = CPU_CORE(dev); SpaprDrc *drc; @@ -4059,12 +3981,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) } } - if (smc->pre_2_10_has_unused_icps) { - for (i = 0; i < cc->nr_threads; i++) { - CPUState *cs = CPU(core->threads[i]); - pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); - } - } } static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, @@ -5165,26 +5081,6 @@ static void spapr_machine_2_10_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 10); -/* - * pseries-2.9 - */ - -static void spapr_machine_2_9_class_options(MachineClass *mc) -{ - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - static GlobalProperty compat[] = { - { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, - }; - - spapr_machine_2_10_class_options(mc); - compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); - smc->pre_2_10_has_unused_icps = true; - smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; -} - -DEFINE_SPAPR_MACHINE(2, 9); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 6e9e62386c..af4aa1cb0f 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -143,7 +143,6 @@ struct SpaprMachineClass { /*< public >*/ bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ - bool pre_2_10_has_unused_icps; bool legacy_irq_allocation; uint32_t nr_xirqs; bool broken_host_serial_model; /* present real host info to the guest */ diff --git a/migration/savevm.c b/migration/savevm.c index 7e1e27182a..839a34402b 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -860,25 +860,6 @@ static void vmstate_check(const VMStateDescription *vmsd) } } -/* - * See comment in hw/intc/xics.c:icp_realize() - * - * This function can be removed when - * pre_2_10_vmstate_register_dummy_icp() is removed. - */ -int vmstate_replace_hack_for_ppc(VMStateIf *obj, int instance_id, - const VMStateDescription *vmsd, - void *opaque) -{ - SaveStateEntry *se = find_se(vmsd->name, instance_id); - - if (se) { - savevm_state_handler_remove(se); - g_free(se->compat); - g_free(se); - } - return vmstate_register(obj, instance_id, vmsd, opaque); -} int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, const VMStateDescription *vmsd, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 30dba050f6..faa610197d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1457,7 +1457,6 @@ struct ArchCPU { opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; /* Fields related to migration compatibility hacks */ - bool pre_2_10_migration; bool pre_3_0_migration; int32_t mig_slb_nr; }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7768392986..39c19e6674 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7452,8 +7452,6 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) } static Property ppc_cpu_properties[] = { - DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, - false), DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, false), DEFINE_PROP_END_OF_LIST(), diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 21bed7c7c8..47495b68b1 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -630,7 +630,7 @@ static bool compat_needed(void *opaque) PowerPCCPU *cpu = opaque; assert(!(cpu->compat_pvr && !cpu->vhyp)); - return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; + return cpu->compat_pvr != 0; } static const VMStateDescription vmstate_compat = { From patchwork Mon Nov 4 00:18:15 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:46 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 26/67] ppc/spapr: remove deprecated machine pseries-2.10 Date: Mon, 4 Nov 2024 10:18:15 +1000 Message-ID: <20241104001900.682660-27-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=npiggin@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.10 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 14a1314af6..4c76d2841c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5069,18 +5069,6 @@ static void spapr_machine_2_11_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 11); -/* - * pseries-2.10 - */ - -static void spapr_machine_2_10_class_options(MachineClass *mc) -{ - spapr_machine_2_11_class_options(mc); - compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); -} - -DEFINE_SPAPR_MACHINE(2, 10); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); From patchwork Mon Nov 4 00:18:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CFF0D11198 for ; Mon, 4 Nov 2024 00:25:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kq0-0000f8-GO; Sun, 03 Nov 2024 19:20:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kpz-0000ax-3U; Sun, 03 Nov 2024 19:20:55 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kpx-0002dx-Fu; Sun, 03 Nov 2024 19:20:54 -0500 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-7205b6f51f3so3037947b3a.1; Sun, 03 Nov 2024 16:20:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679651; x=1731284451; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UEIGqe7PKMmIVL8+XPUOIg+FX1T8unIwew41qiim4B0=; b=lht5W6m7j5PltVENZQOheDxVpcHo7thcdHiwuFskioZLS9pr1sNVqe2FMSDSyzoUmF mPsn26GvrriTX7irWv1rNYWDdWMrHKYLjNzQbJiQGa03kzoa3EcHIfaiCZNVMoocjxCk +pZJJtAsiowWuPWI8w+9SdmII8KO+Gfv8D1qEJ4x+L0wVmrWSJGhS6W+D7XvkBkddMVn bENYWddizjgWGUWwe//hJH5b66tpKkdKkwiDGX5ysBdJJtVstnocHPdaa4HLQhcU7df3 HcaIYpNLomNp6dZFh3ssnvj3TIuSrDyMQfL2XtiFsyKZ0x3V8CWxUd8PVeQYWbRP49gC msWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679651; x=1731284451; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UEIGqe7PKMmIVL8+XPUOIg+FX1T8unIwew41qiim4B0=; b=Xi9KgKn7njsq/Fyxr9PMCd356vKrsn8De8UAEeUoGfgGRUhbXjyxyNYobXrdcPj1Yl s5IHScG22Jah0kkyYs+GT4HjMq25knfjClNE9X4F6G7//HjbrwLhDtrGrmuY6xyPqHwW +h7oqWoODM08UShzl0hyHWcF1dJ91wLrHqP7jk/goCDpvr0IGbSQFNQ2/FyGxj+rJj7y cbORmgTcSipdA6h+EFVW1x9WnMQOYo0ED9XWYCs13HAQa7NSrV6+il9zrCn7nkCxl3ta xZwbpMNKAbj65U7++k/s+oGz+7CzQb05MX4wNGIVybLjo/ULSa9VTBvb5xXuf/kbqQma aplQ== X-Forwarded-Encrypted: i=1; AJvYcCWeHgViAL3nlOAvlpm2Eee3+jsiCj4GpV/ozyR4vF8Ob/Yhv5+MvdEXxHfFMV+gpVLTtiGDJos+Fw==@nongnu.org X-Gm-Message-State: AOJu0YzmcFwSmz8Lk9p0iYEp6WTgTXz6bdB0132ErXOhUDFW6VDLH6pY ZGTwJ7KkC/43qqf2adb1dkdCSrmcwyGoKkjs3mr12NZoQ5pLH5o87SMX/A== X-Google-Smtp-Source: AGHT+IF1B295fl2CzC/fWDQDBmzG+lcgzst2TWlvLZBxqo3PiiNYAHMybGuCQTsXl6vSZC4QlwmAPw== X-Received: by 2002:a05:6a21:2d8f:b0:1d9:1dcd:b229 with SMTP id adf61e73a8af0-1dba54a4957mr14259161637.33.1730679651309; Sun, 03 Nov 2024 16:20:51 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:50 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 27/67] ppc/spapr: remove deprecated machine pseries-2.11 Date: Mon, 4 Nov 2024 10:18:16 +1000 Message-ID: <20241104001900.682660-28-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.11 specific code with this patch. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 4c76d2841c..faf88a177b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5054,21 +5054,6 @@ static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE_TAGGED(2, 12, sxxm); -/* - * pseries-2.11 - */ - -static void spapr_machine_2_11_class_options(MachineClass *mc) -{ - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - - spapr_machine_2_12_class_options(mc); - smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; - compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); -} - -DEFINE_SPAPR_MACHINE(2, 11); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); From patchwork Mon Nov 4 00:18:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5723BD11186 for ; Mon, 4 Nov 2024 00:21:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kq4-000131-Nl; Sun, 03 Nov 2024 19:21:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kq2-0000oY-LA; Sun, 03 Nov 2024 19:20:58 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kq1-0002eG-4y; Sun, 03 Nov 2024 19:20:58 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-71e592d7f6eso2831985b3a.3; Sun, 03 Nov 2024 16:20:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679655; x=1731284455; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l94YX/AReXz7G4uDRXUPyQl8Y+x+XtS8cAUTSBbRCkw=; b=lb3hU0D1WfxLk+uZ1MKKtQ4/aMAp2GfGFFQDCnb9nEnWcJkJdX15r6IkEji5PuRJXg yrHebYwTOAoRFXXGsgCwt107ulVQsDd8pgtvf+7be8vf9C37MiSPDErkD+NJUI8rkUUH wOU/Id5MIIGalp/ieOV2odz9nLiNc2d54a1hwQZstxhcbe7yEZCNBJQL38aKOR8rRyX+ yyYc01/ajF3Q5kElkMpKJwZ0SthCvIGvGQc80gGoGvcp3GN9lv5N90kTch4Zg33YDRoH qqxfGVKLmbVLHiH14nM7V+rHTdoLXCGBHVq9qdzhc/9K6mhfIX9Lb6TQe5Jor+ku//vf EY8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679655; x=1731284455; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l94YX/AReXz7G4uDRXUPyQl8Y+x+XtS8cAUTSBbRCkw=; b=pVearEp1emb/HiF1Lgc6q8AEAWT5zUqqDGVHfQDQKYDvksLQlbDYRHxbUQLSWCLgbE 6sDlj9veJ4eYamwqInkayRiX2vSTHBH3cWBJwsg3k29m07NHCPbGM/d/T7qzuFWtkzvH TC4HEHVKP2p4XTrU4RyrXzqvVcHExVoPmynrVjxKQF1oK9k/1vdHm8aepIowDBFuDPSy GRV7F5iiXrEHT//D3Bp1rKMry4XThPM1ISGlbO8xpqxd7DP6wRxRhDaJjz9a5+kBPvaY QrqNWnFyi2RxzfNXfdv+WT2sufn2iuglOF7ChuMKupBt2BB7GtWcx7nvZM4E6/Iy4Q/J 3E1A== X-Forwarded-Encrypted: i=1; AJvYcCXsOEFpVXwxkM8kPaAXtjnCPwqCANOHOHTU/88Cgm99xxhg+YKAdWCnd/cGVpbGrq4BqqDC4iNzwA==@nongnu.org X-Gm-Message-State: AOJu0YxKEtluFFyIqKqxMsivU3+7iqoGT9I/wYSiNAE4nBH7xrVs05J3 bgDXX2ny8lTf0QMK/blGaMk7nWoJTMxhBDuYrUXGaX0YMEl9/2LrVhljuA== X-Google-Smtp-Source: AGHT+IElnLRQgIUblUlRbMaqqTJtnFjL7sQFstDb/FD50U9/cEmA/5j5FSjF57KxsXyJToawiSzw0Q== X-Received: by 2002:a05:6a00:1708:b0:71d:f423:e6cc with SMTP id d2e1a72fcca58-720c98d5c3dmr16120103b3a.8.1730679654941; Sun, 03 Nov 2024 16:20:54 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:54 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 28/67] ppc/spapr: remove deprecated machine pseries-2.12-sxxm Date: Mon, 4 Nov 2024 10:18:17 +1000 Message-ID: <20241104001900.682660-29-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12-sxxm specific code with this patch. Suggested-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index faf88a177b..aba0ad26f1 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4731,8 +4731,6 @@ static void spapr_machine_latest_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE_IMPL(true, major, minor) #define DEFINE_SPAPR_MACHINE(major, minor) \ DEFINE_SPAPR_MACHINE_IMPL(false, major, minor) -#define DEFINE_SPAPR_MACHINE_TAGGED(major, minor, tag) \ - DEFINE_SPAPR_MACHINE_IMPL(false, major, minor, _, tag) /* * pseries-9.2 @@ -5042,18 +5040,6 @@ static void spapr_machine_2_12_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(2, 12); -static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) -{ - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - - spapr_machine_2_12_class_options(mc); - smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; - smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; - smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; -} - -DEFINE_SPAPR_MACHINE_TAGGED(2, 12, sxxm); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); From patchwork Mon Nov 4 00:18:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D71D4D11194 for ; Mon, 4 Nov 2024 00:22:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kq8-0001IM-UQ; Sun, 03 Nov 2024 19:21:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kq6-0001Bs-KH; Sun, 03 Nov 2024 19:21:02 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kq4-0002eX-JQ; Sun, 03 Nov 2024 19:21:02 -0500 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-720aa3dbda5so2637145b3a.1; Sun, 03 Nov 2024 16:20:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679659; x=1731284459; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=84ZD8pabKLp119VbZhFi0fdSlQOMQdaojXG08AGaLh4=; b=dBdeUTP2VpZvu1Dn+BHme58Y95jI1PbPeUwFRTvKbYm3KQBAAyADYgJoGo83ModuHi Y1mOmmfq3mJhgCGqXrSwV3bRX5EhT1gKIBvnUaEPH99IXSFpCNI+NrD/Xkp4FtotzQTz 0dlwG59bJ8J0Auci8w1qTKlzuzTLUhOHFnVQ6okA4z0F/PbIPxkmSXu+QMf7rMZvvSyW U7KkfWd/BJsQ/2M6cSB9mrQ8b4iP3MAy9LGm+apQr4RtSd3ifpSd691HGU9mrBDtZd1Z JAgDBrRzhXXRVtdaHOfhdl1KtGyqKbzTJ/k/i1VNlhu0cXKu2wVIVPkMAJOC/Tq0IvM2 auUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679659; x=1731284459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=84ZD8pabKLp119VbZhFi0fdSlQOMQdaojXG08AGaLh4=; b=B9YHK/GFP7zrQAJnEX9etvHFniVoOUMJB0DXAgXr9LWqnjsaVgbdporm2STKC1RE48 z72jrkm8L5Fgz8HK07WktmPU0CX+yr58EB31tZT6N8OQ2Up/Gaa71S8WMCEqIXzpJuJi 8Fq5PeR8S0BDp3LUWo0rVtiuzbFk79v14GfwYifoa639kVh2cGfqIEQmhV+0gUVzlX4j 0SJywUgTt/UxlvXXG+Os3UjLWw3Gi3oHQhVmBTfx/JcYVgprmQGqUYP1Z8bZmZ02j6mh iUaEB6leEBSAb5J3PVkaWthVC6SDoot6nLORC0IFKC9gbTVuo9ARuC8X9S9G4i3aDg+3 NcKg== X-Forwarded-Encrypted: i=1; AJvYcCV+LtkUTZ3aFBKFVjRMfInUnnQJV+gvOrUbEitdaC7Gfo/DabWdb2aJIyXOHkTmZH2mp6chkX145A==@nongnu.org X-Gm-Message-State: AOJu0YwX8TBf6WQVb4aNVr8AKNp67US7CVQWnt14L0QbWVZaT3FCslaY k4fZ7B/hECShSFhCFtGevSVxKoiSDuFQOXvidlULaG/J4LMLWVe3s+pnoQ== X-Google-Smtp-Source: AGHT+IGsOAam8Rg+VizetZPqaWov8/aZr41M4blUUYlAv487W+x9S01PQLJ0B5ujRvf55UUCkltouQ== X-Received: by 2002:a05:6a20:6a21:b0:1db:db2f:f3a5 with SMTP id adf61e73a8af0-1dbdb3025c0mr2588895637.21.1730679658591; Sun, 03 Nov 2024 16:20:58 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:20:58 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= Subject: [PULL 29/67] ppc/spapr: remove deprecated machine pseries-2.12 Date: Mon, 4 Nov 2024 10:18:18 +1000 Message-ID: <20241104001900.682660-30-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Commit 0cac0f1b964 marked pseries-2.12 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.12 specific code with this patch. While at it, also remove pre-3.0-migration hacks introduced for backward compatibility which are now turned useless. Suggested-by: Cédric Le Goater Signed-off-by: Harsh Prateek Bora Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- docs/about/deprecated.rst | 8 -------- hw/ppc/spapr.c | 25 ------------------------- hw/ppc/spapr_cpu_core.c | 12 +++--------- include/hw/ppc/spapr_cpu_core.h | 1 - target/ppc/cpu.h | 4 ---- target/ppc/cpu_init.c | 3 +-- target/ppc/machine.c | 18 +----------------- 7 files changed, 5 insertions(+), 66 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 1e1e9f5f18..756186f4f0 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -243,14 +243,6 @@ These old machine types are quite neglected nowadays and thus might have various pitfalls with regards to live migration. Use a newer machine type instead. -``pseries-2.1`` up to ``pseries-2.12`` (since 9.0) -'''''''''''''''''''''''''''''''''''''''''''''''''' - -Older pseries machines before version 3.0 have undergone many changes -to correct issues, mostly regarding migration compatibility. These are -no longer maintained and removing them will make the code easier to -read and maintain. Use versions 3.0 and above as a replacement. - PPC 405 ``ref405ep`` machine (since 9.1) '''''''''''''''''''''''''''''''''''''''' diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index aba0ad26f1..5c02037c56 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -5015,31 +5015,6 @@ static void spapr_machine_3_0_class_options(MachineClass *mc) DEFINE_SPAPR_MACHINE(3, 0); -/* - * pseries-2.12 - */ -static void spapr_machine_2_12_class_options(MachineClass *mc) -{ - SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - static GlobalProperty compat[] = { - { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, - { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, - }; - - spapr_machine_3_0_class_options(mc); - compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); - compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); - - /* We depend on kvm_enabled() to choose a default value for the - * hpt-max-page-size capability. Of course we can't do it here - * because this is too early and the HW accelerator isn't initialized - * yet. Postpone this to machine init (see default_caps_with_cpu()). - */ - smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; -} - -DEFINE_SPAPR_MACHINE(2, 12); - static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 4642245168..1a84345f36 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -197,9 +197,7 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) { CPUPPCState *env = &cpu->env; - if (!sc->pre_3_0_migration) { - vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); - } + vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); cpu_ppc_tb_free(env); qdev_unrealize(DEVICE(cpu)); @@ -285,10 +283,8 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, return false; } - if (!sc->pre_3_0_migration) { - vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, - cpu->machine_data); - } + vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, + cpu->machine_data); return true; } @@ -366,8 +362,6 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) static Property spapr_cpu_core_properties[] = { DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), - DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, - false), DEFINE_PROP_END_OF_LIST() }; diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h index 69a52e39b8..68f7083483 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -28,7 +28,6 @@ struct SpaprCpuCore { /*< public >*/ PowerPCCPU **threads; int node_id; - bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */ }; struct SpaprCpuCoreClass { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index faa610197d..b838bc2ab9 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1455,10 +1455,6 @@ struct ArchCPU { /* Those resources are used only during code translation */ /* opcode handlers */ opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; - - /* Fields related to migration compatibility hacks */ - bool pre_3_0_migration; - int32_t mig_slb_nr; }; /** diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 39c19e6674..011e53d961 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7452,8 +7452,7 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) } static Property ppc_cpu_properties[] = { - DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, - false), + /* add default property here */ DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 47495b68b1..717bf93e88 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -118,15 +118,6 @@ static const VMStateInfo vmstate_info_vsr = { #define VMSTATE_VSR_ARRAY(_f, _s, _n) \ VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) -#if defined(TARGET_PPC64) -static bool cpu_pre_3_0_migration(void *opaque, int version_id) -{ - PowerPCCPU *cpu = opaque; - - return cpu->pre_3_0_migration; -} -#endif - static int cpu_pre_save(void *opaque) { PowerPCCPU *cpu = opaque; @@ -154,12 +145,6 @@ static int cpu_pre_save(void *opaque) env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4]; } - if (cpu->pre_3_0_migration) { - if (cpu->hash64_opts) { - cpu->mig_slb_nr = cpu->hash64_opts->slb_size; - } - } - /* Used to retain migration compatibility for pre 6.0 for 601 machines. */ env->hflags_compat_nmsr = 0; @@ -503,12 +488,11 @@ static int slb_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_slb = { .name = "cpu/slb", - .version_id = 1, + .version_id = 2, .minimum_version_id = 1, .needed = slb_needed, .post_load = slb_post_load, .fields = (const VMStateField[]) { - VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration), VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), VMSTATE_END_OF_LIST() } From patchwork Mon Nov 4 00:18:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27433D11194 for ; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.20.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:01 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , Aditya Gupta , Amit Machhiwal Subject: [PULL 30/67] target/ppc: Reduce code duplication across Power9/10 init code Date: Mon, 4 Nov 2024 10:18:19 +1000 Message-ID: <20241104001900.682660-31-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Power9/10 initialization code consists of a lot of logical OR of various flag bits as supported by respective Power platform during its initialization, most of which is duplicated and only selected bits are added or removed as needed with each new platform support being added. Remove the duplicate code and share using common macros. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora [adityag: renamed many POWERPC_* flags to PPC_* flags, checkpatch fixes] Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 124 +++++------------------------------------- target/ppc/cpu_init.h | 84 ++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 109 deletions(-) create mode 100644 target/ppc/cpu_init.h diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 011e53d961..7c3716b56f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -52,6 +52,7 @@ #include "kvm_ppc.h" #endif +#include "cpu_init.h" /* #define PPC_DEBUG_SPR */ /* #define USE_APPLE_GDB */ @@ -6510,58 +6511,15 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER9"; dc->desc = "POWER9"; pcc->pvr_match = ppc_pvr_match_power9; - pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; - pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | - PCR_COMPAT_2_05; + pcc->pcr_mask = PPC_PCR_MASK_POWER9; + pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9; pcc->init_proc = init_proc_POWER9; pcc->check_pow = check_pow_nocheck; pcc->check_attn = check_attn_hid0_power9; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC | - PPC2_BCDA_ISA206; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_TM) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->insns_flags = PPC_INSNS_FLAGS_POWER9; + pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9; + pcc->msr_mask = PPC_MSR_MASK_POWER9; + pcc->lpcr_mask = PPC_LPCR_MASK_POWER9; pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if !defined(CONFIG_USER_ONLY) @@ -6574,10 +6532,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->excp_model = POWERPC_EXCP_POWER9; pcc->bus_model = PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + pcc->flags = POWERPC_FLAGS_POWER9; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; } @@ -6690,60 +6645,15 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER10"; dc->desc = "POWER10"; pcc->pvr_match = ppc_pvr_match_power10; - pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | - PCR_COMPAT_3_00; - pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | - PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->pcr_mask = PPC_PCR_MASK_POWER10; + pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10; pcc->init_proc = init_proc_POWER10; pcc->check_pow = check_pow_nocheck; pcc->check_attn = check_attn_hid0_power9; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | - PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; - /* DD2 adds an extra HAIL bit */ - pcc->lpcr_mask |= LPCR_HAIL; + pcc->insns_flags = PPC_INSNS_FLAGS_POWER10; + pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10; + pcc->msr_mask = PPC_MSR_MASK_POWER10; + pcc->lpcr_mask = PPC_LPCR_MASK_POWER10; pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; @@ -6756,11 +6666,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->excp_model = POWERPC_EXCP_POWER10; pcc->bus_model = PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | - POWERPC_FLAG_BHRB; + pcc->flags = POWERPC_FLAGS_POWER10; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; } diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h new file mode 100644 index 0000000000..9e027876f3 --- /dev/null +++ b/target/ppc/cpu_init.h @@ -0,0 +1,84 @@ +#ifndef TARGET_PPC_CPU_INIT_H +#define TARGET_PPC_CPU_INIT_H + +#define PPC_INSNS_FLAGS_POWER9 \ + (PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | \ + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | \ + PPC_FLOAT_STFIWX | PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | \ + PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ + PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | \ + PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | \ + PPC_CILDST) + +#define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 + +#define PPC_INSNS_FLAGS2_POWER_COMMON \ + (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206) + +#define PPC_INSNS_FLAGS2_POWER9 \ + (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM) +#define PPC_INSNS_FLAGS2_POWER10 \ + (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310) + +#define PPC_MSR_MASK_POWER_COMMON \ + ((1ull << MSR_SF) | \ + (1ull << MSR_HV) | \ + (1ull << MSR_VR) | \ + (1ull << MSR_VSX) | \ + (1ull << MSR_EE) | \ + (1ull << MSR_PR) | \ + (1ull << MSR_FP) | \ + (1ull << MSR_ME) | \ + (1ull << MSR_FE0) | \ + (1ull << MSR_SE) | \ + (1ull << MSR_DE) | \ + (1ull << MSR_FE1) | \ + (1ull << MSR_IR) | \ + (1ull << MSR_DR) | \ + (1ull << MSR_PMM) | \ + (1ull << MSR_RI) | \ + (1ull << MSR_LE)) + +#define PPC_MSR_MASK_POWER9 \ + (PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM)) +#define PPC_MSR_MASK_POWER10 \ + PPC_MSR_MASK_POWER_COMMON + +#define PPC_PCR_MASK_POWER9 \ + (PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07) +#define PPC_PCR_MASK_POWER10 \ + (PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00) + +#define PPC_PCR_SUPPORTED_POWER9 \ + (PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05) +#define PPC_PCR_SUPPORTED_POWER10 \ + (PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10) + +#define PPC_LPCR_MASK_POWER9 \ + (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | \ + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | \ + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | \ + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | \ + LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | \ + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE) +/* DD2 adds an extra HAIL bit */ +#define PPC_LPCR_MASK_POWER10 \ + (PPC_LPCR_MASK_POWER9 | LPCR_HAIL) + +#define POWERPC_FLAGS_POWER_COMMON \ + (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | \ + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV) + +#define POWERPC_FLAGS_POWER9 \ + (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM) +#define POWERPC_FLAGS_POWER10 \ + (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB) + +#endif /* TARGET_PPC_CPU_INIT_H */ From patchwork Mon Nov 4 00:18:20 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:05 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Aditya Gupta , Amit Machhiwal Subject: [PULL 31/67] target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr' Date: Mon, 4 Nov 2024 10:18:20 +1000 Message-ID: <20241104001900.682660-32-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Aditya Gupta Introduce 'PnvChipClass::spapr_logical_pvr' to know corresponding logical PVR of a PowerPC CPU. This helps to have a one-to-one mapping between PVR and logical PVR for a CPU, and used in a later commit to handle cases where PCR of two generations of Power chip is same, which causes regressions with compat-mode. Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b838bc2ab9..daa12f8733 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1473,6 +1473,7 @@ struct PowerPCCPUClass { void (*parent_parse_features)(const char *type, char *str, Error **errp); uint32_t pvr; + uint32_t spapr_logical_pvr; /* * If @best is false, match if pcc is in the family of pvr * Else match only if pcc is the best match for pvr in this family. diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7c3716b56f..bc8ec77fa0 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6154,6 +6154,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER7"; dc->desc = "POWER7"; + pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS; pcc->pvr_match = ppc_pvr_match_power7; pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; @@ -6317,6 +6318,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER8"; dc->desc = "POWER8"; + pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07; pcc->pvr_match = ppc_pvr_match_power8; pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; @@ -6510,6 +6512,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER9"; dc->desc = "POWER9"; + pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00; pcc->pvr_match = ppc_pvr_match_power9; pcc->pcr_mask = PPC_PCR_MASK_POWER9; pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9; @@ -6644,6 +6647,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER10"; dc->desc = "POWER10"; + pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10; pcc->pvr_match = ppc_pvr_match_power10; pcc->pcr_mask = PPC_PCR_MASK_POWER10; pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10; From patchwork Mon Nov 4 00:18:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19D4FD11194 for ; Mon, 4 Nov 2024 00:29:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kqI-0002KX-GE; Sun, 03 Nov 2024 19:21:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqH-00029q-17; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:09 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Aditya Gupta , Amit Machhiwal Subject: [PULL 32/67] target/ppc: Fix regression due to Power10 and Power11 having same PCR Date: Mon, 4 Nov 2024 10:18:21 +1000 Message-ID: <20241104001900.682660-33-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Aditya Gupta Power11 has the same PCR (Processor Compatibility Register) value, as Power10. Due to this, QEMU considers Power11 as a valid compat-mode for Power10, ie. earlier it was possible to run QEMU with '-M pseries,max-compat-mode=power11 --cpu power10' Same PCR also introduced a regression where `-M pseries --cpu power10` boots as Power11 (ie. logical PVR is of Power11, even though PVR is Power10). The regression was due to 'do_client_architecture_support' checking for valid compat modes and finding Power11 to be a valid compat mode for Power10 (it happens even without passing 'max-compat-mode' explicitly). Fix compat-mode issue and regression, by ensuring a future Power processor (with a higher logical_pvr value, eg. P11) cannot be valid compat-mode for an older Power processor (eg. P10) Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- target/ppc/compat.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index ebef2cccec..5b20fd7ef0 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -132,6 +132,10 @@ static bool pcc_compat(PowerPCCPUClass *pcc, uint32_t compat_pvr, /* Outside specified range */ return false; } + if (compat->pvr > pcc->spapr_logical_pvr) { + /* Older CPU cannot support a newer processor's compat mode */ + return false; + } if (!(pcc->pcr_supported & compat->pcr_level)) { /* Not supported by this CPU */ return false; From patchwork Mon Nov 4 00:18:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CB96D11198 for ; Mon, 4 Nov 2024 00:28:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kqO-0002t8-E7; Sun, 03 Nov 2024 19:21:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqL-0002aV-AF; Sun, 03 Nov 2024 19:21:17 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kqJ-0002fx-6v; Sun, 03 Nov 2024 19:21:16 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-72041ff06a0so3061844b3a.2; Sun, 03 Nov 2024 16:21:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679673; x=1731284473; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c1XsHuBIcfUyMOIaLjJZ+AcxJBNg7k7Apo9qjCBzFG0=; b=EA2qnhO6H1fXuBkyv+la86q7zaWVNXnVO73++6V+lXyk/yDvjdPM4hwo1pK6sjuUGT WD0wqGNN6M9SNADVTZDYe3OaC2QcWOK7iYoeIJ9tCWoLAqE32xV16wMoebDtAq0vrFGZ B2rvMutjLbcTWKi2Hp4upOvexdxgtJaiSIwTi4N1DvW0N6lE5PwCT0A3u6nyo6/p+jZO IURKCNJQ+fX40xhQwggAeMujxohGc3usxok3gvFnOQUfk62mNXi//B5U3jgppyG7P2js tRcLzVl1d0xWpxxTujEZWpHsuaChIvBtbYSiIi+N+/+OrZOy5ndB2HyTpI6E6cdjYDGX PJUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679673; x=1731284473; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c1XsHuBIcfUyMOIaLjJZ+AcxJBNg7k7Apo9qjCBzFG0=; b=ixcEWHclNQINBGnGHxe5/pRi6qC1aAEoffUFJvtKbCdarMQ4xTkJPNxJ3HIwMGJI7D zTT9a/hGYi2ePc+Mkq2ULiAg1nFKB9QAz+nDVG3c0wlJnmaxCWFINiUVt6iSuerPvbUP 5d2qvvJywd4+2pyb3f7kkzbgHdEOWp/1QHZQAcN4k0IU832Rk2WPGHu7GMTkH3DxMrfe cI7oJQUaMZP8hzTh/FytUU8603ZBxse8Ni/M5g3pKjBMD+Epuh4bNEnfCgnDS4c8jFiR dy4gpJ6N3fMNEexgaoEf+2PSeMXQmBqlykZQsM9o3a/MnNlFdddOboJXwdYEWyLvEyWR 7wNQ== X-Forwarded-Encrypted: i=1; AJvYcCWI9SoeVMrKxEf3O6ZgS9ETeJhTzCKip3GPMlGNnvckNPJywMKvNSymlal97qQM+btL4Dlj/NByyQ==@nongnu.org X-Gm-Message-State: AOJu0YyUXeLd7nUMIMFMu/UpQA1RpoAyQ2snYwTvYVTf7UPaKigz3xVm luszpHdEq/w0vdHcevMvBdSWxyl99ZNSUIbytIkJLa/5PULm7blw+V7jnA== X-Google-Smtp-Source: AGHT+IFQqdF2mCD88K9cq8LMxbfi2d3Xy3o0HLqFRwmpgcNyPOfmWaUaNLS8wzvessuuSW1H30pxLg== X-Received: by 2002:a05:6a20:d488:b0:1d9:1045:3ed5 with SMTP id adf61e73a8af0-1dba52a4592mr14872743637.11.1730679673106; Sun, 03 Nov 2024 16:21:13 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:12 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Aditya Gupta , Amit Machhiwal Subject: [PULL 33/67] target/ppc: Add Power11 DD2.0 processor Date: Mon, 4 Nov 2024 10:18:22 +1000 Message-ID: <20241104001900.682660-34-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Aditya Gupta Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- target/ppc/compat.c | 7 +++++ target/ppc/cpu-models.c | 3 ++ target/ppc/cpu-models.h | 3 ++ target/ppc/cpu.h | 2 ++ target/ppc/cpu_init.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/ppc/cpu_init.h | 7 +++++ target/ppc/excp_helper.c | 4 +++ 7 files changed, 86 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 5b20fd7ef0..0cec1bde91 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = { .pcr_level = PCR_COMPAT_3_10, .max_vthreads = 8, }, + { /* POWER11, ISA3.10 */ + .name = "power11", + .pvr = CPU_POWERPC_LOGICAL_3_10_P11, + .pcr = PCR_COMPAT_3_10, + .pcr_level = PCR_COMPAT_3_10, + .max_vthreads = 8, + }, }; static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index f2301b43f7..ece3481781 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -734,6 +734,8 @@ "POWER9 v2.2") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10, "POWER10 v2.0") + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER11, + "POWER11_v2.0") #endif /* defined (TARGET_PPC64) */ /***************************************************************************/ @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, + { "power11", "power11_v2.0" }, #endif /* Generic PowerPCs */ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a..72ad31ba50 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -354,6 +354,8 @@ enum { CPU_POWERPC_POWER10_BASE = 0x00800000, CPU_POWERPC_POWER10_DD1 = 0x00801100, CPU_POWERPC_POWER10_DD20 = 0x00801200, + CPU_POWERPC_POWER11_BASE = 0x00820000, + CPU_POWERPC_POWER11_DD20 = 0x00821200, CPU_POWERPC_970_v22 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, CPU_POWERPC_970FX_v20 = 0x003C0200, @@ -391,6 +393,7 @@ enum { CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, + CPU_POWERPC_LOGICAL_3_10_P11 = 0x0F000007, }; /* System version register (used on MPC 8xxx) */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index daa12f8733..945af07a64 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -216,6 +216,8 @@ typedef enum powerpc_excp_t { POWERPC_EXCP_POWER9, /* POWER10 exception model */ POWERPC_EXCP_POWER10, + /* POWER11 exception model */ + POWERPC_EXCP_POWER11, } powerpc_excp_t; /*****************************************************************************/ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index bc8ec77fa0..c26e5b269c 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6675,6 +6675,66 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_icache_size = 0x8000; } +static void init_proc_POWER11(CPUPPCState *env) +{ + init_proc_POWER10(env); +} + +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) +{ + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; + + if (!best && (base == CPU_POWERPC_POWER11_BASE)) { + return true; + } + + if (base != pcc_base) { + return false; + } + + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { + return true; + } + + return false; +} + +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER11"; + dc->desc = "POWER11"; + pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11; + pcc->pvr_match = ppc_pvr_match_power11; + pcc->pcr_mask = PPC_PCR_MASK_POWER11; + pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11; + pcc->init_proc = init_proc_POWER11; + pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_hid0_power9; + pcc->insns_flags = PPC_INSNS_FLAGS_POWER11; + pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11; + pcc->msr_mask = PPC_MSR_MASK_POWER11; + pcc->lpcr_mask = PPC_LPCR_MASK_POWER11; + + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; + pcc->mmu_model = POWERPC_MMU_3_00; +#if !defined(CONFIG_USER_ONLY) + /* segment page size remain the same */ + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->radix_page_info = &POWER10_radix_page_info; + pcc->lrg_decr_bits = 56; +#endif + pcc->excp_model = POWERPC_EXCP_POWER11; + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAGS_POWER11; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 9e027876f3..f8fd6ff5cd 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -12,6 +12,7 @@ PPC_CILDST) #define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 +#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10 #define PPC_INSNS_FLAGS2_POWER_COMMON \ (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ @@ -25,6 +26,7 @@ (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM) #define PPC_INSNS_FLAGS2_POWER10 \ (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310) +#define PPC_INSNS_FLAGS2_POWER11 PPC_INSNS_FLAGS2_POWER10 #define PPC_MSR_MASK_POWER_COMMON \ ((1ull << MSR_SF) | \ @@ -49,16 +51,19 @@ (PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM)) #define PPC_MSR_MASK_POWER10 \ PPC_MSR_MASK_POWER_COMMON +#define PPC_MSR_MASK_POWER11 PPC_MSR_MASK_POWER10 #define PPC_PCR_MASK_POWER9 \ (PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07) #define PPC_PCR_MASK_POWER10 \ (PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00) +#define PPC_PCR_MASK_POWER11 PPC_PCR_MASK_POWER10 #define PPC_PCR_SUPPORTED_POWER9 \ (PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05) #define PPC_PCR_SUPPORTED_POWER10 \ (PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10) +#define PPC_PCR_SUPPORTED_POWER11 PPC_PCR_SUPPORTED_POWER10 #define PPC_LPCR_MASK_POWER9 \ (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | \ @@ -70,6 +75,7 @@ /* DD2 adds an extra HAIL bit */ #define PPC_LPCR_MASK_POWER10 \ (PPC_LPCR_MASK_POWER9 | LPCR_HAIL) +#define PPC_LPCR_MASK_POWER11 PPC_LPCR_MASK_POWER10 #define POWERPC_FLAGS_POWER_COMMON \ (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ @@ -80,5 +86,6 @@ (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM) #define POWERPC_FLAGS_POWER10 \ (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB) +#define POWERPC_FLAGS_POWER11 POWERPC_FLAGS_POWER10 #endif /* TARGET_PPC_CPU_INIT_H */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b619a6adde..087235bd62 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1661,6 +1661,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_POWER8: case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: powerpc_excp_books(cpu, excp); break; default: @@ -2018,6 +2019,7 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env) return p8_next_unmasked_interrupt(env); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: return p9_next_unmasked_interrupt(env); default: break; @@ -2378,6 +2380,7 @@ static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt) return p8_deliver_interrupt(env, interrupt); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: return p9_deliver_interrupt(env, interrupt); default: break; @@ -3168,6 +3171,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, case POWERPC_EXCP_POWER8: case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: + case POWERPC_EXCP_POWER11: /* * Machine check codes can be found in processor User Manual or * Linux or skiboot source. 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:16 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Aditya Gupta , Harsh Prateek Bora , Amit Machhiwal Subject: [PULL 34/67] ppc/pseries: Add Power11 cpu type Date: Mon, 4 Nov 2024 10:18:23 +1000 Message-ID: <20241104001900.682660-35-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Aditya Gupta Add sPAPR CPU Core definition for Power11 Reviewed-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Tested-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- docs/system/ppc/pseries.rst | 17 +++++++++++++---- hw/ppc/spapr_cpu_core.c | 1 + 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index a876d897b6..bbc51aa7fc 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -14,10 +14,19 @@ virtualization capabilities. Supported devices ================= - * Multi processor support for many Power processors generations: POWER7, - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, - but its state is unknown. - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) + * Multi processor support for many Power processors generations: + - POWER7, POWER7+ + - POWER8, POWER8NVL + - POWER9 + - Power10 + - Power11 + - Support for POWER5+ also exists, works with correct kernel/userspace + * Interrupt Controller + - XICS (POWER8) + - XIVE (Supported by below:) + - POWER9 + - Power10 + - Power11 * vPHB PCIe Host bridge. * vscsi and vnet devices, compatible with the same devices available on a PowerVM hypervisor with VIOS managing LPARs. diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 1a84345f36..ada439e831 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -405,6 +405,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = { DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), + DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"), #ifdef CONFIG_KVM DEFINE_SPAPR_CPU_CORE_TYPE("host"), #endif From patchwork Mon Nov 4 00:18:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E566D11194 for ; Mon, 4 Nov 2024 00:22:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kqW-0003fs-Om; Sun, 03 Nov 2024 19:21:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqS-0003LX-B4; Sun, 03 Nov 2024 19:21:24 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kqQ-0002gb-Re; Sun, 03 Nov 2024 19:21:24 -0500 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-7ee51d9ae30so1977861a12.1; Sun, 03 Nov 2024 16:21:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679681; x=1731284481; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1AYuhGepsU7zeG4tt44YiLnEKuxFxxMmBcxIo9aE1no=; b=aZsTXWOpxzG15h3c6Pu6iRhH8VNp7cVIan0VrIKqFzDup1VOEoF2bEC3bjLGsUI+s1 73joQJ/0JFLQF2IneU+zSHCRV2gC4tTqMsV0aZmxowOYErxCgYGaPflDSS2b+qshEzMB 3vZs0sMwrS6nrkXTIdyNIXYsTX8XhixsILS+OsS57oAmBTL1SCTD9jqS0xMYTLHKKe6R 1UkyioXlcFtRWhuBxOpQWjTEkYlGUcH30N9wu19YdGU+laJ3QJ+26Bt9tf1sZZiOOqmh IlDFgFawfh51EPLvwj/jOLcAnUSaNEYRWS2gaIGz/WSf2r6UOaY9+td0hUtomngHL3x2 VCzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679681; x=1731284481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1AYuhGepsU7zeG4tt44YiLnEKuxFxxMmBcxIo9aE1no=; b=nGY6zQ+WAGzNlK73dZSbSXVUFOgE68pPiq5gCpoEwAZzhRiPhrU1PYHJeXHu6fi+Gt 3lrkHincpN2KlqYGgE5v9Q6ZT/5Sgv6NNwVyxiU9bog02fBwSKed95uShS9ghUK4Zx8a R3XXr8jkxuiB3BKLSB6fnzOtgdfcRnPJKqvwG2tdcdGPI+DHloJm3aDARsk9w48+C24t a3z+EIMXYzxWju6KqxEftlkilAX/g9fDiC9DUo4N8qyN2Hng60CWWDY0BN017nwAoBGX Tz52apGhOqKIgtrBTlfY9NGfUE3XyaY7SH75Z58mgUc4yASJa7wA1C+Bi1fi/QdnOaqK cnag== X-Forwarded-Encrypted: i=1; AJvYcCUreGKBCmTjAHGvAQiYdAO49pOCUTieVpCKAxYOA5wy8CpvJmIhVA8Cs7dQSXlFGdroMdGKLISvGA==@nongnu.org X-Gm-Message-State: AOJu0YxdmfJrw4EI6bPy1WBxsdoD2cQn0PLoK5uhLgGsaEWnQuvnDKlj 6wSPrminR0TMMZPRYGZTuOe1KHlZ1BriD7IvhBdxVEe0c1/QmSCd2fRadw== X-Google-Smtp-Source: AGHT+IFO5jkCvoSHccIrMP4uez9IcyzwXl0bqQttIX9sZ1zgh1eUXXsHI13vTCCdnNqJJDpr9gM9Lg== X-Received: by 2002:a05:6a21:78d:b0:1d8:aca7:912 with SMTP id adf61e73a8af0-1dba5409a21mr15409643637.28.1730679680765; Sun, 03 Nov 2024 16:21:20 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:20 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , BALATON Zoltan Subject: [PULL 35/67] target/ppc: use locally stored msr and avoid indirect access Date: Mon, 4 Nov 2024 10:18:24 +1000 Message-ID: <20241104001900.682660-36-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora hreg_compute_hflags_value already stores msr locally to be used in most of the logic in the routine however some instances are still using env->msr which is unnecessary. Use locally stored value as available. Reviewed-by: Nicholas Piggin Reviewed-by: BALATON Zoltan Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/helper_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 02076e96fb..fe543ab3b8 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -143,10 +143,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) if (ppc_flags & POWERPC_FLAG_DE) { target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; - if ((dbcr0 & DBCR0_ICMP) && FIELD_EX64(env->msr, MSR, DE)) { + if ((dbcr0 & DBCR0_ICMP) && FIELD_EX64(msr, MSR, DE)) { hflags |= 1 << HFLAGS_SE; } - if ((dbcr0 & DBCR0_BRT) && FIELD_EX64(env->msr, MSR, DE)) { + if ((dbcr0 & DBCR0_BRT) && FIELD_EX64(msr, MSR, DE)) { hflags |= 1 << HFLAGS_BE; } } else { From patchwork Mon Nov 4 00:18:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B29DD11198 for ; Mon, 4 Nov 2024 00:25:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kqZ-00042B-2Q; Sun, 03 Nov 2024 19:21:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqV-0003Z0-3m; Sun, 03 Nov 2024 19:21:27 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kqT-0002gv-LG; Sun, 03 Nov 2024 19:21:26 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-723db2798caso65910b3a.0; Sun, 03 Nov 2024 16:21:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679684; x=1731284484; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D5acwOP9v6mqTwgIgkzY3AX70LRjavmcEjrHnDYPLjA=; b=HkyK9lH1oqkY0NXSVPMa2hqyPeEzaZfzc/5P0wwbssGsmOLK1kBLys0ZXwHkDPGPTi 6BZB829MHzyg9LkR91lq/5KGNNav6jxmQBnRWv+L0eZ46tXCjeddj+528e2WhfOBCmQC AuGlIENd71ARt2RaR6M0uAKINhD9elTGGsjgqgfh0Q3Dwmzwl+IaUHWsMOzylFWCfe/Q tH+QvAFYHonnymFm2cLAIiFNIKIWMIUZjTV5sdvhat6iP332kjuwjpb64ycVJZrY+H5V 0DMS6sT3WA2UnxlIzOI+guqym99a8pExmLFWbOSbvKEphZyKFUD8SKo5dd5f3dTGv339 C/yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679684; x=1731284484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D5acwOP9v6mqTwgIgkzY3AX70LRjavmcEjrHnDYPLjA=; b=aRf390+KyHOvSHWEQTQOZW+rEgYDzlxRMdu9IufMrB+bTV6OZnAOui/3YyBhF7DoDT I5UsVTW3Boukbs24DZAmp0cJUHM3wue7+IZy0lw9JzRJiG6B6bKAvrBUxTEJu/TtHIps s8KDipD7yJ4kCZrTwgD1a/TdjqOcgRqb/Spf0RrIPx4LH9Nvzro5rel5WjuRRYLDB4hG 1afJzdkSMM3yCaf8MEQH0XeotvtRUOrHlYqSPTFbRVzigORdV5RTmSayU4+1sWw6XpJv 0mKAl0MiHnWcDhmRO4lCNqfu3Xij6Y+Ve9e2QAmMzHfCwQhBS1jwPikYHf/xAELFhLP6 wWxA== X-Forwarded-Encrypted: i=1; AJvYcCV7tJo6pZO/oLzR3EMKRG87wYnbZndPaEqIjYizwZbd+KVc5o71zVs7HIxRZnIddTdSyrz/U8pelQ==@nongnu.org X-Gm-Message-State: AOJu0YyjOiwuGbhx5lwqO1QlbWASGTN2ioi7OtQHROQ1MOd5SCl7l1Cf o+/SEjFvwVLtmZcvOI9D2yCcmVYJYd4mqie+2x0sRQS+3tNA1pIGSnzMPA== X-Google-Smtp-Source: AGHT+IFKr/EWg0gHaidpnCHmzxm7Rd3iuMQxTpy2lICcjT7z8nVQ0RnlCXk7gfP4XlT9Wq+q954v6w== X-Received: by 2002:a05:6a21:6d93:b0:1db:ddde:33e2 with SMTP id adf61e73a8af0-1dbddde33eamr1773122637.29.1730679683729; Sun, 03 Nov 2024 16:21:23 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:23 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora Subject: [PULL 36/67] target/ppc: optimize hreg_compute_pmu_hflags_value Date: Mon, 4 Nov 2024 10:18:25 +1000 Message-ID: <20241104001900.682660-37-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=npiggin@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple conditions to avoid multiple indirect accesses. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/helper_regs.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index fe543ab3b8..7b23e5ef0e 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -83,15 +83,16 @@ static bool hreg_check_bhrb_enable(CPUPPCState *env) static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env) { uint32_t hflags = 0; - #if defined(TARGET_PPC64) - if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) { + target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; + + if (mmcr0 & MMCR0_PMCC0) { hflags |= 1 << HFLAGS_PMCC0; } - if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { + if (mmcr0 & MMCR0_PMCC1) { hflags |= 1 << HFLAGS_PMCC1; } - if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) { + if (mmcr0 & MMCR0_PMCjCE) { hflags |= 1 << HFLAGS_PMCJCE; } if (hreg_check_bhrb_enable(env)) { From patchwork Mon Nov 4 00:18:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BB72D11198 for ; Mon, 4 Nov 2024 00:25:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kqb-0004HM-95; Sun, 03 Nov 2024 19:21:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqY-0003wP-Ge; Sun, 03 Nov 2024 19:21:30 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kqX-0002hH-0i; Sun, 03 Nov 2024 19:21:30 -0500 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-720cb6ac25aso2512745b3a.3; Sun, 03 Nov 2024 16:21:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679687; x=1731284487; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8tRnHn0imyDgzIBjiEWjpE9f1p8r45aL3qXvb+TAFyY=; b=hUxB8Oo0myL+52D5nNLtn/AWiH7W83P9DrW+Pbq4DGf7OGr/Ej4uZV2D+LxfLT+mtq tLij58Sl0oN4st8/kNy3JmbqaeWU7tJvfN1rOcSgFUiDJiQdrFMi1U1eRlJxa2V5LPSj bxwK6NoKt6s+KXAinWdqardSm6lt5l2jwcQHPrveplg12DH5AQwCgGHR0aQ5wR0Lzclf T526TeE2TXK0Pdw+UK0zcDX/qk2OOq2NceN27OhxeaXMHCCseC2eUjcXqScaf7hGFmgZ nbGL3H9i35n16qOhVunO4GkJS61Mz45SPpb6lg+zB53cr7MfEAL9KEZiIJ8blU1hkGl8 eDrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679687; x=1731284487; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8tRnHn0imyDgzIBjiEWjpE9f1p8r45aL3qXvb+TAFyY=; b=snBFRq3QTHtvogaVwy8NjwBhVDYuZYY8l/YMGZ98xgd9MbCW2GCvSOSDyB5/4vOVtf KptAxAQhkAxc/jWiazFAihMOQDF8BYiXisZVwo3x9ZWSBMob/P+cdR/A9grQyP4Lg87k MHRd+5i51A4Bmo/7kk/PvYQT1+cXP9sj8G7T9RrTX0gG7hkkayPkJe3GbKDIvqW4fVM3 5M3XLhUMbSmkK0m+qgEIoxmMvZL2ycVYrLGcpX84TrYc3Og4pjtlWN5bFk8qyJaUl1zA 9+7oX1a5ha14AC5MQLh98UQehE0Y3daz8iD1a5j2CovLKKeETNm9CJ8ZWdm2LoA26LJV Av0g== X-Forwarded-Encrypted: i=1; AJvYcCWcTIuivwwzX3pxLvdygebl5oRGOReYJBR9sL+BDuuAQw6bTYImp+nRKAFf/dFDojG2WJytamdIpA==@nongnu.org X-Gm-Message-State: AOJu0Yy4wKkioLyk1PZQl3l0UL0wScM4zRy8kDJhOyG1+ROWMZ//64tu e+DQEL/iZJ8yBNyXV9GRgJJrrq9p5yqBBbxrmVT99B48OFw9+Oa5/Oy1Tw== X-Google-Smtp-Source: AGHT+IFWApGiOfcYHz7vbNEMDbivSTmM0vv9xkOlR9XzcOoLYP+i6KY1cIDQoxmrJYGB/BDxqUpFYg== X-Received: by 2002:a05:6a21:2d87:b0:1d8:fbf3:a9ac with SMTP id adf61e73a8af0-1d9a83a998cmr43381238637.2.1730679687155; Sun, 03 Nov 2024 16:21:27 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:26 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , BALATON Zoltan Subject: [PULL 37/67] target/ppc: optimize hreg_compute_pmu_hflags_value Date: Mon, 4 Nov 2024 10:18:26 +1000 Message-ID: <20241104001900.682660-38-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora The second if-condition can be true only if the first one above is true. Enclose the latter into the former to avoid un-necessary check if first condition fails. Reviewed-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/helper_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 7b23e5ef0e..42c681ca4a 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -102,9 +102,9 @@ static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env) #ifndef CONFIG_USER_ONLY if (env->pmc_ins_cnt) { hflags |= 1 << HFLAGS_INSN_CNT; - } - if (env->pmc_ins_cnt & 0x1e) { - hflags |= 1 << HFLAGS_PMC_OTHER; + if (env->pmc_ins_cnt & 0x1e) { + hflags |= 1 << HFLAGS_PMC_OTHER; + } } #endif #endif From patchwork Mon Nov 4 00:18:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB8A1D11194 for ; Mon, 4 Nov 2024 00:24:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kqf-0004ry-6H; Sun, 03 Nov 2024 19:21:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqc-0004Vn-4N; Sun, 03 Nov 2024 19:21:34 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kqa-0002ha-1X; Sun, 03 Nov 2024 19:21:33 -0500 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-720be27db27so2796065b3a.2; Sun, 03 Nov 2024 16:21:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679690; x=1731284490; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hk9/ow9qEkX2Sb6yKS/2UXPFU8j93Otp3AOGck8SdW4=; b=BrW36wNh2EoP505JfYlI/tflUBrnZ1MiPRWwKo/azcgpoho0LYVNJfzkw8JffW3Qfk +ygbyVDEg9utHbD4iwVogkL6X2o2EkCSiH/1ycamSuUvhkPm2uFD+3UE4vntJe4JjfCN IzLJVKBUPRx/HhD059jDnhu2lqSXDJNxiYqBOebO2Y7dJDhehH+Iu78zXjCiqljrM4k9 /V8vEwmKUPEcAxgiqkbCAaOuIphLmIWOggdTFBprBQNXqEszSo6ftj94csUah/ZmntkX wsiA+/Sq+BCZI7RUlcFqO1Lr0fJ4Tz03g0upaRgdIJUu6C3ms424vBvQYYhEUTJAOp/3 q6uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679690; x=1731284490; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hk9/ow9qEkX2Sb6yKS/2UXPFU8j93Otp3AOGck8SdW4=; b=gkJu6WdfMke9Y6L62QhrSIORRN9TvHQFQEa0zHPqGYEbN8uOjFu+def4a2ZNBBncet JyCW/9Sa7jN7Bpu/CzR+NNWJXoZrrCKCbBLJXxo4D1MicSo/0JujoL8tVDGQtJvu8ogP yu7mvamjEKajEBUsdN4kWkfCI3sYynx6pR7Yq1KWk2SK6CmFudfZutHUgyjoB5Z5ef5l 0nYva+MZ37EGNmt6SzYBVoEMRF6j+Mi4dk2R62t8asWp8PxXTnzB70Wr+lVEIDy1h0hn PPhOZjbss4hcnU0IyBLpeVPt9/wEUo6jgLDf5JbQJ31h1U3uqgmekULHYVhg5iWVx3DU 9Q5g== X-Forwarded-Encrypted: i=1; AJvYcCVwu4Xq8kUDG2wISEPZs4LM0capyio5ZDEz4eVNagJ6h5XuhhSZaeJqcWAWzcg/uVJECgSbGtjJSA==@nongnu.org X-Gm-Message-State: AOJu0YwydZ7NEd62mE7NfNgAfJCG9pM/Wpa5AvmVTZjlnlTiWnrMXgWY KecPT/pAMa3WQVELZ0P0J2Gyi/o6dbNou3ShBpaUZ2gWrWlCvge8PPtbDw== X-Google-Smtp-Source: AGHT+IEF88Z39pRiQO77pQ+fovJrXNzw36tKehMCLcqaLVSDl/WlJPMiKLscc/I06nLiScH713U4Aw== X-Received: by 2002:a05:6a20:1589:b0:1db:d7d2:786d with SMTP id adf61e73a8af0-1dbd7d278d1mr3136173637.6.1730679689978; Sun, 03 Nov 2024 16:21:29 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:29 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora Subject: [PULL 38/67] target/ppc: optimize p9 exception handling routines Date: Mon, 4 Nov 2024 10:18:27 +1000 Message-ID: <20241104001900.682660-39-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Currently, p9 exception handling has multiple if-condition checks where it does an indirect access to pending_interrupts and LPCR via env. Pass the values during entry to avoid multiple indirect accesses. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 72 ++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 33 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 087235bd62..7074e6c894 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1872,60 +1872,65 @@ static int p8_next_unmasked_interrupt(CPUPPCState *env) PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \ PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM) -static int p9_interrupt_powersave(CPUPPCState *env) +static int p9_interrupt_powersave(CPUPPCState *env, + uint32_t pending_interrupts, + target_ulong lpcr) { + /* External Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && - (env->spr[SPR_LPCR] & LPCR_EEE)) { - bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if ((pending_interrupts & PPC_INTERRUPT_EXT) && + (lpcr & LPCR_EEE)) { + bool heic = !!(lpcr & LPCR_HEIC); if (!heic || !FIELD_EX64_HV(env->msr) || FIELD_EX64(env->msr, MSR, PR)) { return PPC_INTERRUPT_EXT; } } /* Decrementer Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && - (env->spr[SPR_LPCR] & LPCR_DEE)) { + if ((pending_interrupts & PPC_INTERRUPT_DECR) && + (lpcr & LPCR_DEE)) { return PPC_INTERRUPT_DECR; } /* Machine Check or Hypervisor Maintenance Exception */ - if (env->spr[SPR_LPCR] & LPCR_OEE) { - if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + if (lpcr & LPCR_OEE) { + if (pending_interrupts & PPC_INTERRUPT_MCK) { return PPC_INTERRUPT_MCK; } - if (env->pending_interrupts & PPC_INTERRUPT_HMI) { + if (pending_interrupts & PPC_INTERRUPT_HMI) { return PPC_INTERRUPT_HMI; } } /* Privileged Doorbell Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && - (env->spr[SPR_LPCR] & LPCR_PDEE)) { + if ((pending_interrupts & PPC_INTERRUPT_DOORBELL) && + (lpcr & LPCR_PDEE)) { return PPC_INTERRUPT_DOORBELL; } /* Hypervisor Doorbell Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && - (env->spr[SPR_LPCR] & LPCR_HDEE)) { + if ((pending_interrupts & PPC_INTERRUPT_HDOORBELL) && + (lpcr & LPCR_HDEE)) { return PPC_INTERRUPT_HDOORBELL; } /* Hypervisor virtualization exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && - (env->spr[SPR_LPCR] & LPCR_HVEE)) { + if ((pending_interrupts & PPC_INTERRUPT_HVIRT) && + (lpcr & LPCR_HVEE)) { return PPC_INTERRUPT_HVIRT; } - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + if (pending_interrupts & PPC_INTERRUPT_RESET) { return PPC_INTERRUPT_RESET; } return 0; } -static int p9_next_unmasked_interrupt(CPUPPCState *env) +static int p9_next_unmasked_interrupt(CPUPPCState *env, + uint32_t pending_interrupts, + target_ulong lpcr) { CPUState *cs = env_cpu(env); /* Ignore MSR[EE] when coming out of some power management states */ bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; - assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0); + assert((pending_interrupts & P9_UNUSED_INTERRUPTS) == 0); if (cs->halted) { if (env->spr[SPR_PSSCR] & PSSCR_EC) { @@ -1933,7 +1938,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env) * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can * wakeup the processor */ - return p9_interrupt_powersave(env); + return p9_interrupt_powersave(env, pending_interrupts, lpcr); } else { /* * When it's clear, any system-caused exception exits power-saving @@ -1944,14 +1949,14 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env) } /* Machine check exception */ - if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + if (pending_interrupts & PPC_INTERRUPT_MCK) { return PPC_INTERRUPT_MCK; } /* Hypervisor decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { + if (pending_interrupts & PPC_INTERRUPT_HDECR) { /* LPCR will be clear when not supported so this will work */ - bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); + bool hdice = !!(lpcr & LPCR_HDICE); if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ return PPC_INTERRUPT_HDECR; @@ -1959,18 +1964,18 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env) } /* Hypervisor virtualization interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { + if (pending_interrupts & PPC_INTERRUPT_HVIRT) { /* LPCR will be clear when not supported so this will work */ - bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); + bool hvice = !!(lpcr & LPCR_HVICE); if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) { return PPC_INTERRUPT_HVIRT; } } /* External interrupt can ignore MSR:EE under some circumstances */ - if (env->pending_interrupts & PPC_INTERRUPT_EXT) { - bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (pending_interrupts & PPC_INTERRUPT_EXT) { + bool lpes0 = !!(lpcr & LPCR_LPES0); + bool heic = !!(lpcr & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || @@ -1980,20 +1985,20 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env) } if (msr_ee != 0) { /* Decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + if (pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; } - if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { + if (pending_interrupts & PPC_INTERRUPT_DOORBELL) { return PPC_INTERRUPT_DOORBELL; } - if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { + if (pending_interrupts & PPC_INTERRUPT_HDOORBELL) { return PPC_INTERRUPT_HDOORBELL; } - if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + if (pending_interrupts & PPC_INTERRUPT_PERFM) { return PPC_INTERRUPT_PERFM; } /* EBB exception */ - if (env->pending_interrupts & PPC_INTERRUPT_EBB) { + if (pending_interrupts & PPC_INTERRUPT_EBB) { /* * EBB exception must be taken in problem state and * with BESCR_GE set. @@ -2020,7 +2025,8 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env) case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: case POWERPC_EXCP_POWER11: - return p9_next_unmasked_interrupt(env); + return p9_next_unmasked_interrupt(env, env->pending_interrupts, + env->spr[SPR_LPCR]); default: break; } From patchwork Mon Nov 4 00:18:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57F86D1119B for ; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:32 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora Subject: [PULL 39/67] target/ppc: optimize p8 exception handling routines Date: Mon, 4 Nov 2024 10:18:28 +1000 Message-ID: <20241104001900.682660-40-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=npiggin@gmail.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Most of the p8 exception handling accesses env->pending_interrupts and env->spr[SPR_LPCR] at multiple places. Passing it directly as local variables simplifies the code and avoids multiple indirect accesses. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 60 +++++++++++++++++++++------------------- 1 file changed, 32 insertions(+), 28 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7074e6c894..38733b7521 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1765,39 +1765,42 @@ static int p7_next_unmasked_interrupt(CPUPPCState *env) PPC_INTERRUPT_CEXT | PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | \ PPC_INTERRUPT_FIT | PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM) -static int p8_interrupt_powersave(CPUPPCState *env) +static int p8_interrupt_powersave(uint32_t pending_interrupts, + target_ulong lpcr) { - if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { + if ((pending_interrupts & PPC_INTERRUPT_EXT) && + (lpcr & LPCR_P8_PECE2)) { return PPC_INTERRUPT_EXT; } - if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { + if ((pending_interrupts & PPC_INTERRUPT_DECR) && + (lpcr & LPCR_P8_PECE3)) { return PPC_INTERRUPT_DECR; } - if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { + if ((pending_interrupts & PPC_INTERRUPT_MCK) && + (lpcr & LPCR_P8_PECE4)) { return PPC_INTERRUPT_MCK; } - if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { + if ((pending_interrupts & PPC_INTERRUPT_HMI) && + (lpcr & LPCR_P8_PECE4)) { return PPC_INTERRUPT_HMI; } - if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { + if ((pending_interrupts & PPC_INTERRUPT_DOORBELL) && + (lpcr & LPCR_P8_PECE0)) { return PPC_INTERRUPT_DOORBELL; } - if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { + if ((pending_interrupts & PPC_INTERRUPT_HDOORBELL) && + (lpcr & LPCR_P8_PECE1)) { return PPC_INTERRUPT_HDOORBELL; } - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + if (pending_interrupts & PPC_INTERRUPT_RESET) { return PPC_INTERRUPT_RESET; } return 0; } -static int p8_next_unmasked_interrupt(CPUPPCState *env) +static int p8_next_unmasked_interrupt(CPUPPCState *env, + uint32_t pending_interrupts, + target_ulong lpcr) { CPUState *cs = env_cpu(env); @@ -1808,18 +1811,18 @@ static int p8_next_unmasked_interrupt(CPUPPCState *env) if (cs->halted) { /* LPCR[PECE] controls which interrupts can exit power-saving mode */ - return p8_interrupt_powersave(env); + return p8_interrupt_powersave(pending_interrupts, lpcr); } /* Machine check exception */ - if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + if (pending_interrupts & PPC_INTERRUPT_MCK) { return PPC_INTERRUPT_MCK; } /* Hypervisor decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { + if (pending_interrupts & PPC_INTERRUPT_HDECR) { /* LPCR will be clear when not supported so this will work */ - bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); + bool hdice = !!(lpcr & LPCR_HDICE); if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ return PPC_INTERRUPT_HDECR; @@ -1827,9 +1830,9 @@ static int p8_next_unmasked_interrupt(CPUPPCState *env) } /* External interrupt can ignore MSR:EE under some circumstances */ - if (env->pending_interrupts & PPC_INTERRUPT_EXT) { - bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (pending_interrupts & PPC_INTERRUPT_EXT) { + bool lpes0 = !!(lpcr & LPCR_LPES0); + bool heic = !!(lpcr & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || @@ -1839,20 +1842,20 @@ static int p8_next_unmasked_interrupt(CPUPPCState *env) } if (msr_ee != 0) { /* Decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + if (pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; } - if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { + if (pending_interrupts & PPC_INTERRUPT_DOORBELL) { return PPC_INTERRUPT_DOORBELL; } - if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { + if (pending_interrupts & PPC_INTERRUPT_HDOORBELL) { return PPC_INTERRUPT_HDOORBELL; } - if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + if (pending_interrupts & PPC_INTERRUPT_PERFM) { return PPC_INTERRUPT_PERFM; } /* EBB exception */ - if (env->pending_interrupts & PPC_INTERRUPT_EBB) { + if (pending_interrupts & PPC_INTERRUPT_EBB) { /* * EBB exception must be taken in problem state and * with BESCR_GE set. @@ -2021,7 +2024,8 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env) case POWERPC_EXCP_POWER7: return p7_next_unmasked_interrupt(env); case POWERPC_EXCP_POWER8: - return p8_next_unmasked_interrupt(env); + return p8_next_unmasked_interrupt(env, env->pending_interrupts, + env->spr[SPR_LPCR]); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: case POWERPC_EXCP_POWER11: From patchwork Mon Nov 4 00:18:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC7E6D11199 for ; Mon, 4 Nov 2024 00:25:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7kr9-0005Nk-Fx; Sun, 03 Nov 2024 19:22:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqi-00052b-LW; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:36 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora Subject: [PULL 40/67] target/ppc: optimize p7 exception handling routines Date: Mon, 4 Nov 2024 10:18:29 +1000 Message-ID: <20241104001900.682660-41-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Like p8 and p9, simplifying p7 exception handling rotuines to avoid un-necessary multiple indirect accesses to env->pending_interrupts and env->spr[SPR_LPCR]. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 46 ++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 38733b7521..8d2e880c83 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1683,51 +1683,54 @@ void ppc_cpu_do_interrupt(CPUState *cs) PPC_INTERRUPT_PIT | PPC_INTERRUPT_DOORBELL | PPC_INTERRUPT_HDOORBELL | \ PPC_INTERRUPT_THERM | PPC_INTERRUPT_EBB) -static int p7_interrupt_powersave(CPUPPCState *env) +static int p7_interrupt_powersave(uint32_t pending_interrupts, + target_ulong lpcr) { - if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { + if ((pending_interrupts & PPC_INTERRUPT_EXT) && + (lpcr & LPCR_P7_PECE0)) { return PPC_INTERRUPT_EXT; } - if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { + if ((pending_interrupts & PPC_INTERRUPT_DECR) && + (lpcr & LPCR_P7_PECE1)) { return PPC_INTERRUPT_DECR; } - if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { + if ((pending_interrupts & PPC_INTERRUPT_MCK) && + (lpcr & LPCR_P7_PECE2)) { return PPC_INTERRUPT_MCK; } - if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { + if ((pending_interrupts & PPC_INTERRUPT_HMI) && + (lpcr & LPCR_P7_PECE2)) { return PPC_INTERRUPT_HMI; } - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + if (pending_interrupts & PPC_INTERRUPT_RESET) { return PPC_INTERRUPT_RESET; } return 0; } -static int p7_next_unmasked_interrupt(CPUPPCState *env) +static int p7_next_unmasked_interrupt(CPUPPCState *env, + uint32_t pending_interrupts, + target_ulong lpcr) { CPUState *cs = env_cpu(env); /* Ignore MSR[EE] when coming out of some power management states */ bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; - assert((env->pending_interrupts & P7_UNUSED_INTERRUPTS) == 0); + assert((pending_interrupts & P7_UNUSED_INTERRUPTS) == 0); if (cs->halted) { /* LPCR[PECE] controls which interrupts can exit power-saving mode */ - return p7_interrupt_powersave(env); + return p7_interrupt_powersave(pending_interrupts, lpcr); } /* Machine check exception */ - if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + if (pending_interrupts & PPC_INTERRUPT_MCK) { return PPC_INTERRUPT_MCK; } /* Hypervisor decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { + if (pending_interrupts & PPC_INTERRUPT_HDECR) { /* LPCR will be clear when not supported so this will work */ bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { @@ -1737,9 +1740,9 @@ static int p7_next_unmasked_interrupt(CPUPPCState *env) } /* External interrupt can ignore MSR:EE under some circumstances */ - if (env->pending_interrupts & PPC_INTERRUPT_EXT) { - bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (pending_interrupts & PPC_INTERRUPT_EXT) { + bool lpes0 = !!(lpcr & LPCR_LPES0); + bool heic = !!(lpcr & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || @@ -1749,10 +1752,10 @@ static int p7_next_unmasked_interrupt(CPUPPCState *env) } if (msr_ee != 0) { /* Decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + if (pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; } - if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + if (pending_interrupts & PPC_INTERRUPT_PERFM) { return PPC_INTERRUPT_PERFM; } } @@ -2022,7 +2025,8 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env) #ifdef TARGET_PPC64 switch (env->excp_model) { case POWERPC_EXCP_POWER7: - return p7_next_unmasked_interrupt(env); + return p7_next_unmasked_interrupt(env, env->pending_interrupts, + env->spr[SPR_LPCR]); case POWERPC_EXCP_POWER8: return p8_next_unmasked_interrupt(env, env->pending_interrupts, env->spr[SPR_LPCR]); From patchwork Mon Nov 4 00:18:30 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:39 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora Subject: [PULL 41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt Date: Mon, 4 Nov 2024 10:18:30 +1000 Message-ID: <20241104001900.682660-42-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=npiggin@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora As previously done for arch specific handlers, simplify var usage in ppc_next_unmasked_interrupt by caching the env->pending_interrupts and env->spr[SPR_LPCR] in local vars and using it later at multiple places. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 54 ++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 8d2e880c83..2806afd9bd 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2022,31 +2022,31 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env, static int ppc_next_unmasked_interrupt(CPUPPCState *env) { + uint32_t pending_interrupts = env->pending_interrupts; + target_ulong lpcr = env->spr[SPR_LPCR]; + bool async_deliver; + #ifdef TARGET_PPC64 switch (env->excp_model) { case POWERPC_EXCP_POWER7: - return p7_next_unmasked_interrupt(env, env->pending_interrupts, - env->spr[SPR_LPCR]); + return p7_next_unmasked_interrupt(env, pending_interrupts, lpcr); case POWERPC_EXCP_POWER8: - return p8_next_unmasked_interrupt(env, env->pending_interrupts, - env->spr[SPR_LPCR]); + return p8_next_unmasked_interrupt(env, pending_interrupts, lpcr); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: case POWERPC_EXCP_POWER11: - return p9_next_unmasked_interrupt(env, env->pending_interrupts, - env->spr[SPR_LPCR]); + return p9_next_unmasked_interrupt(env, pending_interrupts, lpcr); default: break; } #endif - bool async_deliver; /* External reset */ - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + if (pending_interrupts & PPC_INTERRUPT_RESET) { return PPC_INTERRUPT_RESET; } /* Machine check exception */ - if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + if (pending_interrupts & PPC_INTERRUPT_MCK) { return PPC_INTERRUPT_MCK; } #if 0 /* TODO */ @@ -2065,9 +2065,9 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env) async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; /* Hypervisor decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { + if (pending_interrupts & PPC_INTERRUPT_HDECR) { /* LPCR will be clear when not supported so this will work */ - bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); + bool hdice = !!(lpcr & LPCR_HDICE); if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ return PPC_INTERRUPT_HDECR; @@ -2075,18 +2075,18 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env) } /* Hypervisor virtualization interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { + if (pending_interrupts & PPC_INTERRUPT_HVIRT) { /* LPCR will be clear when not supported so this will work */ - bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); + bool hvice = !!(lpcr & LPCR_HVICE); if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { return PPC_INTERRUPT_HVIRT; } } /* External interrupt can ignore MSR:EE under some circumstances */ - if (env->pending_interrupts & PPC_INTERRUPT_EXT) { - bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (pending_interrupts & PPC_INTERRUPT_EXT) { + bool lpes0 = !!(lpcr & LPCR_LPES0); + bool heic = !!(lpcr & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || @@ -2096,45 +2096,45 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env) } if (FIELD_EX64(env->msr, MSR, CE)) { /* External critical interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { + if (pending_interrupts & PPC_INTERRUPT_CEXT) { return PPC_INTERRUPT_CEXT; } } if (async_deliver != 0) { /* Watchdog timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_WDT) { + if (pending_interrupts & PPC_INTERRUPT_WDT) { return PPC_INTERRUPT_WDT; } - if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { + if (pending_interrupts & PPC_INTERRUPT_CDOORBELL) { return PPC_INTERRUPT_CDOORBELL; } /* Fixed interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_FIT) { + if (pending_interrupts & PPC_INTERRUPT_FIT) { return PPC_INTERRUPT_FIT; } /* Programmable interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_PIT) { + if (pending_interrupts & PPC_INTERRUPT_PIT) { return PPC_INTERRUPT_PIT; } /* Decrementer exception */ - if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + if (pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; } - if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { + if (pending_interrupts & PPC_INTERRUPT_DOORBELL) { return PPC_INTERRUPT_DOORBELL; } - if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { + if (pending_interrupts & PPC_INTERRUPT_HDOORBELL) { return PPC_INTERRUPT_HDOORBELL; } - if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + if (pending_interrupts & PPC_INTERRUPT_PERFM) { return PPC_INTERRUPT_PERFM; } /* Thermal interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_THERM) { + if (pending_interrupts & PPC_INTERRUPT_THERM) { return PPC_INTERRUPT_THERM; } /* EBB exception */ - if (env->pending_interrupts & PPC_INTERRUPT_EBB) { + if (pending_interrupts & PPC_INTERRUPT_EBB) { /* * EBB exception must be taken in problem state and * with BESCR_GE set. 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:43 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora Subject: [PULL 42/67] target/ppc: combine multiple ail checks into one Date: Mon, 4 Nov 2024 10:18:31 +1000 Message-ID: <20241104001900.682660-43-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora ppc_excp_apply_ail has multiple if-checks for ail which is un-necessary. Combine them as appropriate. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2806afd9bd..70daa5076a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -324,10 +324,7 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr, } ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; - if (ail == 0) { - return; - } - if (ail == 1) { + if (ail == 0 || ail == 1) { /* AIL=1 is reserved, treat it like AIL=0 */ return; } @@ -351,10 +348,7 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr, } else { ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; } - if (ail == 0) { - return; - } - if (ail == 1 || ail == 2) { + if (ail == 0 || ail == 1 || ail == 2) { /* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */ return; } From patchwork Mon Nov 4 00:18:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58752D11199 for ; Mon, 4 Nov 2024 00:27:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krM-0006X6-SO; Sun, 03 Nov 2024 19:22:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kqt-0005JN-0F; Sun, 03 Nov 2024 19:21:53 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kqr-0002j2-EH; Sun, 03 Nov 2024 19:21:50 -0500 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-71e8235f0b6so3172058b3a.3; Sun, 03 Nov 2024 16:21:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679707; x=1731284507; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VvmgHv54ktpg3v0jpm0c0B4J0dywq59PujDGLDVe7UA=; b=X7bpXP5v3QTH8MzEyKTlkwNvNvdduzE5Yny3DcT+cz5skVi3uqazUUM5Z3R2zim5L6 BnVMNcNodgdvCqKVx5sbN9TZr74TolFuoXQYwxakmZ4MoUwDVcWaJlEIx3iPjMwXJN7q JlSYeZ0M6f0J4hm8wxC+HNE8ZMjEqzmcZFxvLCGVIRF82pj8CZiazoM/BX9WfaE9eTMM 502AiuBfl+UkLz9mKrpmSdYZZAR5Sb+5K25n9m6cPbVfW2jZXOL1hHm9AcvKbQz9GY8p ecNWov5wHnrlrJhwhjjsbVFon5P7U03lS+433s8zigQ61dZdB9jLrcOVOCZPdifwb4jF 9g3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679707; x=1731284507; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VvmgHv54ktpg3v0jpm0c0B4J0dywq59PujDGLDVe7UA=; b=VeCeyfn2eP6sEo/gjfoV6rD6ZTZF60bOFjz0dXHoEnC8XGaZZJotunGjGRDvSvj9EW Mh1QexiNSNPS30f5gg+Dsc0DvWrdM5yh1xCq4iT+2vFBA6Tue5ZjHzYE3Zq9xPu9CG8u bSWwU6EHFxG9lJmKGN+0+59xJTLBkwwB1CE3IWwmEymT5Sq2L0SyhJkbTWTdDTPl8rfr 3tPaA7V5D+3mJSp5rsXhERTv98YjYdVrZvur3lYL95e6YObNtBS/scdqIb7SkSrEQsKb pxSv+kh/hsbpV6NBd9zsEMVUYlSrro3360VjvFbfrrtOqhtdVXcV9F/QrWqP5p9nESS6 JkRQ== X-Forwarded-Encrypted: i=1; AJvYcCXQLF+XKwc9KGfIwY3zyLjyYZ2GEibKS8h5paPUKmoo5/xEE/ArLEGPDuvbulF/vYGhSm2DX1ZWeQ==@nongnu.org X-Gm-Message-State: AOJu0YwCqUq6SLsGSBhSgJ36/kS71TzArhfBCzLi+MPh0n7SFiH6+R4j 6vezwWGJZMnpTHshJJozM4NJQTJ3wp1TCADStb6lSO4xqCRbUQ06Wn0xJw== X-Google-Smtp-Source: AGHT+IHf2k2rFyKx/oYDd7VKNMJgZb18H0K+eAXGkNorltp9PjXmDXj8nAOqVPEQXFt64Av2EZYsww== X-Received: by 2002:a05:6a00:10cd:b0:71e:634e:fe0d with SMTP id d2e1a72fcca58-720b9c05526mr21510104b3a.12.1730679706971; Sun, 03 Nov 2024 16:21:46 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:46 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , Harsh Prateek Bora Subject: [PULL 43/67] target/ppc: reduce duplicate code between init_proc_POWER{9, 10} Date: Mon, 4 Nov 2024 10:18:32 +1000 Message-ID: <20241104001900.682660-44-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora Historically, the registration of sprs have been inherited alongwith every new Power arch support being added leading to a lot of code duplication. It's time to do necessary cleanups now to avoid further duplication with newer arch support being added. Signed-off-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 58 +++++++++---------------------------------- 1 file changed, 12 insertions(+), 46 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c26e5b269c..6f352550db 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6410,7 +6410,7 @@ static struct ppc_radix_page_info POWER9_radix_page_info = { #endif /* CONFIG_USER_ONLY */ #define POWER9_BHRB_ENTRIES_LOG2 5 -static void init_proc_POWER9(CPUPPCState *env) +static void register_power9_common_sprs(CPUPPCState *env) { /* Common Registers */ init_proc_book3s_common(env); @@ -6429,7 +6429,6 @@ static void init_proc_POWER9(CPUPPCState *env) register_power5p_ear_sprs(env); register_power5p_tb_sprs(env); register_power6_common_sprs(env); - register_HEIR32_spr(env); register_power6_dbg_sprs(env); register_power7_common_sprs(env); register_power8_tce_address_control_sprs(env); @@ -6447,16 +6446,21 @@ static void init_proc_POWER9(CPUPPCState *env) register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); - /* POWER9 Specific registers */ - spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, - spr_read_generic, spr_write_generic, - KVM_REG_PPC_TIDR, 0); - /* FIXME: Filter fields properly based on privilege level */ spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, spr_read_generic, spr_write_generic, KVM_REG_PPC_PSSCR, 0); +} + +static void init_proc_POWER9(CPUPPCState *env) +{ + register_power9_common_sprs(env); + register_HEIR32_spr(env); + /* POWER9 Specific registers */ + spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_TIDR, 0); /* env variables */ env->dcache_line_size = 128; env->icache_line_size = 128; @@ -6562,50 +6566,12 @@ static struct ppc_radix_page_info POWER10_radix_page_info = { #define POWER10_BHRB_ENTRIES_LOG2 5 static void init_proc_POWER10(CPUPPCState *env) { - /* Common Registers */ - init_proc_book3s_common(env); - register_book3s_207_dbg_sprs(env); - - /* Common TCG PMU */ - init_tcg_pmu_power8(env); - - /* POWER8 Specific Registers */ - register_book3s_ids_sprs(env); - register_amr_sprs(env); - register_iamr_sprs(env); - register_book3s_purr_sprs(env); - register_power5p_common_sprs(env); - register_power5p_lpar_sprs(env); - register_power5p_ear_sprs(env); - register_power5p_tb_sprs(env); - register_power6_common_sprs(env); + register_power9_common_sprs(env); register_HEIR64_spr(env); - register_power6_dbg_sprs(env); - register_power7_common_sprs(env); - register_power8_tce_address_control_sprs(env); - register_power8_ids_sprs(env); - register_power8_ebb_sprs(env); - register_power8_fscr_sprs(env); - register_power8_pmu_sup_sprs(env); - register_power8_pmu_user_sprs(env); - register_power8_tm_sprs(env); - register_power8_pspb_sprs(env); - register_power8_dpdes_sprs(env); - register_vtb_sprs(env); - register_power8_ic_sprs(env); - register_power9_book4_sprs(env); - register_power8_rpr_sprs(env); - register_power9_mmu_sprs(env); register_power10_hash_sprs(env); register_power10_dexcr_sprs(env); register_power10_pmu_sup_sprs(env); register_power10_pmu_user_sprs(env); - - /* FIXME: Filter fields properly based on privilege level */ - spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, - spr_read_generic, spr_write_generic, - KVM_REG_PPC_PSSCR, 0); - /* env variables */ env->dcache_line_size = 128; env->icache_line_size = 128; From patchwork Mon Nov 4 00:18:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F239D11199 for ; Mon, 4 Nov 2024 00:30:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krI-00062l-4s; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:50 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Amit Machhiwal , Harsh Prateek Bora Subject: [PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0 Date: Mon, 4 Nov 2024 10:18:33 +1000 Message-ID: <20241104001900.682660-45-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Amit Machhiwal The DPDES support for doorbell emulation and handling for KVM on PAPR guests was added in Linux via [1]. Subsequently, a new GSB (Guest State Buffer) element for DPDES was added in Linux; the same has been missing in TCG L0 implementation. Add support for DPDES register's APIv2 GSB element and required handling in `spapr_nested.c`. Currently, booting a KVM guest inside a QEMU TCG guest fails with the following crash. The crash occurs while handling the GUEST_RUN_VCPU hcall made in TCG L0. In the hcall handling path, map_and_getset_state() calls getset_state(), which, in turn, calls guest_state_request_check() to validate the GSR (Guest State Request) elements. During this process, guest_state_request_check() iterates over the GSR elements and receives a NULL return code from guest_state_element_type_find() for the type variable corresponding to the DPDES register's elemetn ID (which was unknown to TCG L0). Subsequently, getset_state() returns H_P3, ultimately leading to the hcall failure and causing the KVM guest to crash. KVM: unknown exit, hardware reason ffffffffffffffea [ ... KVM register dump ... ] Fix this by adding the required support in TCG L0 implementation of APIv2. [1] https://lore.kernel.org/all/20240605113913.83715-1-gautam@linux.ibm.com/ Fixes: 4a575f9a0567 ("spapr: nested: Initialize the GSB elements lookup table.") Suggested-by: Harsh Prateek Bora Signed-off-by: Amit Machhiwal Reviewed-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_nested.c | 1 + include/hw/ppc/spapr_nested.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index c02785756c..1b41c8fb8b 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -982,6 +982,7 @@ struct guest_state_element_type guest_state_element_types[] = { GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FSCR, fscr), GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PSPB, pspb), GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTRL, ctrl), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DPDES, dpdes), GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_VRSAVE, vrsave), GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAR, dar), GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DSISR, dsisr), diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index 93ef14adcc..3b5cd993c2 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -99,7 +99,8 @@ #define GSB_VCPU_SPR_HASHKEYR 0x1050 #define GSB_VCPU_SPR_HASHPKEYR 0x1051 #define GSB_VCPU_SPR_CTRL 0x1052 - /* RESERVED 0x1053 - 0x1FFF */ +#define GSB_VCPU_SPR_DPDES 0x1053 + /* RESERVED 0x1054 - 0x1FFF */ #define GSB_VCPU_SPR_CR 0x2000 #define GSB_VCPU_SPR_PIDR 0x2001 #define GSB_VCPU_SPR_DSISR 0x2002 From patchwork Mon Nov 4 00:18:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA13DD11194 for ; Mon, 4 Nov 2024 00:25:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krG-0005vB-Lx; Sun, 03 Nov 2024 19:22:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kr2-0005Mu-0t; Sun, 03 Nov 2024 19:22:02 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kqy-0002jT-NY; Sun, 03 Nov 2024 19:21:58 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-20cf3e36a76so37722515ad.0; Sun, 03 Nov 2024 16:21:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679714; x=1731284514; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CcJfhU/kdfOpvzZk2Pu8ysuvtr/X2+No2KDA3lj866Y=; b=baoWgxLcJkdePD2Y6e3Pw3g4PU3UE0iCvai0KccXIModoZM/v/pKmSzUQSoQ6M0dBI UgEKmv+i98mNNg7Ii5wwDVXg3ZWxfCZh7wwKl5BcgClYEJqn92YfixuSGBt2XdnYb/8g Y4isFQ4EOYeoFvEjkHhbOF/BdnJryBfubSp4GSmw7nDW6epJMP1YSxEem+Lx7Bmx0XBr EKN+40A0II6YMKHfxpt9r4X5R1Xtax3tdSzDScIfwLD+GqdGaj3jPWh2SxBFbO7CfPYk KdE06fgn835/A0UW2Sq+u64Sh7seZooQf3uCTjvGyEWfei0fpPmfcbVlHvd8b6tMRVkM uM+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679714; x=1731284514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CcJfhU/kdfOpvzZk2Pu8ysuvtr/X2+No2KDA3lj866Y=; b=Fn4gUtCQAlb5+zJIvufL72/vxp+1FxY8y72CKhhDuezZpPayD5clG17JSv4lnplzFZ PctE3yoK8qhng1iwckTsNd+sZc4jlNlBW4nHm8K09TPx9F3BAcdU98cloQrNdbWhHyns wRuKrFZ5YHwMZaRgEpiCu5BilJ4atAXM7w1MOYMYHU1t6Ertrc/XLdsYt208z2aiMw7B xAvfYIU5xChz+VQfsLxLTER+t+XhRePUCXmhQNgtLIhMnIqho6h0DRxXQ40XJL2EmvYM aKcXDW7tEQWQD3sjUbraBiZjoK29noeyLBoubBNhYMiWg8JTugBwcaII6WwC1jjf6uy/ TMRQ== X-Forwarded-Encrypted: i=1; AJvYcCVDpTRjN0maltvY4iqyzcovSfl3voWJjEkrsV6WqJtWB3fYeJShHffEikNuP+1gauehsd6Lz3QpjA==@nongnu.org X-Gm-Message-State: AOJu0YxVVewcAoZ1wjSAb0uB45d4w3S3DCCnKWaNFf4oIYdBWchUg/Fd TWNSNMq050WGt7mK0rLXqgLQVbbfJIPN6dBqK27Y/IePk/XtbowKBMc4tQ== X-Google-Smtp-Source: AGHT+IFLJTsKs5H2153MomdXH25od4HS8DPgc+ZaTG8Bz9bkFvI0CKPtGn6hyRU1Qctk5REOmfA4kw== X-Received: by 2002:a17:902:f68f:b0:20c:8839:c515 with SMTP id d9443c01a7336-21103ca485bmr199758095ad.56.1730679713633; Sun, 03 Nov 2024 16:21:53 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:53 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Amit Machhiwal Subject: [PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0 Date: Mon, 4 Nov 2024 10:18:34 +1000 Message-ID: <20241104001900.682660-46-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Amit Machhiwal The Power11 architected and raw mode support in Linux was merged via [1] and the corresponding support in QEMU is waiting to be added by [2] which in V6 currently. Add the Power11 capabilities and the required handling in TCG L0 implementation of the "Nested PAPR API". Note: This patch is based on [2]. [1] https://lore.kernel.org/all/20240221044623.1598642-1-mpe@ellerman.id.au/ [2] https://lore.kernel.org/all/20240731055022.696051-1-adityag@linux.ibm.com/ Signed-off-by: Amit Machhiwal Signed-off-by: Nicholas Piggin --- hw/ppc/spapr_nested.c | 12 +++++++++++- include/hw/ppc/spapr_nested.h | 5 ++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 1b41c8fb8b..7def8eb73b 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -771,6 +771,7 @@ static void copy_logical_pvr(void *a, void *b, bool set) if (*pvr_logical_ptr) { switch (*pvr_logical_ptr) { + case CPU_POWERPC_LOGICAL_3_10_P11: case CPU_POWERPC_LOGICAL_3_10: pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00; break; @@ -1185,6 +1186,12 @@ static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu, return H_PARAMETER; } + /* P11 capabilities */ + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0, + spapr->max_compat_pvr)) { + env->gpr[4] |= H_GUEST_CAPABILITIES_P11_MODE; + } + /* P10 capabilities */ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, spapr->max_compat_pvr)) { @@ -1227,7 +1234,10 @@ static target_ulong h_guest_set_capabilities(PowerPCCPU *cpu, env->gpr[4] = 1; /* set R5 to the first supported Power Processor Mode */ - if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0, + spapr->max_compat_pvr)) { + env->gpr[5] = H_GUEST_CAP_P11_MODE_BMAP; + } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, spapr->max_compat_pvr)) { env->gpr[5] = H_GUEST_CAP_P10_MODE_BMAP; } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index 3b5cd993c2..e420220484 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -211,11 +211,14 @@ typedef struct SpaprMachineStateNestedGuest { #define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000 #define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000 #define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000 -#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P10_MODE | \ +#define H_GUEST_CAPABILITIES_P11_MODE 0x1000000000000000 +#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P11_MODE | \ + H_GUEST_CAPABILITIES_P10_MODE | \ H_GUEST_CAPABILITIES_P9_MODE) #define H_GUEST_CAP_COPY_MEM_BMAP 0 #define H_GUEST_CAP_P9_MODE_BMAP 1 #define H_GUEST_CAP_P10_MODE_BMAP 2 +#define H_GUEST_CAP_P11_MODE_BMAP 3 #define PAPR_NESTED_GUEST_MAX 4096 #define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL #define PAPR_NESTED_GUEST_VCPU_MAX 2048 From patchwork Mon Nov 4 00:18:35 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:56 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Aditya Gupta Subject: [PULL 46/67] hw/ppc: Implement -dtb support for PowerNV Date: Mon, 4 Nov 2024 10:18:35 +1000 Message-ID: <20241104001900.682660-47-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Aditya Gupta Currently any device tree passed with -dtb option in QEMU, was ignored by the PowerNV code. Read and pass the passed -dtb to the kernel, thus enabling easier debugging with custom DTBs. The existing behaviour when -dtb is 'not' passed, is preserved as-is. But when a '-dtb' is passed, it completely overrides any dtb nodes or changes QEMU might have done, such as '-append' arguments to the kernel (which are mentioned in /chosen/bootargs in the dtb), hence add warning when -dtb is being used Reviewed-by: Nicholas Piggin Signed-off-by: Aditya Gupta Signed-off-by: Nicholas Piggin --- hw/ppc/pnv.c | 51 ++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 795acc289f..f0f0d7567d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -736,21 +736,27 @@ static void pnv_reset(MachineState *machine, ResetType type) } } - fdt = pnv_dt_create(machine); - - /* Pack resulting tree */ - _FDT((fdt_pack(fdt))); + if (machine->fdt) { + fdt = machine->fdt; + } else { + fdt = pnv_dt_create(machine); + /* Pack resulting tree */ + _FDT((fdt_pack(fdt))); + } qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); - /* - * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free - * the existing machine->fdt to avoid leaking it during - * a reset. - */ - g_free(machine->fdt); - machine->fdt = fdt; + /* Update machine->fdt with latest fdt */ + if (machine->fdt != fdt) { + /* + * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free + * the existing machine->fdt to avoid leaking it during + * a reset. + */ + g_free(machine->fdt); + machine->fdt = fdt; + } } static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) @@ -952,6 +958,14 @@ static void pnv_init(MachineState *machine) g_free(sz); exit(EXIT_FAILURE); } + + /* checks for invalid option combinations */ + if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { + error_report("-append and -dtb cannot be used together, as passed" + " command line is ignored in case of custom dtb"); + exit(EXIT_FAILURE); + } + memory_region_add_subregion(get_system_memory(), 0, machine->ram); /* @@ -1003,6 +1017,21 @@ static void pnv_init(MachineState *machine) } } + /* load dtb if passed */ + if (machine->dtb) { + int fdt_size; + + warn_report("with manually passed dtb, some options like '-append'" + " will get ignored and the dtb passed will be used as-is"); + + /* read the file 'machine->dtb', and load it into 'fdt' buffer */ + machine->fdt = load_device_tree(machine->dtb, &fdt_size); + if (!machine->fdt) { + error_report("Could not load dtb '%s'", machine->dtb); + exit(1); + } + } + /* MSIs are supported on this platform */ msi_nonbroken = true; From patchwork Mon Nov 4 00:18:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFBB9D11198 for ; Mon, 4 Nov 2024 00:27:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krN-0006gU-O4; Sun, 03 Nov 2024 19:22:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kr5-0005Nc-BA; Sun, 03 Nov 2024 19:22:06 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kr3-0002kH-JH; Sun, 03 Nov 2024 19:22:02 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-720d14c8dbfso2325857b3a.0; Sun, 03 Nov 2024 16:22:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679719; x=1731284519; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ftki89nEYstrfFSAin/yFBIlJQIjomoZE+uZMXBkVss=; b=GvB9gOVu8LFfncOekovFH77bLyXmdcXz9QF8+wMZOWYfZVNKUbYZ0zq9Yi4MqEgHcb tWoDF8IMyjYQ1zfgOyro6+3eoPQ0YSh6KUW+Z17jwPeWOo9CSuX6h8+6PrRAu2ElSpKx oxKgcT1f3v/60nLBIPXOcDN/1D0tN3DDKks+yYaI+QXe6sGV5kTb/upmBvyfZDw3NWz1 IYZnkUPCdJNe70q4Iq94iVbfHcfA4PInJ9UQ3ThddST5fD+WHUGFPe0lEdD25sFR23sG +tUDOq3CN2KnC9R1OBVt8TEhbD3fM7iZF7vXnFxC7kc8Czrn5Ujhc162FOYtOgT07Ha8 fNtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679719; x=1731284519; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ftki89nEYstrfFSAin/yFBIlJQIjomoZE+uZMXBkVss=; b=pV1j4IIYBVqGwyR+8XDVgQ3pZ7CPljL/RDVPT2TcBo7Q/rcoFTaUrYZ1GsSHD/g/Cj uR7sXEUZxI1n1bvse1mwC+E2pS+bu7BNN1QVEDc1nvvK/eOMAHuwz9n/tv9fue9w6wWe NVZDq06QNLAYSBQ/9/kUARknAbYHD8nSxauEurnJz+UWuNQh5/3L8jahK0AuWwhWpMU6 FeGIXjN9TixnxyJoCoUPnCqsYQNglvGunPxLzEsQW/bkE4sSv3c/znefoSXFdNmBkO4u IXDcxc9jw2ITjbJjWvj6V9nsBHLhVzQ2Sh30wVWXuOnN6MXoEzfUQEE7svGtEL7h6H8A 5KGQ== X-Forwarded-Encrypted: i=1; AJvYcCU5p25Kd/4uQ4J1WG+0NmKTPj52Ro9tz7Vx2M48BUASz1fwuqeqxwr7lZYW62rLKy9VVTNzuSyk2A==@nongnu.org X-Gm-Message-State: AOJu0YwJsOl8wEzapCSphzCeK5Tirf2657cO5kmF5aWq5tmfbfm3Bl0H jCCfH1Ivnd3DI6pgYwrUScjt5tCjSX/9k26auMqZtpLw1/i80OM+aF0t3A== X-Google-Smtp-Source: AGHT+IHO1sQuIOtze6zkEGzlWozl1J1Y8MlNv5lV+kDD4mmRWTnSES24uoqlMfixeLExFDykDj9XaA== X-Received: by 2002:a05:6a21:38f:b0:1d9:282f:3d17 with SMTP id adf61e73a8af0-1db91e53617mr22126673637.35.1730679718971; Sun, 03 Nov 2024 16:21:58 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:21:58 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org Subject: [PULL 47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts Date: Mon, 4 Nov 2024 10:18:36 +1000 Message-ID: <20241104001900.682660-48-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The length of this region can be > 32-bits, which overflows size_t on 32-bit hosts. Change to uint64_t. Signed-off-by: Nicholas Piggin --- hw/intc/spapr_xive_kvm.c | 4 ++-- hw/intc/xive.c | 2 +- include/hw/ppc/xive.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 5789062379..7a86197fc9 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -720,7 +720,7 @@ int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers, { SpaprXive *xive = SPAPR_XIVE(intc); XiveSource *xsrc = &xive->source; - size_t esb_len = xive_source_esb_len(xsrc); + uint64_t esb_len = xive_source_esb_len(xsrc); size_t tima_len = 4ull << TM_SHIFT; CPUState *cs; int fd; @@ -824,7 +824,7 @@ void kvmppc_xive_disconnect(SpaprInterruptController *intc) { SpaprXive *xive = SPAPR_XIVE(intc); XiveSource *xsrc; - size_t esb_len; + uint64_t esb_len; assert(xive->fd != -1); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5a02dd8e02..b600546e78 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1242,7 +1242,7 @@ static void xive_source_reset(void *dev) static void xive_source_realize(DeviceState *dev, Error **errp) { XiveSource *xsrc = XIVE_SOURCE(dev); - size_t esb_len = xive_source_esb_len(xsrc); + uint64_t esb_len = xive_source_esb_len(xsrc); assert(xsrc->xive); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 28c181faa2..3a65c2f29a 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -218,7 +218,7 @@ static inline bool xive_source_esb_has_2page(XiveSource *xsrc) xsrc->esb_shift == XIVE_ESB_4K_2PAGE; } -static inline size_t xive_source_esb_len(XiveSource *xsrc) +static inline uint64_t xive_source_esb_len(XiveSource *xsrc) { return (1ull << xsrc->esb_shift) * xsrc->nr_irqs; } From patchwork Mon Nov 4 00:18:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4018BD11198 for ; Mon, 4 Nov 2024 00:25:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krk-000757-9B; Sun, 03 Nov 2024 19:22:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7kr8-0005OX-0J; Sun, 03 Nov 2024 19:22:06 -0500 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kr6-0002kd-7O; Sun, 03 Nov 2024 19:22:05 -0500 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-7eae96e6624so2620363a12.2; Sun, 03 Nov 2024 16:22:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679722; x=1731284522; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C3MEKvteMsJO9gub1u2YO3fvm/n2k8+R2+Pv63fB2zM=; b=PuskgmFGPMCL2ehr232AMS4vjdck4bL2qx3oBBECkj/NjKSf5fhKLWRXBhOW6ERd+r mcfpANsri7kcIt3QT1LIVHxrtgweitSSAcCdM829qcWEzOwlUko0uVHMtMS6ELqPj+VH UZfs5dG4XijHODO6LYEwsoudoiARFQQOAhKFlFtg9I/XYGjglSmm7JWs/88/sneJiqFi fxvtjsT7KTVmy/bQxHsV7rb3Pq39yMPO8x/6iUbkY8sDkmOSctf6mJYymyTmbC80DCMg TfCZtAF+XuX3gdNj07ojlp5aoDrSF6V9a18wXu4HKfOXI4TtnqNZt5X72IvoK/Lhu8Ae Acsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679722; x=1731284522; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C3MEKvteMsJO9gub1u2YO3fvm/n2k8+R2+Pv63fB2zM=; b=EgUc5GN9En8dAT2iGa2p2Rgl6w+OELRjMkpLvrApwS3KfoC4MnNaVmu72jQouOfhl1 8T+BdmLL0d49PS9jBRaCd3W4Ui9YOycfZvvEi8e+1tbDUIqQTl2rHrl7vdnHh434s8yw NRyxiONF2Kudzz9uqTEDpXLLKo3bqtU0gWDq4sXdpHhgEFSWqx0TBaJjY+jHZJqS9ROG 6pmufpBbIQ4MwvOitvyyXt/dVBLXnaY6hbPkXHF6o8fx7aidDPYbSQfgRxjYXK8yrvpV AoTX9uUA4EfgSaRCHPrSi8jybSCiGdDqF5Mb/XXZOfuf1SyrV+I69KUxbMSV91b5u6mp 859g== X-Forwarded-Encrypted: i=1; AJvYcCU3R5RhHkxAh6h8+YKUxDf3qwjpfCqJbhMBhV3b++M9W1V7QHKactTmkS0eY5/EoqZCccuIA8jczw==@nongnu.org X-Gm-Message-State: AOJu0YzhOFwf2SOsGB/P5chZ463CwufSFYYpEAH0IGgybL8AUxBN0Uco zcN0+F6MEoUfsPXGNGScLqD78M+GxdoXJRDDAC5ch2hzb7PgITMNcgN3cA== X-Google-Smtp-Source: AGHT+IFQq9UMS3vCv9msj5eYBw3B/6v6CpnuH2tH2v3mntImqxktVWDtdEQin5WqoSikJcqNZz8XMw== X-Received: by 2002:a17:903:40c9:b0:20c:c694:f6c6 with SMTP id d9443c01a7336-210c6c52417mr404540205ad.49.1730679722242; Sun, 03 Nov 2024 16:22:02 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:01 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes Date: Mon, 4 Nov 2024 10:18:37 +1000 Message-ID: <20241104001900.682660-49-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=npiggin@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Michael Kowal Making some pre-requisite alignment changes ahead of the following patch sets. Making these changes now will ease the review of the patch sets. Checkpatch wants the closing comment '*/' on a separate line, unless it is on the same line as the starting comment '/*'. There are also changes to prevent lines from spanning 80 columns. Changed block of defines from: #define A 1 /* original define comment is not * preferred, but not flagged... */ #define B 2 /* Newly added define comment * is flagged with a warning */ To: #define A 1 /* original define comment is */ /* now fine, no warning... */ #define B 2 /* Newly added define comment */ /* is fine... */ Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 72 +++++++++++++++++++++++++------------- include/hw/ppc/xive_regs.h | 32 ++++++++--------- 2 files changed, 64 insertions(+), 40 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index b600546e78..dc86a7a3be 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -488,20 +488,32 @@ static const XiveTmOp xive_tm_operations[] = { * MMIOs below 2K : raw values and special operations without side * effects */ - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, + xive_tm_vt_poll }, /* MMIOs above 2K : special operations with side effects */ - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, - { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive_tm_pull_os_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive_tm_pull_os_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, + xive_tm_ack_os_reg }, + { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, + NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, + xive_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, + xive_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, + xive_tm_ack_hv_reg }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, + xive_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, + xive_tm_pull_pool_ctx }, }; static const XiveTmOp xive2_tm_operations[] = { @@ -509,20 +521,32 @@ static const XiveTmOp xive2_tm_operations[] = { * MMIOs below 2K : raw values and special operations without side * effects */ - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, + NULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, + xive_tm_vt_poll }, /* MMIOs above 2K : special operations with side effects */ - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg }, - { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive2_tm_pull_os_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive2_tm_pull_os_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, + xive_tm_ack_os_reg }, + { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, + NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, + xive2_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, + xive2_tm_pull_os_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, + xive_tm_ack_hv_reg }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, + xive_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, + xive_tm_pull_pool_ctx }, }; static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index b9db7abc2e..9d52d464d9 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -114,23 +114,23 @@ * Then we have all these "special" CI ops at these offset that trigger * all sorts of side effects: */ -#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ -#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ +#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg */ +#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ -#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user - * context */ -#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ -#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS - * context to reg */ -#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool - * context to reg*/ -#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ -#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd - * line */ -#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ -#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even - * line */ -#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ +#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */ + /* context */ +#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ +#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */ + /* context to reg */ +#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */ + /* context to reg */ +#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ +#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ + /* line */ +#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ +#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */ + /* line */ +#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ /* XXX more... */ /* NSR fields for the various QW ack types */ From patchwork Mon Nov 4 00:18:38 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:05 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Frederic Barrat , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 49/67] pnv/xive2: Define OGEN field in the TIMA Date: Mon, 4 Nov 2024 10:18:38 +1000 Message-ID: <20241104001900.682660-50-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frederic Barrat The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This patch defines it. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 4 ++++ include/hw/ppc/xive_regs.h | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index dc86a7a3be..0e81678ab3 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -742,6 +742,10 @@ void xive_tctx_reset(XiveTCTX *tctx) tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; + if (!(xive_presenter_get_config(tctx->xptr) & + XIVE_PRESENTER_GEN1_TIMA_OS)) { + tctx->regs[TM_QW1_OS + TM_OGEN] = 2; + } /* * Initialize PIPR to 0xFF to avoid phantom interrupts when the diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 9d52d464d9..9062c6abf6 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -79,6 +79,7 @@ #define TM_INC 0x5 /* - + - + */ #define TM_AGE 0x6 /* - + - + */ #define TM_PIPR 0x7 /* - + - + */ +#define TM_OGEN 0xF /* - + - - */ /* P10 only */ #define TM_WORD0 0x0 #define TM_WORD1 0x4 From patchwork Mon Nov 4 00:18:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EA7BD11198 for ; Mon, 4 Nov 2024 00:26:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krn-0007gQ-Pf; Sun, 03 Nov 2024 19:22:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7krG-0005w3-0q; Sun, 03 Nov 2024 19:22:14 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7krD-0002lZ-TX; Sun, 03 Nov 2024 19:22:13 -0500 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-720be27db27so2796296b3a.2; Sun, 03 Nov 2024 16:22:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679730; x=1731284530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gueGYKVObJn2ZkN8cgWwc4frsrvVGquB46cJw5g0cbU=; b=An6PMH8g3eQDWRnQ5PQblYOoWEAc1vrkcSxdncbihUxwUaIPgIpde2axro24CRmRWV y2aWrc/HauNKOytgftwzu9UbVGuTzyIKWEF5U42xlHocIeICsl/EFBpXQ/Ruo5ROL6TS RV9NMvJxg1z7aBrdMGPMa6XQ2jEkfhkvn+oCYTEFFlCUbLUwG7Xa0wqCo42zgTDPbETl B6f5JmEGjpj4hUa89AJJrPbD2A0vDT4PkOiQNaRI+LlYfG7OAY0mpn2ERD9P52R+g8Ic H6zBCs3qN0TYIsQ+ls0yenk+bWkY3VM9hTs7mBHqot1shAs6HSAz/h36EKpTsU0Hd0eL Hkxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679730; x=1731284530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gueGYKVObJn2ZkN8cgWwc4frsrvVGquB46cJw5g0cbU=; b=MlBfcFvtBp8FmG+Qb0E8M7rgaKptp3ybm16N07FNBlzsmgu5YJGiKiZ25yfiu2Adw7 /A6pkOr2HZqIPjUQZdMj4RdtR2S0P4vFSL1g4mJHUxLJn8OTllzco1e0b7BzUv+0ynmf LL9yflP7TRmISPnDw0Q/rG92cfRlnGRrlWlfxJ96V6s8WKJDSxhak5TD0YpkdW4NmvWi cLCFKr6Kb0UDePY8nvl87T5iTXLODcrNgImRaRuZBMZUoS0eK2fDfwdEQ5q240uZOHU9 WC2IqEPeWjf3HZfF8R4pN+4mYvuUNMOTTHtd5VjyDrsjnEeX3+tpIcgJRTMweqNXyxDm uNJw== X-Forwarded-Encrypted: i=1; AJvYcCUQMcy/Rbi56+CozIdyMr+Ruk1ealFotE+OfVggC6q/zt0gZa7M0kWQKddONBMMc3GsRC60oRNSPg==@nongnu.org X-Gm-Message-State: AOJu0YyxF9R3hJyUzvjY1icv8sEXVSWquoMYuLLuD/nranZToba4RJOa TN4SZ+/e/X5+YBQjXPjjz1KBnnme/swrxF8+oBVraQmQpyRZAdNJVOctBA== X-Google-Smtp-Source: AGHT+IFEuf5KwqHu0T2L9+81MZ94NFzUiYpdaUu3+hh4bMfx8Ss9JbDIxAjsnxrOGU8T6IvwBU000g== X-Received: by 2002:a05:6a20:1589:b0:1db:d7d2:786d with SMTP id adf61e73a8af0-1dbd7d278d1mr3138346637.6.1730679729923; Sun, 03 Nov 2024 16:22:09 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:09 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Frederic Barrat , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" Date: Mon, 4 Nov 2024 10:18:39 +1000 Message-ID: <20241104001900.682660-51-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frederic Barrat Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CAM entry. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 2 + hw/intc/xive2.c | 160 ++++++++++++++++++++++++++++++------ include/hw/ppc/xive2.h | 2 + include/hw/ppc/xive2_regs.h | 2 + include/hw/ppc/xive_regs.h | 3 + 5 files changed, 142 insertions(+), 27 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 0e81678ab3..4532cfc467 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -547,6 +547,8 @@ static const XiveTmOp xive2_tm_operations[] = { xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol, + NULL }, }; static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 1f150685bf..fbd05aa9f5 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -26,6 +26,23 @@ uint32_t xive2_router_get_config(Xive2Router *xrtr) return xrc->get_config(xrtr); } +static int xive2_router_get_block_id(Xive2Router *xrtr) +{ + Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); + + return xrc->get_block_id(xrtr); +} + +static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) +{ + uint64_t cache_addr; + + cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | + xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); + cache_addr <<= 8; /* aligned on a cache line pair */ + return cache_addr; +} + void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) { if (!xive2_eas_is_valid(eas)) { @@ -270,6 +287,27 @@ static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk, *ho = !!(cam & TM2_QW1W2_HO); } + +/* + * Encode the HW CAM line with 7bit or 8bit thread id. The thread id + * width and block id width is configurable at the IC level. + * + * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) + * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) + */ +static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) +{ + Xive2Router *xrtr = XIVE2_ROUTER(xptr); + CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; + uint32_t pir = env->spr_cb[SPR_PIR].default_value; + uint8_t blk = xive2_router_get_block_id(xrtr); + uint8_t tid_shift = + xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; + uint8_t tid_mask = (1 << tid_shift) - 1; + + return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); +} + uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size) { @@ -301,6 +339,101 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, return qw1w2; } +#define REPORT_LINE_GEN1_SIZE 16 + +static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, + uint8_t size) +{ + uint8_t *regs = tctx->regs; + + g_assert(size == REPORT_LINE_GEN1_SIZE); + memset(data, 0, size); + /* + * See xive architecture for description of what is saved. It is + * hand-picked information to fit in 16 bytes. + */ + data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; + data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR]; + data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB]; + data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; + data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; + data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS]; + data[0x6] = 0xFF; + data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; + data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; + data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; + data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); + data[0x8] = regs[TM_QW1_OS + TM_NSR]; + data[0x9] = regs[TM_QW1_OS + TM_CPPR]; + data[0xA] = regs[TM_QW1_OS + TM_IPB]; + data[0xB] = regs[TM_QW1_OS + TM_LGS]; + if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { + /* + * Logical server extension, except VU bit replaced by EB bit + * from NSR + */ + data[0xC] = regs[TM_QW0_USER + TM_WORD2]; + data[0xC] &= ~0x80; + data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; + data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; + data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; + data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; + } +} + +void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + Xive2Router *xrtr = XIVE2_ROUTER(xptr); + uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; + uint8_t nvp_blk; + Xive2Nvp nvp; + uint64_t phys_addr; + MemTxResult result; + + hw_cam = xive2_tctx_hw_cam_line(xptr, tctx); + nvp_blk = xive2_nvp_blk(hw_cam); + nvp_idx = xive2_nvp_idx(hw_cam); + + if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", + nvp_blk, nvp_idx); + return; + } + + if (!xive2_nvp_is_valid(&nvp)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", + nvp_blk, nvp_idx); + return; + } + + xive2_cfg = xive2_router_get_config(xrtr); + + phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */ + if (xive2_cfg & XIVE2_GEN1_TIMA_OS) { + uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE]; + + xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE); + result = dma_memory_write(&address_space_memory, phys_addr, + pull_ctxt, REPORT_LINE_GEN1_SIZE, + MEMTXATTRS_UNSPECIFIED); + assert(result == MEMTX_OK); + } else { + result = dma_memory_write(&address_space_memory, phys_addr, + &tctx->regs, sizeof(tctx->regs), + MEMTXATTRS_UNSPECIFIED); + assert(result == MEMTX_OK); + reserved = 0xFFFFFFFF; + result = dma_memory_write(&address_space_memory, phys_addr + 12, + &reserved, sizeof(reserved), + MEMTXATTRS_UNSPECIFIED); + assert(result == MEMTX_OK); + } + + /* the rest is similar to pull OS context to registers */ + xive2_tm_pull_os_ctx(xptr, tctx, offset, size); +} + static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t nvp_blk, uint32_t nvp_idx, Xive2Nvp *nvp) @@ -471,33 +604,6 @@ int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); } -static int xive2_router_get_block_id(Xive2Router *xrtr) -{ - Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); - - return xrc->get_block_id(xrtr); -} - -/* - * Encode the HW CAM line with 7bit or 8bit thread id. The thread id - * width and block id width is configurable at the IC level. - * - * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) - * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) - */ -static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) -{ - Xive2Router *xrtr = XIVE2_ROUTER(xptr); - CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; - uint32_t pir = env->spr_cb[SPR_PIR].default_value; - uint8_t blk = xive2_router_get_block_id(xrtr); - uint8_t tid_shift = - xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; - uint8_t tid_mask = (1 << tid_shift) - 1; - - return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); -} - /* * The thread context register words are in big-endian format. */ diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index ab68f8d157..654f485e9b 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -107,5 +107,7 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); #endif /* PPC_XIVE2_H */ diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 4349d009d0..7acf7dccf3 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -171,7 +171,9 @@ typedef struct Xive2Nvp { #define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7) #define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31) uint32_t w6; +#define NVP2_W6_REPORTING_LINE PPC_BITMASK32(4, 31) uint32_t w7; +#define NVP2_W7_REPORTING_LINE PPC_BITMASK32(0, 23) } Xive2Nvp; #define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 9062c6abf6..27a744d50d 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -77,6 +77,7 @@ #define TM_LSMFB 0x3 /* - + + + */ #define TM_ACK_CNT 0x4 /* - + - - */ #define TM_INC 0x5 /* - + - + */ +#define TM_LGS 0x5 /* + + + + */ /* Rename P10 */ #define TM_AGE 0x6 /* - + - + */ #define TM_PIPR 0x7 /* - + - + */ #define TM_OGEN 0xF /* - + - - */ /* P10 only */ @@ -129,6 +130,8 @@ #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ /* line */ #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ +#define TM_SPC_PULL_OS_CTX_OL 0xc18 /* Pull/Invalidate OS context to */ + /* odd Thread reporting line */ #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */ /* line */ #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ From patchwork Mon Nov 4 00:18:40 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:13 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation Date: Mon, 4 Nov 2024 10:18:40 +1000 Message-ID: <20241104001900.682660-52-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles Adds support for single byte writes to offset 0x15 of the TIMA address space. This offset holds the Logical Server Group Size (LGS) field. The field is used to evenly distribute the interrupt load among the members of a group, but is unused in the current implementation so we just support the writing of the value for now. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 4532cfc467..caa8dc74b6 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -341,6 +341,19 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); } +static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs) +{ + uint8_t *regs = &tctx->regs[ring]; + + regs[TM_LGS] = lgs; +} + +static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); +} + /* * Adjust the IPB to allow a CPU to process event queues of other * priorities during one physical interrupt cycle. @@ -525,6 +538,8 @@ static const XiveTmOp xive2_tm_operations[] = { NULL }, { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, NULL }, + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs, + NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, From patchwork Mon Nov 4 00:18:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9821FD11198 for ; Mon, 4 Nov 2024 00:25:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krp-0007ry-HK; Sun, 03 Nov 2024 19:22:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7krN-0006jU-AV; Sun, 03 Nov 2024 19:22:21 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7krL-0002mJ-LL; Sun, 03 Nov 2024 19:22:21 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-71e61b47c6cso3273851b3a.2; Sun, 03 Nov 2024 16:22:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679738; x=1731284538; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gO8rc0AL2JsckP0Oo9U10hDIi/2TOJ1ZcNhDVDLVnL0=; b=KN2L9S4WAQ4EVzSVWwAhqO6wh/PC5ykxXltyQhDBMqZCe/e3gWfmQpB4fZ4M023Mz2 9PAsln3WVEFF+puSyWkI1ko1Qr3fRdBc/djCzxMvxMR5VsHY9UwZvbBFGr7VyZ2gW+aW ye61pnm1JNy1xL6MjuMFUry5f9z0s+gQsBn4MnVSZAy/TJIU1EeYCCKSqAfTaLZrsaGi FY9kiKM9PLSBMaToCUxET9t+m/nwKapPcOKr2+Lssgzoi32XhffVO/PKKP7zEGsOfVvs AJn+ipuDYFO99fh3xDiKBVerNUU49Q4NQWuKRVqrWAnVKmtQ9QIhX3kA4nhQwjDaA6fF kcEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679738; x=1731284538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gO8rc0AL2JsckP0Oo9U10hDIi/2TOJ1ZcNhDVDLVnL0=; b=pwlrjsjN8O2DZmRAV1JGchkDW1Jkf9R6C90Jx94fyfhGVWPzO++nunKO2tA71H5Egu 3A7o3nSAW85BBQo9QuX1VHBqHE276p8lLzgsh5AOxZE9OoU1Ah6mKKX1EQvdnrufgXSG CFikyC0RZ4JXsltZir8GubQWCJENPP5i4AZ1w0y1VwMI9YoBuS92QlJpW1KEyiFXFBCY prvNvSe7jyTnPR12qN7FeZRxNh2i+yktv9UzdjUVZqEKTzTUSAFev1zEk/X3h2caHraq a3CMZ9mfDO4mWpFfz6lczDen092u7hAKQokR2Sx3fwaLmRt403f8Cfz/7ww6UOhvfoSz 41Fg== X-Forwarded-Encrypted: i=1; AJvYcCXGsawjighk7I1YjRnB2mAfBBmpRu5fx/AogtuI4ReCdSQy5PmMpgn7vkQjkZRDJ6IyYih+C+q48Q==@nongnu.org X-Gm-Message-State: AOJu0YypDS9EJEMoOUjQZPzmfXaEPDqVokqoal50WuKDvfkeEm8JJlcG gscc8ELOGdu3hGsC0t2418Bk7mmKilIEGl+q2tu4wdxL1fPTKGeTT0zyEw== X-Google-Smtp-Source: AGHT+IEPJCzPyna2b8fd41adWUeFIeVvICtgUmwrW+oTBIJt1dBwajKV4PdC1+E0fpOd/6XbpVLzVw== X-Received: by 2002:a05:6a21:1690:b0:1d9:3456:b794 with SMTP id adf61e73a8af0-1d9a84bcdd6mr45311652637.38.1730679737737; Sun, 03 Nov 2024 16:22:17 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:17 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Frederic Barrat , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 52/67] ppc/xive2: Dump more NVP state with 'info pic' Date: Mon, 4 Nov 2024 10:18:41 +1000 Message-ID: <20241104001900.682660-53-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frederic Barrat The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP belongs to a VP group. Also, print the Reporting Cache Line address, if defined. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive2.c | 10 ++++++++-- include/hw/ppc/xive2_regs.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index fbd05aa9f5..ac581fa195 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -161,14 +161,20 @@ void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) { uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); + uint64_t cache_line = xive2_nvp_reporting_addr(nvp); if (!xive2_nvp_is_valid(nvp)) { return; } - g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x", + g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", nvp_idx, eq_blk, eq_idx, - xive_get_field32(NVP2_W2_IPB, nvp->w2)); + xive_get_field32(NVP2_W2_IPB, nvp->w2), + xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); + if (cache_line) { + g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line); + } + /* * When the NVP is HW controlled, more fields are updated */ diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 7acf7dccf3..d71a54f9ff 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -151,6 +151,7 @@ typedef struct Xive2Nvp { #define NVP2_W0_VALID PPC_BIT32(0) #define NVP2_W0_HW PPC_BIT32(7) #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */ +#define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31) uint32_t w1; #define NVP2_W1_CO PPC_BIT32(13) #define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15) From patchwork Mon Nov 4 00:18:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8989BD11198 for ; Mon, 4 Nov 2024 00:26:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krr-0008BT-Cu; Sun, 03 Nov 2024 19:22:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7krR-0006z8-Td; Sun, 03 Nov 2024 19:22:31 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7krP-0002me-EH; Sun, 03 Nov 2024 19:22:25 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-72097a5ca74so3421483b3a.3; Sun, 03 Nov 2024 16:22:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679741; x=1731284541; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bh6b9iqeWevef2cEJe76rh+lALiI/hMsSWHKlE5vZws=; b=RbSN8V9dU0Y7dXdspHTV7elI1MShJtKuopH9yJ5rVu3EBH/7wuxMIjNw0eu9pWF8w0 8LsQMDBriQ/MGpziIA7/XN8NF38eRQePgDASyJ0Zw3I3UDABVOy7gu3GwVyWvW2JdW4B VBVzRMM4sTYyPwqJGqgEhpA45OcF9glBunyyc7kMeqziqJikerleviRLtj8EdmE2OPVN IMFInbO/0BbWzu+irIvzc/XoxQoKzxEWsObd2AbWplO09S8tP+Ke0eGYLjED37UavxHC y6Phnkie5MJTj9PGUi/VXKz9QNlxT2apL6G3bhiRwvReSzpY1esfGas2iH1C6A9QX5eu e1QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679741; x=1731284541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bh6b9iqeWevef2cEJe76rh+lALiI/hMsSWHKlE5vZws=; b=nVpUEukq+Gkyvm2HRdfwNxNo8Z/e1NRTvBZKfenBKosssf2KtNfpofOs7TPHIbFKRn UPsBBdpXrZGSN0lTKKpx196DlDvi/CXMu2LG3JFfgZdxkRpee1d4tQmYHB5TDjcoaw7j zhmT442pUvCPZoD9yvmqXhWQ041n4Ym3/5oeXJvhNbzUxBgHP9rEVXswD5pqWAefdDnr b6T1CIDzTqzT8iMrTqXT7trhJUu1Hypg15s2ThxKmJXZ72aPDZRqUmtb/2TF1ysaNPlz smF9kip14xeNZxAtgac2rhVgZFk5fLUjbre4V9pua0Fh2QKpdteIdWXo3/TjFVm8bdNA 9+iw== X-Forwarded-Encrypted: i=1; AJvYcCUJJ4AKBT7t9hw2z4bjOMcQRtl31GLw7/XWQm4m1A5eYepbP3NFNBXCGJwZ/+1XmsKlmhvhTi8bVA==@nongnu.org X-Gm-Message-State: AOJu0YxlKqfASnMv9lpGoINJk9DCSDnAKDZOZ3Q/LL630zvsLLOVUvPg YH53Bg75LbA3hPfxFWxbsf5s9FMC3nmIzX1DaPIGhHblvl7e5huKoDHSug== X-Google-Smtp-Source: AGHT+IH32QBCj49gUkmRjAAfu91xQIKVQqngiDg94k5ihZnRK0gvKy7I1559BbYXvh06Uv9kI7MIbw== X-Received: by 2002:a05:6a21:1693:b0:1d9:1dcd:b22c with SMTP id adf61e73a8af0-1dba55734fdmr17159905637.47.1730679741329; Sun, 03 Nov 2024 16:22:21 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:20 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Frederic Barrat , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 53/67] ppc/xive2: Dump the VP-group and crowd tables with 'info pic' Date: Mon, 4 Nov 2024 10:18:42 +1000 Message-ID: <20241104001900.682660-54-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=npiggin@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frederic Barrat The 'info pic' HMP command dumps the state of the interrupt controller. Add the dump of the NVG and NVC tables to its output to ease debug. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/pnv_xive2.c | 44 +++++++++++++++++++++++++++-- hw/intc/xive2.c | 55 +++++++++++++++++++++++++++++++++++++ include/hw/ppc/xive2.h | 12 ++++++++ include/hw/ppc/xive2_regs.h | 6 ++++ 4 files changed, 114 insertions(+), 3 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 78609105a8..834d32287b 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -490,6 +490,23 @@ static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, word_number); } +static int pnv_xive2_get_nvgc(Xive2Router *xrtr, bool crowd, + uint8_t blk, uint32_t idx, + Xive2Nvgc *nvgc) +{ + return pnv_xive2_vst_read(PNV_XIVE2(xrtr), crowd ? VST_NVC : VST_NVG, + blk, idx, nvgc); +} + +static int pnv_xive2_write_nvgc(Xive2Router *xrtr, bool crowd, + uint8_t blk, uint32_t idx, + Xive2Nvgc *nvgc) +{ + return pnv_xive2_vst_write(PNV_XIVE2(xrtr), crowd ? VST_NVC : VST_NVG, + blk, idx, nvgc, + XIVE_VST_WORD_ALL); +} + static int pnv_xive2_nxc_to_table_type(uint8_t nxc_type, uint32_t *table_type) { switch (nxc_type) { @@ -2407,6 +2424,8 @@ static void pnv_xive2_class_init(ObjectClass *klass, void *data) xrc->write_end = pnv_xive2_write_end; xrc->get_nvp = pnv_xive2_get_nvp; xrc->write_nvp = pnv_xive2_write_nvp; + xrc->get_nvgc = pnv_xive2_get_nvgc; + xrc->write_nvgc = pnv_xive2_write_nvgc; xrc->get_config = pnv_xive2_get_config; xrc->get_block_id = pnv_xive2_get_block_id; @@ -2497,8 +2516,9 @@ void pnv_xive2_pic_print_info(PnvXive2 *xive, GString *buf) Xive2Eas eas; Xive2End end; Xive2Nvp nvp; + Xive2Nvgc nvgc; int i; - uint64_t xive_nvp_per_subpage; + uint64_t entries_per_subpage; g_string_append_printf(buf, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, srcno0 + nr_esbs - 1); @@ -2530,10 +2550,28 @@ void pnv_xive2_pic_print_info(PnvXive2 *xive, GString *buf) g_string_append_printf(buf, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 0, XIVE2_NVP_COUNT - 1); - xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); - for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { + entries_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); + for (i = 0; i < XIVE2_NVP_COUNT; i += entries_per_subpage) { while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { xive2_nvp_pic_print_info(&nvp, i++, buf); } } + + g_string_append_printf(buf, "XIVE[%x] #%d NVGT %08x .. %08x\n", + chip_id, blk, 0, XIVE2_NVP_COUNT - 1); + entries_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVG); + for (i = 0; i < XIVE2_NVP_COUNT; i += entries_per_subpage) { + while (!xive2_router_get_nvgc(xrtr, false, blk, i, &nvgc)) { + xive2_nvgc_pic_print_info(&nvgc, i++, buf); + } + } + + g_string_append_printf(buf, "XIVE[%x] #%d NVCT %08x .. %08x\n", + chip_id, blk, 0, XIVE2_NVP_COUNT - 1); + entries_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVC); + for (i = 0; i < XIVE2_NVP_COUNT; i += entries_per_subpage) { + while (!xive2_router_get_nvgc(xrtr, true, blk, i, &nvgc)) { + xive2_nvgc_pic_print_info(&nvgc, i++, buf); + } + } } diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index ac581fa195..26b6e72129 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -43,6 +43,26 @@ static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) return cache_addr; } +static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority) +{ + uint32_t val = 0; + uint8_t *ptr, i; + + if (priority > 7) { + return 0; + } + + /* + * The per-priority backlog counters are 24-bit and the structure + * is stored in big endian + */ + ptr = (uint8_t *)&nvgc->w2 + priority * 3; + for (i = 0; i < 3; i++, ptr++) { + val = (val << 8) + *ptr; + } + return val; +} + void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) { if (!xive2_eas_is_valid(eas)) { @@ -189,6 +209,23 @@ void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) g_string_append_c(buf, '\n'); } +void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) +{ + uint8_t i; + + if (!xive2_nvgc_is_valid(nvgc)) { + return; + } + + g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx, + xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); + for (i = 0; i <= XIVE_PRIORITY_MAX; i++) { + g_string_append_printf(buf, "[%d]=0x%x ", + i, xive2_nvgc_get_backlog(nvgc, i)); + } + g_string_append_printf(buf, "\n"); +} + static void xive2_end_enqueue(Xive2End *end, uint32_t data) { uint64_t qaddr_base = xive2_end_qaddr(end); @@ -610,6 +647,24 @@ int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); } +int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, + uint8_t nvgc_blk, uint32_t nvgc_idx, + Xive2Nvgc *nvgc) +{ + Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); + + return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); +} + +int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, + uint8_t nvgc_blk, uint32_t nvgc_idx, + Xive2Nvgc *nvgc) +{ + Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); + + return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); +} + /* * The thread context register words are in big-endian format. */ diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index 654f485e9b..b7a7c33ddd 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -53,6 +53,12 @@ typedef struct Xive2RouterClass { Xive2Nvp *nvp); int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, Xive2Nvp *nvp, uint8_t word_number); + int (*get_nvgc)(Xive2Router *xrtr, bool crowd, + uint8_t nvgc_blk, uint32_t nvgc_idx, + Xive2Nvgc *nvgc); + int (*write_nvgc)(Xive2Router *xrtr, bool crowd, + uint8_t nvgc_blk, uint32_t nvgc_idx, + Xive2Nvgc *nvgc); uint8_t (*get_block_id)(Xive2Router *xrtr); uint32_t (*get_config)(Xive2Router *xrtr); } Xive2RouterClass; @@ -67,6 +73,12 @@ int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, Xive2Nvp *nvp); int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, Xive2Nvp *nvp, uint8_t word_number); +int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, + uint8_t nvgc_blk, uint32_t nvgc_idx, + Xive2Nvgc *nvgc); +int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, + uint8_t nvgc_blk, uint32_t nvgc_idx, + Xive2Nvgc *nvgc); uint32_t xive2_router_get_config(Xive2Router *xrtr); void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index d71a54f9ff..99840e88a8 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -212,6 +212,7 @@ void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf); typedef struct Xive2Nvgc { uint32_t w0; #define NVGC2_W0_VALID PPC_BIT32(0) +#define NVGC2_W0_PGONEXT PPC_BITMASK32(26, 31) uint32_t w1; uint32_t w2; uint32_t w3; @@ -221,4 +222,9 @@ typedef struct Xive2Nvgc { uint32_t w7; } Xive2Nvgc; +#define xive2_nvgc_is_valid(nvgc) (be32_to_cpu((nvgc)->w0) & NVGC2_W0_VALID) + +void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, + GString *buf); + #endif /* PPC_XIVE2_REGS_H */ From patchwork Mon Nov 4 00:18:43 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:24 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA Date: Mon, 4 Nov 2024 10:18:43 +1000 Message-ID: <20241104001900.682660-55-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=npiggin@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for writes to the "TARGET" field which was added for XIVE GEN2. To fix this, we add special op support for 1-byte writes to this field. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 2 ++ hw/intc/xive2.c | 13 +++++++++++++ include/hw/ppc/xive2.h | 2 ++ include/hw/ppc/xive_regs.h | 1 + 4 files changed, 18 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index caa8dc74b6..574ac685c3 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -546,6 +546,8 @@ static const XiveTmOp xive2_tm_operations[] = { NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, xive2_tm_set_hv_target, + NULL }, /* MMIOs above 2K : special operations with side effects */ { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 26b6e72129..8d3d69a0db 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -585,6 +585,19 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, } } +static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) +{ + uint8_t *regs = &tctx->regs[ring]; + + regs[TM_T] = target; +} + +void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); +} + /* * XIVE Router (aka. Virtualization Controller or IVRE) */ diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index b7a7c33ddd..36bd0e747f 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -121,5 +121,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); +void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); #endif /* PPC_XIVE2_H */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 27a744d50d..f8f05deafd 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -79,6 +79,7 @@ #define TM_INC 0x5 /* - + - + */ #define TM_LGS 0x5 /* + + + + */ /* Rename P10 */ #define TM_AGE 0x6 /* - + - + */ +#define TM_T 0x6 /* - + - + */ /* Rename P10 */ #define TM_PIPR 0x7 /* - + - + */ #define TM_OGEN 0xF /* - + - - */ /* P10 only */ From patchwork Mon Nov 4 00:18:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5D48D11198 for ; Mon, 4 Nov 2024 00:24:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krx-0000M8-MQ; Sun, 03 Nov 2024 19:22:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7krZ-00070C-8w; Sun, 03 Nov 2024 19:22:35 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7krX-0002nH-2F; Sun, 03 Nov 2024 19:22:32 -0500 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-7ee020ec76dso3124786a12.3; Sun, 03 Nov 2024 16:22:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679749; x=1731284549; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wt9sdYER6slUStoqyOAXgzU/BryYr6CLR9YuB/Abd7M=; b=fOcIms3B6J85R3gfpWJMyLLitJ/55Te7f7wyytxtz2NrzstAkYx5g4M5vptMIQOIUx wya0hBCP/laoVAwD0D4Bbl1AGS3cqYoc6qaHs7GfB/XdAuaIQapkmTNtZvZQTpAW/Fel XEX+SbIXkFKLS2M6g7JKNx5LyyieXo+/ntdPvq+dEU1EJpCXQbxLEPXRtDeRz73BGLJ2 4K3RJQC711BvGyXrGufkuLfcLnKdZZ0AnWBO/uf15JYPLAiP28TqAx9qt+uziLtBC8Vu cvGcmNJrZhHoSs+HmbO4BgkZNVhdqI6KKeiE2BV+KWSq2k7LjUIfRjoFzSBRrJMkjNWI oX6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679749; x=1731284549; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wt9sdYER6slUStoqyOAXgzU/BryYr6CLR9YuB/Abd7M=; b=ONE2pg1ZxMQJ6Auzc9NCLqweu8rXIt5S8fBeSnYxABqGALANMJjH5QqJ5Y87bcLr43 NKzqHvq2MHwA1uMYdoml3hzZWlquoVXzAP8504u/XjMLdLliarPMibceMxrHUguLwGSx Bj5VhwMth3pKgRQxslK7cTS6UgEu0koj6uOXZYk7OjZAarejwMJZPQ3TDDY20R/vcbjH z+jcY05Gwdw+rNFgnD/cOmzwBoDr0VNM61WKKuw38HswGw7HOTUG0V/5sgkUiVvtxbd4 z/6L5YcBAmAbG7QtCHIbWSIjJloCPjZbNOy4nP0swBmsWEtYLLA60sVu3AcndvnZpNX2 R9Tg== X-Forwarded-Encrypted: i=1; AJvYcCXEFETx8eSQBfXIC9P6KymrjzyHRU3t/WUBnvHxGYw6vgAu54eQg2Ih+jBU7dk34Tod4cyP4gXSBg==@nongnu.org X-Gm-Message-State: AOJu0Yy0tgsXlgbQbPkE6R5GWGnFNbaww8Qlzas9rnccC/SU605nSbrB 3EZYmtGCMuK8Cz6jN2BPixcaZyMPYIuSOK7mJODkQVRnLO9ibWxqSYJhdA== X-Google-Smtp-Source: AGHT+IF6yFW9UGSiGayhSuk4WOEDSLWB8TnTnMA5XOqJhktXAMpbbi7cYHror7armlc6hzLOMnJv8w== X-Received: by 2002:a05:6a20:db0a:b0:1d2:e81c:adc0 with SMTP id adf61e73a8af0-1d9a8506e15mr43299036637.46.1730679748992; Sun, 03 Nov 2024 16:22:28 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:28 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 55/67] ppc/xive2: Support "Pull Thread Context to Register" operation Date: Mon, 4 Nov 2024 10:18:44 +1000 Message-ID: <20241104001900.682660-56-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=npiggin@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the hardware to atomically: 1. Read the number of bytes requested (lbz or lhz are supported). 2. Reset the valid bit of the thread context. 3. Return the number of bytes requested in step 1 to a register. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 15 +++++++++++++++ include/hw/ppc/xive_regs.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 574ac685c3..774e624160 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -179,6 +179,17 @@ static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, return qw2w2; } +static uint64_t xive_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) +{ + uint8_t qw3b8_prev = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; + uint8_t qw3b8; + + qw3b8 = qw3b8_prev & ~TM_QW3B8_VT; + tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = qw3b8; + return qw3b8; +} + static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size) { @@ -527,6 +538,8 @@ static const XiveTmOp xive_tm_operations[] = { xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, + xive_tm_pull_phys_ctx }, }; static const XiveTmOp xive2_tm_operations[] = { @@ -566,6 +579,8 @@ static const XiveTmOp xive2_tm_operations[] = { xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, + xive_tm_pull_phys_ctx }, }; static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index f8f05deafd..558a5ae742 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -101,6 +101,7 @@ #define TM_QW3W2_LP PPC_BIT32(6) #define TM_QW3W2_LE PPC_BIT32(7) #define TM_QW3W2_T PPC_BIT32(31) +#define TM_QW3B8_VT PPC_BIT8(0) /* * In addition to normal loads to "peek" and writes (only when invalid) @@ -128,6 +129,7 @@ #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */ /* context to reg */ #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ +#define TM_SPC_PULL_PHYS_CTX 0x838 /* Pull phys ctx to reg */ #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ /* line */ #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ From patchwork Mon Nov 4 00:18:45 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:31 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 56/67] ppc/xive2: Change context/ring specific functions to be generic Date: Mon, 4 Nov 2024 10:18:45 +1000 Message-ID: <20241104001900.682660-57-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=npiggin@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Michael Kowal Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate on any ring/context. This will simplify the next patch sets that are adding additional ring/context operations. Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 6 +++--- hw/intc/xive2.c | 20 ++++++++++---------- include/hw/ppc/xive.h | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 774e624160..84240d3c3e 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -114,7 +114,7 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) } } -void xive_tctx_reset_os_signal(XiveTCTX *tctx) +void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring) { /* * Lower the External interrupt. Used when pulling an OS @@ -122,7 +122,7 @@ void xive_tctx_reset_os_signal(XiveTCTX *tctx) * context. It should be raised again when re-pushing the OS * context. */ - qemu_irq_lower(xive_tctx_output(tctx, TM_QW1_OS)); + qemu_irq_lower(xive_tctx_output(tctx, ring)); } static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) @@ -424,7 +424,7 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); xive_tctx_set_os_cam(tctx, qw1w2_new); - xive_tctx_reset_os_signal(tctx); + xive_tctx_reset_signal(tctx, TM_QW1_OS); return qw1w2; } diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 8d3d69a0db..c5aa784fe8 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -270,13 +270,14 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data) * the NVP by changing the H bit while the context is enabled */ -static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, - uint8_t nvp_blk, uint32_t nvp_idx) +static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, + uint8_t nvp_blk, uint32_t nvp_idx, + uint8_t ring) { CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; uint32_t pir = env->spr_cb[SPR_PIR].default_value; Xive2Nvp nvp; - uint8_t *regs = &tctx->regs[TM_QW1_OS]; + uint8_t *regs = &tctx->regs[ring]; if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", @@ -321,8 +322,8 @@ static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); } -static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk, - uint32_t *nvp_idx, bool *vo, bool *ho) +static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, + uint32_t *nvp_idx, bool *vo, bool *ho) { *nvp_blk = xive2_nvp_blk(cam); *nvp_idx = xive2_nvp_idx(cam); @@ -330,7 +331,6 @@ static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk, *ho = !!(cam & TM2_QW1W2_HO); } - /* * Encode the HW CAM line with 7bit or 8bit thread id. The thread id * width and block id width is configurable at the IC level. @@ -363,7 +363,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, bool vo; bool do_save; - xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save); + xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save); if (!vo) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", @@ -375,10 +375,10 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { - xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx); + xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, TM_QW1_OS); } - xive_tctx_reset_os_signal(tctx); + xive_tctx_reset_signal(tctx, TM_QW1_OS); return qw1w2; } @@ -573,7 +573,7 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, bool vo; bool do_restore; - xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); + xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); /* First update the thead context */ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 3a65c2f29a..ebee982528 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -533,7 +533,7 @@ Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); -void xive_tctx_reset_os_signal(XiveTCTX *tctx); +void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring); /* * KVM XIVE device helpers From patchwork Mon Nov 4 00:18:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD6DBD1119A for ; Mon, 4 Nov 2024 00:26:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krz-0000aH-SY; Sun, 03 Nov 2024 19:22:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7krf-000719-Iv; Sun, 03 Nov 2024 19:22:40 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7krd-0002nw-Pv; Sun, 03 Nov 2024 19:22:39 -0500 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-71e79f73aaeso3003741b3a.3; Sun, 03 Nov 2024 16:22:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679756; x=1731284556; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eNQIlh9E03AkTT+nJ3mokqkoQL2ZdRCi7nnwW1kK7io=; b=EzsbuCdvlQ/u7zRMbggIN2MEkkw364DrMKBYmx9zYlB8eAcJIOiJMuvKT3SA323Tgt XgYZetcYJ44fUZDNiFl/j4QBP43OGgMbsw7GCYWBBC4GB5vDVb6UoDF+4Or0/139ODxP INezAJjuHoCGgMSmt266tVW7aRkJhn9ro3DOon4F8Le7rjRMlEXluXbVDeucOr2Z84EK WKDkG6tCbK4iWUEtrhct9Cx+0ixjEiMwvVsnH9s9ys/MZD9D0JwneDucUHNVhuoWqbnR gd+1l1zsb7U3R87dOKW0BdMoanpLUhY9CkLzl8SPTS0Bh3AOKy8SdOJtpz8pHlYcZg20 WzQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679756; x=1731284556; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eNQIlh9E03AkTT+nJ3mokqkoQL2ZdRCi7nnwW1kK7io=; b=a03/cO5aMYg5g2xiLSMphpub1Fie71R/vY6ByqrC9BE707lo/iIPS3hh06PHs1/W9l 0G39pARe1spG58TPuXjqQVQ7f06YW2j0a7OgtUSlgtKx9KVjKTDLMhw7jW/h3b6aiZeU hPwVmbzqT2MITaTkWwLOHHnvD3wAR0CjAPvM5XtHJi00X6eNmQzOW2Giv8h317Wn8sEV 2i9+KdoHUwH+qqZw9uF5CoM5rqtJ4ek6UMZF4K3hITTdeS97C/9BzrLNGIukLSrUBQq+ o6qi1VvdlbgxRwo/siT8+ihff93BFlVHjBa2npXsR4AVYLGnS3xR73uOrCRQpzjpNaTo HAzw== X-Forwarded-Encrypted: i=1; AJvYcCVyDqUPskiMnA8jELRhWMxvV61GqwWeiyNhbabpbEb9T6Aw+ULyH4d6RP/yGAb2LKNp5TJDBy5odw==@nongnu.org X-Gm-Message-State: AOJu0YyFwVIk/iN2NNALoSOOFQVfn+qeduaNDJfwm407EbaJ9ujUZD98 vg+L+DWQLNwgGTrk+JSLpcQHNd/asa/1RF99gmDIccsbnZOxerFhoFajAw== X-Google-Smtp-Source: AGHT+IF3gcE8g3Pn3kKH+81cdgAgWvYY0FErEHqE9nmqL3LyTpiyWSKAQTfrLLoCs53WYutLY++BHQ== X-Received: by 2002:a05:6a21:e88:b0:1d8:f171:dccd with SMTP id adf61e73a8af0-1d9a851e08dmr37851670637.37.1730679755792; Sun, 03 Nov 2024 16:22:35 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:35 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" Date: Mon, 4 Nov 2024 10:18:46 +1000 Message-ID: <20241104001900.682660-58-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles Adds support for single byte writes to offset 0xC38 of the TIMA address space. When this offset is written to, the hardware disables the thread context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the THREAD CAM entry. Note that this operation is almost identical to what we are already doing for the "Pull OS Context to Odd Thread Reporting Line" operation except that it also invalidates the Pool and Thread Contexts. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 9 +++-- hw/intc/xive2.c | 73 ++++++++++++++++++++++++++----------- include/hw/ppc/xive2.h | 2 + include/hw/ppc/xive2_regs.h | 16 ++++---- include/hw/ppc/xive_regs.h | 1 + 5 files changed, 69 insertions(+), 32 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 84240d3c3e..951aaf5279 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -117,10 +117,9 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring) { /* - * Lower the External interrupt. Used when pulling an OS - * context. It is necessary to avoid catching it in the hypervisor - * context. It should be raised again when re-pushing the OS - * context. + * Lower the External interrupt. Used when pulling a context. It is + * necessary to avoid catching it in the higher privilege context. It + * should be raised again when re-pushing the lower privilege context. */ qemu_irq_lower(xive_tctx_output(tctx, ring)); } @@ -581,6 +580,8 @@ static const XiveTmOp xive2_tm_operations[] = { NULL }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, xive_tm_pull_phys_ctx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol, + NULL }, }; static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index c5aa784fe8..2e41bd9edb 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -323,12 +323,12 @@ static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, } static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, - uint32_t *nvp_idx, bool *vo, bool *ho) + uint32_t *nvp_idx, bool *valid, bool *hw) { *nvp_blk = xive2_nvp_blk(cam); *nvp_idx = xive2_nvp_idx(cam); - *vo = !!(cam & TM2_QW1W2_VO); - *ho = !!(cam & TM2_QW1W2_HO); + *valid = !!(cam & TM2_W2_VALID); + *hw = !!(cam & TM2_W2_HW); } /* @@ -351,35 +351,52 @@ static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); } -uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, - hwaddr offset, unsigned size) +static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size, uint8_t ring) { Xive2Router *xrtr = XIVE2_ROUTER(xptr); - uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); - uint32_t qw1w2_new; - uint32_t cam = be32_to_cpu(qw1w2); + uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); + uint32_t cam = be32_to_cpu(target_ringw2); uint8_t nvp_blk; uint32_t nvp_idx; - bool vo; + uint8_t cur_ring; + bool valid; bool do_save; - xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save); + xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); - if (!vo) { + if (!valid) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", nvp_blk, nvp_idx); } - /* Invalidate CAM line */ - qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0); - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); + /* Invalidate CAM line of requested ring and all lower rings */ + for (cur_ring = TM_QW0_USER; cur_ring <= ring; + cur_ring += XIVE_TM_RING_SIZE) { + uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); + uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0); + memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); + } if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { - xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, TM_QW1_OS); + xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring); + } + + /* + * Lower external interrupt line of requested ring and below except for + * USER, which doesn't exist. + */ + for (cur_ring = TM_QW1_OS; cur_ring <= ring; + cur_ring += XIVE_TM_RING_SIZE) { + xive_tctx_reset_signal(tctx, cur_ring); } + return target_ringw2; +} - xive_tctx_reset_signal(tctx, TM_QW1_OS); - return qw1w2; +uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) +{ + return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); } #define REPORT_LINE_GEN1_SIZE 16 @@ -424,8 +441,9 @@ static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, } } -void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, - hwaddr offset, uint64_t value, unsigned size) +static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, + unsigned size, uint8_t ring) { Xive2Router *xrtr = XIVE2_ROUTER(xptr); uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; @@ -473,8 +491,21 @@ void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, assert(result == MEMTX_OK); } - /* the rest is similar to pull OS context to registers */ - xive2_tm_pull_os_ctx(xptr, tctx, offset, size); + /* the rest is similar to pull context to registers */ + xive2_tm_pull_ctx(xptr, tctx, offset, size, ring); +} + +void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); +} + + +void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); } static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index 36bd0e747f..5bccf41159 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -123,5 +123,7 @@ void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); +void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size); #endif /* PPC_XIVE2_H */ diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 99840e88a8..1d00c8df64 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -19,16 +19,18 @@ * mode (P10), the CAM line is slightly different as the VP space was * increased. */ -#define TM2_QW0W2_VU PPC_BIT32(0) +#define TM2_W2_VALID PPC_BIT32(0) +#define TM2_W2_HW PPC_BIT32(1) +#define TM2_QW0W2_VU TM2_W2_VALID #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31) -#define TM2_QW1W2_VO PPC_BIT32(0) -#define TM2_QW1W2_HO PPC_BIT32(1) +#define TM2_QW1W2_VO TM2_W2_VALID +#define TM2_QW1W2_HO TM2_W2_HW #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31) -#define TM2_QW2W2_VP PPC_BIT32(0) -#define TM2_QW2W2_HP PPC_BIT32(1) +#define TM2_QW2W2_VP TM2_W2_VALID +#define TM2_QW2W2_HP TM2_W2_HW #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31) -#define TM2_QW3W2_VT PPC_BIT32(0) -#define TM2_QW3W2_HT PPC_BIT32(1) +#define TM2_QW3W2_VT TM2_W2_VALID +#define TM2_QW3W2_HT TM2_W2_HW #define TM2_QW3W2_LP PPC_BIT32(6) #define TM2_QW3W2_LE PPC_BIT32(7) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 558a5ae742..5b11463777 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -138,6 +138,7 @@ #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */ /* line */ #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ +#define TM_SPC_PULL_PHYS_CTX_OL 0xc38 /* Pull phys ctx to odd cache line */ /* XXX more... */ /* NSR fields for the various QW ack types */ From patchwork Mon Nov 4 00:18:47 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:39 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 58/67] pnv/xive: Add special handling for pool targets Date: Mon, 4 Nov 2024 10:18:47 +1000 Message-ID: <20241104001900.682660-59-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles Hypervisor "pool" targets do not get their own interrupt line and instead must share an interrupt line with the hypervisor "physical" targets. This also means that the pool ring must use some of the registers from the physical ring in the TIMA. Specifically, the NSR, PIPR and CPPR registers: NSR = Notification Source Register PIPR = Post Interrupt Priority Register CPPR = Current Processor Priority Register The NSR specifies that there is an active interrupt. The CPPR specifies the priority of the context and the PIPR specifies the priority of the interrupt. For an interrupt to be presented to a context, the priority of the interrupt must be higher than the priority of the context it is interrupting (value must be lower). The existing code was not aware of the sharing of these registers. This commit adds that support. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 951aaf5279..baad7129ca 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -74,33 +74,49 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) if (regs[TM_NSR] & mask) { uint8_t cppr = regs[TM_PIPR]; + uint8_t alt_ring; + uint8_t *alt_regs; + + /* POOL interrupt uses IPB in QW2, POOL ring */ + if ((ring == TM_QW3_HV_PHYS) && (nsr & (TM_QW3_NSR_HE_POOL << 6))) { + alt_ring = TM_QW2_HV_POOL; + } else { + alt_ring = ring; + } + alt_regs = &tctx->regs[alt_ring]; regs[TM_CPPR] = cppr; /* Reset the pending buffer bit */ - regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); - regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); + alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); + regs[TM_PIPR] = ipb_to_pipr(alt_regs[TM_IPB]); /* Drop Exception bit */ regs[TM_NSR] &= ~mask; - trace_xive_tctx_accept(tctx->cs->cpu_index, ring, - regs[TM_IPB], regs[TM_PIPR], + trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, + alt_regs[TM_IPB], regs[TM_PIPR], regs[TM_CPPR], regs[TM_NSR]); } - return (nsr << 8) | regs[TM_CPPR]; + return ((uint64_t)nsr << 8) | regs[TM_CPPR]; } static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) { + /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ + uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; + uint8_t *alt_regs = &tctx->regs[alt_ring]; uint8_t *regs = &tctx->regs[ring]; - if (regs[TM_PIPR] < regs[TM_CPPR]) { + if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) { switch (ring) { case TM_QW1_OS: regs[TM_NSR] |= TM_QW1_NSR_EO; break; + case TM_QW2_HV_POOL: + alt_regs[TM_NSR] = (TM_QW3_NSR_HE_POOL << 6); + break; case TM_QW3_HV_PHYS: regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); break; @@ -108,8 +124,8 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring) g_assert_not_reached(); } trace_xive_tctx_notify(tctx->cs->cpu_index, ring, - regs[TM_IPB], regs[TM_PIPR], - regs[TM_CPPR], regs[TM_NSR]); + regs[TM_IPB], alt_regs[TM_PIPR], + alt_regs[TM_CPPR], alt_regs[TM_NSR]); qemu_irq_raise(xive_tctx_output(tctx, ring)); } } @@ -217,14 +233,14 @@ static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, static const uint8_t xive_tm_hw_view[] = { 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ - 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ + 0, 0, 3, 3, 0, 3, 3, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */ }; static const uint8_t xive_tm_hv_view[] = { 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */ 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */ - 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ + 0, 0, 3, 3, 0, 3, 3, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */ 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */ }; From patchwork Mon Nov 4 00:18:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49BA3D11198 for ; Mon, 4 Nov 2024 00:25:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7krr-000879-5N; Sun, 03 Nov 2024 19:22:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7krm-0007cu-VC; Sun, 03 Nov 2024 19:22:47 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7krl-0002oi-8l; Sun, 03 Nov 2024 19:22:46 -0500 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-720d14c8dbfso2326207b3a.0; Sun, 03 Nov 2024 16:22:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679763; x=1731284563; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bKJeZuECGCGYQRCE/Wz2aptnEpkzwWv0a7kXALVVYP8=; b=H4O4WLtx+QnA4byWd8SIocZZ8LpBKxCcy2eSIzD0UWtBsuBmsHniETIlR8sAj98TI3 HRneZsHHw//e7ntb39nkcaRinrmSqnYw1cbCNUKIsm3HAdcUdeQMnvpQ/Ry3c3pSCKoi F8egmM2+t684qS+Tk393KmLjkoybdEQf7+JIe6YEYntvtt+GLT2o+1ZyLjNBycZZI+IN YpnHuPpJxLCVzkeJCHHaDsTxu24K6fr9fw1xrLX6pbfrIURrLoiSiv/rk4lxsXRABiA9 Cby/Sq6ROOyfl2O5MDoRDT1hgTa0KK6PltL7Jtm/L6IUkNXf0LgwpWwBzB9OftArIhA9 66fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679763; x=1731284563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bKJeZuECGCGYQRCE/Wz2aptnEpkzwWv0a7kXALVVYP8=; b=nPpMs6tovlu65fuNCxPwBSNKJndGLIH/jBySdONRMHvU6x69Zm1it+URYo80HpAHrf P8T2uCAYRh9MIk4TrNRWWnTsdgkbzSm6kV+AgGtqoSf9ezOY8nn/zvNB4k/4SvhqcN67 N6KQm8iknGEoOrl1boHz2jUIOh2wAEBj7NU0jLnCtp5FG9EQLFLx09ZfGXBqqxC+lmjT zO9AU++Q8F4u1k3EIEneuBkDhoF7LS40wB9Cx488oTAZRfS4EcUFTHcE68iW5eh7+9hw WoT6HPDGiK9OAV10tC2LaY8Zwh7BnQR7XYYmY8BIewc3H9X9U7MVQkZsWk3tMVIJ6pQz 75Qw== X-Forwarded-Encrypted: i=1; AJvYcCW81B0ptl+FDz9oA+bcwOIUbMEiiR9vm16JWPzfhf9Fjm9okszhRQGa1YMVbkLL+EDtg5H7OaOj3Q==@nongnu.org X-Gm-Message-State: AOJu0YzbNNVGwklpEBEyKu8y6jEONqlop3xcVYn9JKpWxyFydvHB7YtB nQYAFtkYcmjuUQsP0b+CSjw4HPTtt8SxaIdu0oSUyC7K2VNUaUb0uw/e9Q== X-Google-Smtp-Source: AGHT+IH8WTOaxPIx8AOQS8yZLRGGkYNd23+mHjiZsjacKdsC5+S/GCkrHz8LysRomM4VnF1nCp0L+Q== X-Received: by 2002:a05:6a20:d498:b0:1d9:1823:83bf with SMTP id adf61e73a8af0-1db91d516d0mr19815344637.8.1730679763291; Sun, 03 Nov 2024 16:22:43 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:42 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 59/67] pnv/xive: Update PIPR when updating CPPR Date: Mon, 4 Nov 2024 10:18:48 +1000 Message-ID: <20241104001900.682660-60-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Moved the update to the xive_tctx_set_cppr function which required additional support for pool interrupts. Fixes: cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority is more privileged") Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index baad7129ca..8460bd622a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -89,7 +89,6 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) /* Reset the pending buffer bit */ alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); - regs[TM_PIPR] = ipb_to_pipr(alt_regs[TM_IPB]); /* Drop Exception bit */ regs[TM_NSR] &= ~mask; @@ -143,6 +142,8 @@ void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring) static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { uint8_t *regs = &tctx->regs[ring]; + uint8_t pipr_min; + uint8_t ring_min; trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, regs[TM_IPB], regs[TM_PIPR], @@ -154,8 +155,37 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) tctx->regs[ring + TM_CPPR] = cppr; + /* + * Recompute the PIPR based on local pending interrupts. The PHYS + * ring must take the minimum of both the PHYS and POOL PIPR values. + */ + pipr_min = ipb_to_pipr(regs[TM_IPB]); + ring_min = ring; + + /* PHYS updates also depend on POOL values */ + if (ring == TM_QW3_HV_PHYS) { + uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; + + /* POOL values only matter if POOL ctx is valid */ + if (pool_regs[TM_WORD2] & 0x80) { + + uint8_t pool_pipr = ipb_to_pipr(pool_regs[TM_IPB]); + + /* + * Determine highest priority interrupt and + * remember which ring has it. + */ + if (pool_pipr < pipr_min) { + pipr_min = pool_pipr; + ring_min = TM_QW2_HV_POOL; + } + } + } + + regs[TM_PIPR] = pipr_min; + /* CPPR has changed, check if we need to raise a pending exception */ - xive_tctx_notify(tctx, ring); + xive_tctx_notify(tctx, ring_min); } void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) From patchwork Mon Nov 4 00:18:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 066CCD11199 for ; Mon, 4 Nov 2024 00:30:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7ks3-0000ry-Co; Sun, 03 Nov 2024 19:23:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7krq-00083o-FC; Sun, 03 Nov 2024 19:22:50 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7kro-0002p9-RF; Sun, 03 Nov 2024 19:22:50 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-71e7086c231so3039973b3a.0; Sun, 03 Nov 2024 16:22:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679767; x=1731284567; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+WwBo0jIjtqBSBwsn7hROT+x0KuPSJ7wyOc1nHG67tI=; b=K/qEH2EkVTwd4iSzjeD+4P6PurJua+57V7v/S6iFe3zQGfMnnPhLkPcFkeQRdiNooB kqPI9JgOxgg87ZLJLP6ERbJBGgxwfmioe4tvlrNNrq5tr5EHGZVKeoTopISedzFZOgsI rbF2jkO3mBbZkqFhgcOy0scoPnS62NJBmCpbz17NFhvrEjuNWGBNQ2H0XEOyjrBQx32p HBgvP3G9edWDn7qE2feM5CcLfGWDQPhKI9WGdhG8G8Ph4HY7CIfKiYEfGPO9kTSbJYif A47bvmgQj8ewuPBezZhnMcEpvQnWKDwnjHanrjmbpvhCVPI4hhNLW3EyKi2uJGcMNHRE 819Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679767; x=1731284567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+WwBo0jIjtqBSBwsn7hROT+x0KuPSJ7wyOc1nHG67tI=; b=gwh+rWOnm+f8VJisaPQ0Kg/AGHN+Vj+2tWDaVDN/2xNsdrngq5RWEUlP10w6P8ZXQk 15ZyyoYk4l/hrmgls2nATCAoJwwC4jla6aINMD34W6c+7RX23/B5yY8oHYcA6cGLsRXl W043GKqT4yFcN/GNGDH8A2AP81CPTUw19bbi9y6JfWC0QmtMpWwhxgIWvW0Xn5q9Gzeb kB71o9LC531NVkHZnJTNGuqvuYF4WKoZV3W8E9YIhMazFFcfgdc69LB50YQM1jNWp3yE 5zOg82EP15hqb26K/SKN3vaNxuxZCQm12+9Lfs3jQKwKdrlz9B6dLXg3fnPuwmJxJKjw zTmw== X-Forwarded-Encrypted: i=1; AJvYcCW3JNOZVi0Q76tecIj8AD7f/WXYbd8Fc/xqq7ixBqOmAAhwcrCdrIbpPGmANLQf7oEISk1nBwQ25A==@nongnu.org X-Gm-Message-State: AOJu0YxeNu8cazXDqNPQT960rckCM9dYGI3tb4QUw1Xu5aowKr4Mu10J G3lL2hONXZ5/51+81vKb9pVErMykvvjLrzoC/ukMYbwp1mcHRTMCHiNiNA== X-Google-Smtp-Source: AGHT+IHEDju3nuEQnuwITS6/E5Mw7V/IQFA8dxgXkF16pNTgVlpSl4G1dlWKrnHyFqhbpIqdj+2qLw== X-Received: by 2002:a05:6a20:43ac:b0:1d8:a759:525c with SMTP id adf61e73a8af0-1d9a851df61mr42449271637.39.1730679766896; Sun, 03 Nov 2024 16:22:46 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:46 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP Date: Mon, 4 Nov 2024 10:18:49 +1000 Message-ID: <20241104001900.682660-61-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles PHYP uses 8-byte writes to the 2nd doubleword of the OS context line when dispatching an OS level virtual processor. This support was not used by OPAL/Linux and so was never added. Without this support, the XIVE code doesn't notice that a new context is being pushed and fails to check for unpresented pending interrupts for that context. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 2 ++ hw/intc/xive2.c | 24 +++++++++++++++++++----- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8460bd622a..82c676b151 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -596,6 +596,8 @@ static const XiveTmOp xive2_tm_operations[] = { NULL }, { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, NULL }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, xive2_tm_push_os_ctx, + NULL }, { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 2e41bd9edb..d1df35e9b3 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -597,17 +597,31 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size) { - uint32_t cam = value; - uint32_t qw1w2 = cpu_to_be32(cam); + uint32_t cam; + uint32_t qw1w2; + uint64_t qw1dw1; uint8_t nvp_blk; uint32_t nvp_idx; bool vo; bool do_restore; - xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); - /* First update the thead context */ - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + switch (size) { + case 4: + cam = value; + qw1w2 = cpu_to_be32(cam); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + break; + case 8: + cam = value >> 32; + qw1dw1 = cpu_to_be64(value); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); + break; + default: + g_assert_not_reached(); + } + + xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); /* Check the interrupt pending bits */ if (vo) { From patchwork Mon Nov 4 00:18:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E6D3D11194 for ; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:49 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 61/67] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths Date: Mon, 4 Nov 2024 10:18:50 +1000 Message-ID: <20241104001900.682660-62-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=npiggin@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Michael Kowal Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_opertions[] table entries are missing when they exist for other offsets/sizes and have been added: - lwz@0x810 Pull/Invalidate O/S Context to register added lwz@0x818 exists ld @0x818 exists - lwz@0x820 Pull Pool Context to register added lwz@0x828 exists ld @0x828 exists - lwz@0x830 Pull Thread Context to register added lbz@0x838 exists Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 6 ++++++ include/hw/ppc/xive_regs.h | 7 ++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 82c676b151..245e4d181a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -614,18 +614,24 @@ static const XiveTmOp xive2_tm_operations[] = { xive_tm_ack_os_reg }, { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL, + xive2_tm_pull_os_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive2_tm_pull_os_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive2_tm_pull_os_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL, + xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL, + xive_tm_pull_phys_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, xive_tm_pull_phys_ctx }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol, diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 5b11463777..326327fc79 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -124,12 +124,17 @@ #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */ /* context */ #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ +#define TM_SPC_PULL_OS_CTX_G2 0x810 /* Load32/Load64 Pull/Invalidate OS */ + /* context to reg */ #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */ /* context to reg */ +#define TM_SPC_PULL_POOL_CTX_G2 0x820 /* Load32/Load64 Pull/Invalidate Pool */ + /* context to reg */ #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */ /* context to reg */ #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ -#define TM_SPC_PULL_PHYS_CTX 0x838 /* Pull phys ctx to reg */ +#define TM_SPC_PULL_PHYS_CTX_G2 0x830 /* Load32 Pull phys ctx to reg */ +#define TM_SPC_PULL_PHYS_CTX 0x838 /* Load8 Pull phys ctx to reg */ #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */ /* line */ #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ From patchwork Mon Nov 4 00:18:51 2024 Content-Type: text/plain; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:54 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Frederic Barrat , Glenn Miles , Michael Kowal , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 62/67] tests/qtest: Add XIVE tests for the powernv10 machine Date: Mon, 4 Nov 2024 10:18:51 +1000 Message-ID: <20241104001900.682660-63-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frederic Barrat These XIVE tests include: - General interrupt IRQ tests that: - enable and trigger an interrupt - acknowledge the interrupt - end of interrupt processing - Test the Pull Thread Context to Odd Thread Reporting Line - Test the different cache flush inject and queue sync inject operations Co-authored-by: Frederic Barrat Co-authored-by: Glenn Miles Co-authored-by: Michael Kowal Signed-off-by: Frederic Barrat Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- MAINTAINERS | 1 + tests/qtest/meson.build | 2 + tests/qtest/pnv-xive2-common.c | 190 ++++++++++++++++ tests/qtest/pnv-xive2-common.h | 111 ++++++++++ tests/qtest/pnv-xive2-flush-sync.c | 205 +++++++++++++++++ tests/qtest/pnv-xive2-test.c | 344 +++++++++++++++++++++++++++++ 6 files changed, 853 insertions(+) create mode 100644 tests/qtest/pnv-xive2-common.c create mode 100644 tests/qtest/pnv-xive2-common.h create mode 100644 tests/qtest/pnv-xive2-flush-sync.c create mode 100644 tests/qtest/pnv-xive2-test.c diff --git a/MAINTAINERS b/MAINTAINERS index cf39ad4b7c..64b4ffa91c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2625,6 +2625,7 @@ L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/*/*xive* F: include/hw/*/*xive* +F: tests/qtest/*xive* F: docs/*/*xive* Renesas peripherals diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 9d51114539..db101cbbee 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -176,6 +176,7 @@ qtests_ppc64 = \ qtests_ppc + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) + \ + (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xive2-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-spi-seeprom-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : []) + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['numa-test'] : []) + \ @@ -344,6 +345,7 @@ qtests = { 'ivshmem-test': [rt, '../../contrib/ivshmem-server/ivshmem-server.c'], 'migration-test': migration_files, 'pxe-test': files('boot-sector.c'), + 'pnv-xive2-test': files('pnv-xive2-common.c', 'pnv-xive2-flush-sync.c'), 'qos-test': [chardev, io, qos_test_ss.apply({}).sources()], 'tpm-crb-swtpm-test': [io, tpmemu_files], 'tpm-crb-test': [io, tpmemu_files], diff --git a/tests/qtest/pnv-xive2-common.c b/tests/qtest/pnv-xive2-common.c new file mode 100644 index 0000000000..bf2bce0056 --- /dev/null +++ b/tests/qtest/pnv-xive2-common.c @@ -0,0 +1,190 @@ +/* + * QTest testcase for PowerNV 10 interrupt controller (xive2) + * - Common functions for XIVE2 tests + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "libqtest.h" + +#include "pnv-xive2-common.h" + + +static uint64_t pnv_xscom_addr(uint32_t pcba) +{ + return P10_XSCOM_BASE | ((uint64_t) pcba << 3); +} + +static uint64_t pnv_xive_xscom_addr(uint32_t reg) +{ + return pnv_xscom_addr(XIVE_XSCOM + reg); +} + +uint64_t pnv_xive_xscom_read(QTestState *qts, uint32_t reg) +{ + return qtest_readq(qts, pnv_xive_xscom_addr(reg)); +} + +void pnv_xive_xscom_write(QTestState *qts, uint32_t reg, uint64_t val) +{ + qtest_writeq(qts, pnv_xive_xscom_addr(reg), val); +} + +static void xive_get_struct(QTestState *qts, uint64_t src, void *dest, + size_t size) +{ + uint8_t *destination = (uint8_t *)dest; + size_t i; + + for (i = 0; i < size; i++) { + *(destination + i) = qtest_readb(qts, src + i); + } +} + +static void xive_copy_struct(QTestState *qts, void *src, uint64_t dest, + size_t size) +{ + uint8_t *source = (uint8_t *)src; + size_t i; + + for (i = 0; i < size; i++) { + qtest_writeb(qts, dest + i, *(source + i)); + } +} + +uint64_t xive_get_queue_addr(uint32_t end_index) +{ + return XIVE_QUEUE_MEM + (uint64_t)end_index * XIVE_QUEUE_SIZE; +} + +uint8_t get_esb(QTestState *qts, uint32_t index, uint8_t page, + uint32_t offset) +{ + uint64_t addr; + + addr = XIVE_ESB_ADDR + ((uint64_t)index << (XIVE_PAGE_SHIFT + 1)); + if (page == 1) { + addr += 1 << XIVE_PAGE_SHIFT; + } + return qtest_readb(qts, addr + offset); +} + +void set_esb(QTestState *qts, uint32_t index, uint8_t page, + uint32_t offset, uint32_t val) +{ + uint64_t addr; + + addr = XIVE_ESB_ADDR + ((uint64_t)index << (XIVE_PAGE_SHIFT + 1)); + if (page == 1) { + addr += 1 << XIVE_PAGE_SHIFT; + } + return qtest_writel(qts, addr + offset, cpu_to_be32(val)); +} + +void get_nvp(QTestState *qts, uint32_t index, Xive2Nvp* nvp) +{ + uint64_t addr = XIVE_NVP_MEM + (uint64_t)index * sizeof(Xive2Nvp); + xive_get_struct(qts, addr, nvp, sizeof(Xive2Nvp)); +} + +void set_nvp(QTestState *qts, uint32_t index, uint8_t first) +{ + uint64_t nvp_addr; + Xive2Nvp nvp; + uint64_t report_addr; + + nvp_addr = XIVE_NVP_MEM + (uint64_t)index * sizeof(Xive2Nvp); + report_addr = (XIVE_REPORT_MEM + (uint64_t)index * XIVE_REPORT_SIZE) >> 8; + + memset(&nvp, 0, sizeof(nvp)); + nvp.w0 = xive_set_field32(NVP2_W0_VALID, 0, 1); + nvp.w0 = xive_set_field32(NVP2_W0_PGOFIRST, nvp.w0, first); + nvp.w6 = xive_set_field32(NVP2_W6_REPORTING_LINE, nvp.w6, + (report_addr >> 24) & 0xfffffff); + nvp.w7 = xive_set_field32(NVP2_W7_REPORTING_LINE, nvp.w7, + report_addr & 0xffffff); + xive_copy_struct(qts, &nvp, nvp_addr, sizeof(nvp)); +} + +static uint64_t get_cl_pair_addr(Xive2Nvp *nvp) +{ + uint64_t upper = xive_get_field32(0x0fffffff, nvp->w6); + uint64_t lower = xive_get_field32(0xffffff00, nvp->w7); + return (upper << 32) | (lower << 8); +} + +void get_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair) +{ + uint64_t addr = get_cl_pair_addr(nvp); + xive_get_struct(qts, addr, cl_pair, XIVE_REPORT_SIZE); +} + +void set_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair) +{ + uint64_t addr = get_cl_pair_addr(nvp); + xive_copy_struct(qts, cl_pair, addr, XIVE_REPORT_SIZE); +} + +void set_nvg(QTestState *qts, uint32_t index, uint8_t next) +{ + uint64_t nvg_addr; + Xive2Nvgc nvg; + + nvg_addr = XIVE_NVG_MEM + (uint64_t)index * sizeof(Xive2Nvgc); + + memset(&nvg, 0, sizeof(nvg)); + nvg.w0 = xive_set_field32(NVGC2_W0_VALID, 0, 1); + nvg.w0 = xive_set_field32(NVGC2_W0_PGONEXT, nvg.w0, next); + xive_copy_struct(qts, &nvg, nvg_addr, sizeof(nvg)); +} + +void set_eas(QTestState *qts, uint32_t index, uint32_t end_index, + uint32_t data) +{ + uint64_t eas_addr; + Xive2Eas eas; + + eas_addr = XIVE_EAS_MEM + (uint64_t)index * sizeof(Xive2Eas); + + memset(&eas, 0, sizeof(eas)); + eas.w = xive_set_field64(EAS2_VALID, 0, 1); + eas.w = xive_set_field64(EAS2_END_INDEX, eas.w, end_index); + eas.w = xive_set_field64(EAS2_END_DATA, eas.w, data); + xive_copy_struct(qts, &eas, eas_addr, sizeof(eas)); +} + +void set_end(QTestState *qts, uint32_t index, uint32_t nvp_index, + uint8_t priority, bool i) +{ + uint64_t end_addr, queue_addr, queue_hi, queue_lo; + uint8_t queue_size; + Xive2End end; + + end_addr = XIVE_END_MEM + (uint64_t)index * sizeof(Xive2End); + queue_addr = xive_get_queue_addr(index); + queue_hi = (queue_addr >> 32) & END2_W2_EQ_ADDR_HI; + queue_lo = queue_addr & END2_W3_EQ_ADDR_LO; + queue_size = ctz16(XIVE_QUEUE_SIZE) - 12; + + memset(&end, 0, sizeof(end)); + end.w0 = xive_set_field32(END2_W0_VALID, 0, 1); + end.w0 = xive_set_field32(END2_W0_ENQUEUE, end.w0, 1); + end.w0 = xive_set_field32(END2_W0_UCOND_NOTIFY, end.w0, 1); + end.w0 = xive_set_field32(END2_W0_BACKLOG, end.w0, 1); + + end.w1 = xive_set_field32(END2_W1_GENERATION, 0, 1); + + end.w2 = cpu_to_be32(queue_hi); + + end.w3 = cpu_to_be32(queue_lo); + end.w3 = xive_set_field32(END2_W3_QSIZE, end.w3, queue_size); + + end.w6 = xive_set_field32(END2_W6_IGNORE, 0, i); + end.w6 = xive_set_field32(END2_W6_VP_OFFSET, end.w6, nvp_index); + + end.w7 = xive_set_field32(END2_W7_F0_PRIORITY, 0, priority); + xive_copy_struct(qts, &end, end_addr, sizeof(end)); +} + diff --git a/tests/qtest/pnv-xive2-common.h b/tests/qtest/pnv-xive2-common.h new file mode 100644 index 0000000000..9ae34771aa --- /dev/null +++ b/tests/qtest/pnv-xive2-common.h @@ -0,0 +1,111 @@ +/* + * QTest testcase for PowerNV 10 interrupt controller (xive2) + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TEST_PNV_XIVE2_COMMON_H +#define TEST_PNV_XIVE2_COMMON_H + +#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) +#define PPC_BIT32(bit) (0x80000000 >> (bit)) +#define PPC_BIT8(bit) (0x80 >> (bit)) +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) +#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ + PPC_BIT32(bs)) +#include "qemu/bswap.h" +#include "hw/intc/pnv_xive2_regs.h" +#include "hw/ppc/xive_regs.h" +#include "hw/ppc/xive2_regs.h" + +/* + * sizing: + * 128 interrupts + * => ESB BAR range: 16M + * 256 ENDs + * => END BAR range: 16M + * 256 VPs + * => NVPG,NVC BAR range: 32M + */ +#define MAX_IRQS 128 +#define MAX_ENDS 256 +#define MAX_VPS 256 + +#define XIVE_PAGE_SHIFT 16 + +#define XIVE_TRIGGER_PAGE 0 +#define XIVE_EOI_PAGE 1 + +#define XIVE_IC_ADDR 0x0006030200000000ull +#define XIVE_IC_TM_INDIRECT (XIVE_IC_ADDR + (256 << XIVE_PAGE_SHIFT)) +#define XIVE_IC_BAR ((0x3ull << 62) | XIVE_IC_ADDR) +#define XIVE_TM_BAR 0xc006030203180000ull +#define XIVE_ESB_ADDR 0x0006050000000000ull +#define XIVE_ESB_BAR ((0x3ull << 62) | XIVE_ESB_ADDR) +#define XIVE_END_BAR 0xc006060000000000ull +#define XIVE_NVPG_ADDR 0x0006040000000000ull +#define XIVE_NVPG_BAR ((0x3ull << 62) | XIVE_NVPG_ADDR) +#define XIVE_NVC_ADDR 0x0006030208000000ull +#define XIVE_NVC_BAR ((0x3ull << 62) | XIVE_NVC_ADDR) + +/* + * Memory layout + * A check is done when a table is configured to ensure that the max + * size of the resource fits in the table. + */ +#define XIVE_VST_SIZE 0x10000ull /* must be at least 4k */ + +#define XIVE_MEM_START 0x10000000ull +#define XIVE_ESB_MEM XIVE_MEM_START +#define XIVE_EAS_MEM (XIVE_ESB_MEM + XIVE_VST_SIZE) +#define XIVE_END_MEM (XIVE_EAS_MEM + XIVE_VST_SIZE) +#define XIVE_NVP_MEM (XIVE_END_MEM + XIVE_VST_SIZE) +#define XIVE_NVG_MEM (XIVE_NVP_MEM + XIVE_VST_SIZE) +#define XIVE_NVC_MEM (XIVE_NVG_MEM + XIVE_VST_SIZE) +#define XIVE_SYNC_MEM (XIVE_NVC_MEM + XIVE_VST_SIZE) +#define XIVE_QUEUE_MEM (XIVE_SYNC_MEM + XIVE_VST_SIZE) +#define XIVE_QUEUE_SIZE 4096 /* per End */ +#define XIVE_REPORT_MEM (XIVE_QUEUE_MEM + XIVE_QUEUE_SIZE * MAX_VPS) +#define XIVE_REPORT_SIZE 256 /* two cache lines per NVP */ +#define XIVE_MEM_END (XIVE_REPORT_MEM + XIVE_REPORT_SIZE * MAX_VPS) + +#define P10_XSCOM_BASE 0x000603fc00000000ull +#define XIVE_XSCOM 0x2010800ull + +#define XIVE_ESB_RESET 0b00 +#define XIVE_ESB_OFF 0b01 +#define XIVE_ESB_PENDING 0b10 +#define XIVE_ESB_QUEUED 0b11 + +#define XIVE_ESB_GET 0x800 +#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ +#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ +#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ +#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ + +#define XIVE_ESB_STORE_EOI 0x400 /* Store */ + + +extern uint64_t pnv_xive_xscom_read(QTestState *qts, uint32_t reg); +extern void pnv_xive_xscom_write(QTestState *qts, uint32_t reg, uint64_t val); +extern uint64_t xive_get_queue_addr(uint32_t end_index); +extern uint8_t get_esb(QTestState *qts, uint32_t index, uint8_t page, + uint32_t offset); +extern void set_esb(QTestState *qts, uint32_t index, uint8_t page, + uint32_t offset, uint32_t val); +extern void get_nvp(QTestState *qts, uint32_t index, Xive2Nvp* nvp); +extern void set_nvp(QTestState *qts, uint32_t index, uint8_t first); +extern void get_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair); +extern void set_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair); +extern void set_nvg(QTestState *qts, uint32_t index, uint8_t next); +extern void set_eas(QTestState *qts, uint32_t index, uint32_t end_index, + uint32_t data); +extern void set_end(QTestState *qts, uint32_t index, uint32_t nvp_index, + uint8_t priority, bool i); + + +void test_flush_sync_inject(QTestState *qts); + +#endif /* TEST_PNV_XIVE2_COMMON_H */ diff --git a/tests/qtest/pnv-xive2-flush-sync.c b/tests/qtest/pnv-xive2-flush-sync.c new file mode 100644 index 0000000000..3b32446adb --- /dev/null +++ b/tests/qtest/pnv-xive2-flush-sync.c @@ -0,0 +1,205 @@ +/* + * QTest testcase for PowerNV 10 interrupt controller (xive2) + * - Test cache flush/queue sync injection + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "libqtest.h" + +#include "pnv-xive2-common.h" +#include "hw/intc/pnv_xive2_regs.h" +#include "hw/ppc/xive_regs.h" +#include "hw/ppc/xive2_regs.h" + +#define PNV_XIVE2_QUEUE_IPI 0x00 +#define PNV_XIVE2_QUEUE_HW 0x01 +#define PNV_XIVE2_QUEUE_NXC 0x02 +#define PNV_XIVE2_QUEUE_INT 0x03 +#define PNV_XIVE2_QUEUE_OS 0x04 +#define PNV_XIVE2_QUEUE_POOL 0x05 +#define PNV_XIVE2_QUEUE_HARD 0x06 +#define PNV_XIVE2_CACHE_ENDC 0x08 +#define PNV_XIVE2_CACHE_ESBC 0x09 +#define PNV_XIVE2_CACHE_EASC 0x0a +#define PNV_XIVE2_QUEUE_NXC_LD_LCL_NCO 0x10 +#define PNV_XIVE2_QUEUE_NXC_LD_LCL_CO 0x11 +#define PNV_XIVE2_QUEUE_NXC_ST_LCL_NCI 0x12 +#define PNV_XIVE2_QUEUE_NXC_ST_LCL_CI 0x13 +#define PNV_XIVE2_QUEUE_NXC_ST_RMT_NCI 0x14 +#define PNV_XIVE2_QUEUE_NXC_ST_RMT_CI 0x15 +#define PNV_XIVE2_CACHE_NXC 0x18 + +#define PNV_XIVE2_SYNC_IPI 0x000 +#define PNV_XIVE2_SYNC_HW 0x080 +#define PNV_XIVE2_SYNC_NxC 0x100 +#define PNV_XIVE2_SYNC_INT 0x180 +#define PNV_XIVE2_SYNC_OS_ESC 0x200 +#define PNV_XIVE2_SYNC_POOL_ESC 0x280 +#define PNV_XIVE2_SYNC_HARD_ESC 0x300 +#define PNV_XIVE2_SYNC_NXC_LD_LCL_NCO 0x800 +#define PNV_XIVE2_SYNC_NXC_LD_LCL_CO 0x880 +#define PNV_XIVE2_SYNC_NXC_ST_LCL_NCI 0x900 +#define PNV_XIVE2_SYNC_NXC_ST_LCL_CI 0x980 +#define PNV_XIVE2_SYNC_NXC_ST_RMT_NCI 0xA00 +#define PNV_XIVE2_SYNC_NXC_ST_RMT_CI 0xA80 + + +static uint64_t get_sync_addr(uint32_t src_pir, int ic_topo_id, int type) +{ + int thread_nr = src_pir & 0x7f; + uint64_t addr = XIVE_SYNC_MEM + thread_nr * 512 + ic_topo_id * 32 + type; + return addr; +} + +static uint8_t get_sync(QTestState *qts, uint32_t src_pir, int ic_topo_id, + int type) +{ + uint64_t addr = get_sync_addr(src_pir, ic_topo_id, type); + return qtest_readb(qts, addr); +} + +static void clr_sync(QTestState *qts, uint32_t src_pir, int ic_topo_id, + int type) +{ + uint64_t addr = get_sync_addr(src_pir, ic_topo_id, type); + qtest_writeb(qts, addr, 0x0); +} + +static void inject_cache_flush(QTestState *qts, int ic_topo_id, + uint64_t scom_addr) +{ + (void)ic_topo_id; + pnv_xive_xscom_write(qts, scom_addr, 0); +} + +static void inject_queue_sync(QTestState *qts, int ic_topo_id, uint64_t offset) +{ + (void)ic_topo_id; + uint64_t addr = XIVE_IC_ADDR + (VST_SYNC << XIVE_PAGE_SHIFT) + offset; + qtest_writeq(qts, addr, 0); +} + +static void inject_op(QTestState *qts, int ic_topo_id, int type) +{ + switch (type) { + case PNV_XIVE2_QUEUE_IPI: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_IPI); + break; + case PNV_XIVE2_QUEUE_HW: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_HW); + break; + case PNV_XIVE2_QUEUE_NXC: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_NxC); + break; + case PNV_XIVE2_QUEUE_INT: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_INT); + break; + case PNV_XIVE2_QUEUE_OS: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_OS_ESC); + break; + case PNV_XIVE2_QUEUE_POOL: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_POOL_ESC); + break; + case PNV_XIVE2_QUEUE_HARD: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_HARD_ESC); + break; + case PNV_XIVE2_CACHE_ENDC: + inject_cache_flush(qts, ic_topo_id, X_VC_ENDC_FLUSH_INJECT); + break; + case PNV_XIVE2_CACHE_ESBC: + inject_cache_flush(qts, ic_topo_id, X_VC_ESBC_FLUSH_INJECT); + break; + case PNV_XIVE2_CACHE_EASC: + inject_cache_flush(qts, ic_topo_id, X_VC_EASC_FLUSH_INJECT); + break; + case PNV_XIVE2_QUEUE_NXC_LD_LCL_NCO: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_NXC_LD_LCL_NCO); + break; + case PNV_XIVE2_QUEUE_NXC_LD_LCL_CO: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_NXC_LD_LCL_CO); + break; + case PNV_XIVE2_QUEUE_NXC_ST_LCL_NCI: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_NXC_ST_LCL_NCI); + break; + case PNV_XIVE2_QUEUE_NXC_ST_LCL_CI: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_NXC_ST_LCL_CI); + break; + case PNV_XIVE2_QUEUE_NXC_ST_RMT_NCI: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_NXC_ST_RMT_NCI); + break; + case PNV_XIVE2_QUEUE_NXC_ST_RMT_CI: + inject_queue_sync(qts, ic_topo_id, PNV_XIVE2_SYNC_NXC_ST_RMT_CI); + break; + case PNV_XIVE2_CACHE_NXC: + inject_cache_flush(qts, ic_topo_id, X_PC_NXC_FLUSH_INJECT); + break; + default: + g_assert_not_reached(); + break; + } +} + +const uint8_t xive_inject_tests[] = { + PNV_XIVE2_QUEUE_IPI, + PNV_XIVE2_QUEUE_HW, + PNV_XIVE2_QUEUE_NXC, + PNV_XIVE2_QUEUE_INT, + PNV_XIVE2_QUEUE_OS, + PNV_XIVE2_QUEUE_POOL, + PNV_XIVE2_QUEUE_HARD, + PNV_XIVE2_CACHE_ENDC, + PNV_XIVE2_CACHE_ESBC, + PNV_XIVE2_CACHE_EASC, + PNV_XIVE2_QUEUE_NXC_LD_LCL_NCO, + PNV_XIVE2_QUEUE_NXC_LD_LCL_CO, + PNV_XIVE2_QUEUE_NXC_ST_LCL_NCI, + PNV_XIVE2_QUEUE_NXC_ST_LCL_CI, + PNV_XIVE2_QUEUE_NXC_ST_RMT_NCI, + PNV_XIVE2_QUEUE_NXC_ST_RMT_CI, + PNV_XIVE2_CACHE_NXC, +}; + +void test_flush_sync_inject(QTestState *qts) +{ + int ic_topo_id = 0; + + /* + * Writes performed by qtest are not done in the context of a thread. + * This means that QEMU XIVE code doesn't have a way to determine what + * thread is originating the write. In order to allow for some testing, + * QEMU XIVE code will assume a PIR of 0 when unable to determine the + * source thread for cache flush and queue sync inject operations. + * See hw/intc/pnv_xive2.c: pnv_xive2_inject_notify() for details. + */ + int src_pir = 0; + int test_nr; + uint8_t byte; + + printf("# ============================================================\n"); + printf("# Starting cache flush/queue sync injection tests...\n"); + + for (test_nr = 0; test_nr < sizeof(xive_inject_tests); + test_nr++) { + int op_type = xive_inject_tests[test_nr]; + + printf("# Running test %d\n", test_nr); + + /* start with status byte set to 0 */ + clr_sync(qts, src_pir, ic_topo_id, op_type); + byte = get_sync(qts, src_pir, ic_topo_id, op_type); + g_assert_cmphex(byte, ==, 0); + + /* request cache flush or queue sync operation */ + inject_op(qts, ic_topo_id, op_type); + + /* verify that status byte was written to 0xff */ + byte = get_sync(qts, src_pir, ic_topo_id, op_type); + g_assert_cmphex(byte, ==, 0xff); + + clr_sync(qts, src_pir, ic_topo_id, op_type); + } +} + diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c new file mode 100644 index 0000000000..dd19e88861 --- /dev/null +++ b/tests/qtest/pnv-xive2-test.c @@ -0,0 +1,344 @@ +/* + * QTest testcase for PowerNV 10 interrupt controller (xive2) + * - Test irq to hardware thread + * - Test 'Pull Thread Context to Odd Thread Reporting Line' + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "libqtest.h" + +#include "pnv-xive2-common.h" +#include "hw/intc/pnv_xive2_regs.h" +#include "hw/ppc/xive_regs.h" +#include "hw/ppc/xive2_regs.h" + +#define SMT 4 /* some tests will break if less than 4 */ + + +static void set_table(QTestState *qts, uint64_t type, uint64_t addr) +{ + uint64_t vsd, size, log_size; + + /* + * First, let's make sure that all the resources used fit in the + * given table. + */ + switch (type) { + case VST_ESB: + size = MAX_IRQS / 4; + break; + case VST_EAS: + size = MAX_IRQS * 8; + break; + case VST_END: + size = MAX_ENDS * 32; + break; + case VST_NVP: + case VST_NVG: + case VST_NVC: + size = MAX_VPS * 32; + break; + case VST_SYNC: + size = 64 * 1024; + break; + default: + g_assert_not_reached(); + } + + g_assert_cmpuint(size, <=, XIVE_VST_SIZE); + log_size = ctzl(XIVE_VST_SIZE) - 12; + + vsd = ((uint64_t) VSD_MODE_EXCLUSIVE) << 62 | addr | log_size; + pnv_xive_xscom_write(qts, X_VC_VSD_TABLE_ADDR, type << 48); + pnv_xive_xscom_write(qts, X_VC_VSD_TABLE_DATA, vsd); + + if (type != VST_EAS && type != VST_IC && type != VST_ERQ) { + pnv_xive_xscom_write(qts, X_PC_VSD_TABLE_ADDR, type << 48); + pnv_xive_xscom_write(qts, X_PC_VSD_TABLE_DATA, vsd); + } +} + +static void set_tima8(QTestState *qts, uint32_t pir, uint32_t offset, + uint8_t b) +{ + uint64_t ic_addr; + + ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); + qtest_writeb(qts, ic_addr + offset, b); +} + +static void set_tima32(QTestState *qts, uint32_t pir, uint32_t offset, + uint32_t l) +{ + uint64_t ic_addr; + + ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); + qtest_writel(qts, ic_addr + offset, l); +} + +static uint8_t get_tima8(QTestState *qts, uint32_t pir, uint32_t offset) +{ + uint64_t ic_addr; + + ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); + return qtest_readb(qts, ic_addr + offset); +} + +static uint16_t get_tima16(QTestState *qts, uint32_t pir, uint32_t offset) +{ + uint64_t ic_addr; + + ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); + return qtest_readw(qts, ic_addr + offset); +} + +static uint32_t get_tima32(QTestState *qts, uint32_t pir, uint32_t offset) +{ + uint64_t ic_addr; + + ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); + return qtest_readl(qts, ic_addr + offset); +} + +static void reset_pool_threads(QTestState *qts) +{ + uint8_t first_group = 0; + int i; + + for (i = 0; i < SMT; i++) { + uint32_t nvp_idx = 0x100 + i; + set_nvp(qts, nvp_idx, first_group); + set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD0, 0x000000ff); + set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD1, 0); + set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | nvp_idx); + } +} + +static void reset_hw_threads(QTestState *qts) +{ + uint8_t first_group = 0; + uint32_t w1 = 0x000000ff; + int i; + + if (SMT >= 4) { + /* define 2 groups of 2, part of a bigger group of size 4 */ + set_nvg(qts, 0x80, 0x02); + set_nvg(qts, 0x82, 0x02); + set_nvg(qts, 0x81, 0); + first_group = 0x01; + w1 = 0x000300ff; + } + + for (i = 0; i < SMT; i++) { + set_nvp(qts, 0x80 + i, first_group); + set_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD0, 0x00ff00ff); + set_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD1, w1); + set_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD2, 0x80000000); + } +} + +static void reset_state(QTestState *qts) +{ + size_t mem_used = XIVE_MEM_END - XIVE_MEM_START; + + qtest_memset(qts, XIVE_MEM_START, 0, mem_used); + reset_hw_threads(qts); + reset_pool_threads(qts); +} + +static void init_xive(QTestState *qts) +{ + uint64_t val1, val2, range; + + /* + * We can take a few shortcuts here, as we know the default values + * used for xive initialization + */ + + /* + * Set the BARs. + * We reuse the same values used by firmware to ease debug. + */ + pnv_xive_xscom_write(qts, X_CQ_IC_BAR, XIVE_IC_BAR); + pnv_xive_xscom_write(qts, X_CQ_TM_BAR, XIVE_TM_BAR); + + /* ESB and NVPG use 2 pages per resource. The others only one page */ + range = (MAX_IRQS << 17) >> 25; + val1 = XIVE_ESB_BAR | range; + pnv_xive_xscom_write(qts, X_CQ_ESB_BAR, val1); + + range = (MAX_ENDS << 16) >> 25; + val1 = XIVE_END_BAR | range; + pnv_xive_xscom_write(qts, X_CQ_END_BAR, val1); + + range = (MAX_VPS << 17) >> 25; + val1 = XIVE_NVPG_BAR | range; + pnv_xive_xscom_write(qts, X_CQ_NVPG_BAR, val1); + + range = (MAX_VPS << 16) >> 25; + val1 = XIVE_NVC_BAR | range; + pnv_xive_xscom_write(qts, X_CQ_NVC_BAR, val1); + + /* + * Enable hw threads. + * We check the value written. Useless with current + * implementation, but it validates the xscom read path and it's + * what the hardware procedure says + */ + val1 = 0xF000000000000000ull; /* core 0, 4 threads */ + pnv_xive_xscom_write(qts, X_TCTXT_EN0, val1); + val2 = pnv_xive_xscom_read(qts, X_TCTXT_EN0); + g_assert_cmphex(val1, ==, val2); + + /* Memory tables */ + set_table(qts, VST_ESB, XIVE_ESB_MEM); + set_table(qts, VST_EAS, XIVE_EAS_MEM); + set_table(qts, VST_END, XIVE_END_MEM); + set_table(qts, VST_NVP, XIVE_NVP_MEM); + set_table(qts, VST_NVG, XIVE_NVG_MEM); + set_table(qts, VST_NVC, XIVE_NVC_MEM); + set_table(qts, VST_SYNC, XIVE_SYNC_MEM); + + reset_hw_threads(qts); + reset_pool_threads(qts); +} + +static void test_hw_irq(QTestState *qts) +{ + uint32_t irq = 2; + uint32_t irq_data = 0x600df00d; + uint32_t end_index = 5; + uint32_t target_pir = 1; + uint32_t target_nvp = 0x80 + target_pir; + uint8_t priority = 5; + uint32_t reg32; + uint16_t reg16; + uint8_t pq, nsr, cppr; + + printf("# ============================================================\n"); + printf("# Testing irq %d to hardware thread %d\n", irq, target_pir); + + /* irq config */ + set_eas(qts, irq, end_index, irq_data); + set_end(qts, end_index, target_nvp, priority, false /* group */); + + /* enable and trigger irq */ + get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00); + set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0); + + /* check irq is raised on cpu */ + pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, ==, XIVE_ESB_PENDING); + + reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0); + nsr = reg32 >> 24; + cppr = (reg32 >> 16) & 0xFF; + g_assert_cmphex(nsr, ==, 0x80); + g_assert_cmphex(cppr, ==, 0xFF); + + /* ack the irq */ + reg16 = get_tima16(qts, target_pir, TM_SPC_ACK_HV_REG); + nsr = reg16 >> 8; + cppr = reg16 & 0xFF; + g_assert_cmphex(nsr, ==, 0x80); + g_assert_cmphex(cppr, ==, priority); + + /* check irq data is what was configured */ + reg32 = qtest_readl(qts, xive_get_queue_addr(end_index)); + g_assert_cmphex((reg32 & 0x7fffffff), ==, (irq_data & 0x7fffffff)); + + /* End Of Interrupt */ + set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0); + pq = get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET); + g_assert_cmpuint(pq, ==, XIVE_ESB_RESET); + + /* reset CPPR */ + set_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_CPPR, 0xFF); + reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0); + nsr = reg32 >> 24; + cppr = (reg32 >> 16) & 0xFF; + g_assert_cmphex(nsr, ==, 0x00); + g_assert_cmphex(cppr, ==, 0xFF); +} + +#define XIVE_ODD_CL 0x80 +static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts) +{ + uint32_t target_pir = 1; + uint32_t target_nvp = 0x80 + target_pir; + Xive2Nvp nvp; + uint8_t cl_pair[XIVE_REPORT_SIZE]; + uint32_t qw1w0, qw3w0, qw1w2, qw2w2; + uint8_t qw3b8; + uint32_t cl_word; + uint32_t word2; + + printf("# ============================================================\n"); + printf("# Testing 'Pull Thread Context to Odd Thread Reporting Line'\n"); + + /* clear odd cache line prior to pull operation */ + memset(cl_pair, 0, sizeof(cl_pair)); + get_nvp(qts, target_nvp, &nvp); + set_cl_pair(qts, &nvp, cl_pair); + + /* Read some values from TIMA that we expect to see in cacheline */ + qw1w0 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD0); + qw3w0 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0); + qw1w2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); + qw2w2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); + qw3b8 = get_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2); + + /* Execute the pull operation */ + set_tima8(qts, target_pir, TM_SPC_PULL_PHYS_CTX_OL, 0); + + /* Verify odd cache line values match TIMA after pull operation */ + get_cl_pair(qts, &nvp, cl_pair); + memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD0], 4); + g_assert_cmphex(qw1w0, ==, be32_to_cpu(cl_word)); + memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW3_HV_PHYS + TM_WORD0], 4); + g_assert_cmphex(qw3w0, ==, be32_to_cpu(cl_word)); + memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD2], 4); + g_assert_cmphex(qw1w2, ==, be32_to_cpu(cl_word)); + memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW2_HV_POOL + TM_WORD2], 4); + g_assert_cmphex(qw2w2, ==, be32_to_cpu(cl_word)); + g_assert_cmphex(qw3b8, ==, + cl_pair[XIVE_ODD_CL + TM_QW3_HV_PHYS + TM_WORD2]); + + /* Verify that all TIMA valid bits for target thread are cleared */ + word2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); + g_assert_cmphex(xive_get_field32(TM_QW1W2_VO, word2), ==, 0); + word2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); + g_assert_cmphex(xive_get_field32(TM_QW2W2_VP, word2), ==, 0); + word2 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2); + g_assert_cmphex(xive_get_field32(TM_QW3W2_VT, word2), ==, 0); +} +static void test_xive(void) +{ + QTestState *qts; + + qts = qtest_initf("-M powernv10 -smp %d,cores=1,threads=%d -nographic " + "-nodefaults -serial mon:stdio -S " + "-d guest_errors -trace '*xive*'", + SMT, SMT); + init_xive(qts); + + test_hw_irq(qts); + + /* omit reset_state here and use settings from test_hw_irq */ + test_pull_thread_ctx_to_odd_thread_cl(qts); + + reset_state(qts); + test_flush_sync_inject(qts); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("xive2", test_xive); + return g_test_run(); +} From patchwork Mon Nov 4 00:18:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A211D1119A for ; Mon, 4 Nov 2024 00:30:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7ksn-0002Ql-Bw; Sun, 03 Nov 2024 19:23:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7ks2-0000oX-ET; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:22:57 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan , "Edgar E . Iglesias" Subject: [PULL 63/67] hw/ppc: Consolidate e500 initial mapping creation functions Date: Mon, 4 Nov 2024 10:18:52 +1000 Message-ID: <20241104001900.682660-64-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=npiggin@gmail.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: BALATON Zoltan Add booke206_set_tlb() utility function and use it to replace very similar create_initial_mapping functions in e500 machines. Signed-off-by: BALATON Zoltan Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Nicholas Piggin --- hw/ppc/e500.c | 41 +++++++++++++++++++---------------------- hw/ppc/e500.h | 2 -- hw/ppc/ppce500_spin.c | 30 +++++++++--------------------- include/hw/ppc/ppc.h | 5 +++++ 4 files changed, 33 insertions(+), 45 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b760c6d6a2..6433348072 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -721,11 +721,21 @@ static int ppce500_prep_device_tree(PPCE500MachineState *machine, kernel_base, kernel_size, true); } -hwaddr booke206_page_size_to_tlb(uint64_t size) +static hwaddr booke206_page_size_to_tlb(uint64_t size) { return 63 - clz64(size / KiB); } +void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa, + hwaddr len) +{ + tlb->mas1 = booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT; + tlb->mas1 |= MAS1_VALID; + tlb->mas2 = va & TARGET_PAGE_MASK; + tlb->mas7_3 = pa & TARGET_PAGE_MASK; + tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; +} + static int booke206_initial_map_tsize(CPUPPCState *env) { struct boot_info *bi = env->load_info; @@ -751,25 +761,6 @@ static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) return (1ULL << 10 << tsize); } -/* Create -kernel TLB entries for BookE. */ -static void mmubooke_create_initial_mapping(CPUPPCState *env) -{ - ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); - hwaddr size; - int ps; - - ps = booke206_initial_map_tsize(env); - size = (ps << MAS1_TSIZE_SHIFT); - tlb->mas1 = MAS1_VALID | size; - tlb->mas2 = 0; - tlb->mas7_3 = 0; - tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; - -#ifdef CONFIG_KVM - env->tlb_dirty = true; -#endif -} - static void ppce500_cpu_reset_sec(void *opaque) { PowerPCCPU *cpu = opaque; @@ -786,6 +777,8 @@ static void ppce500_cpu_reset(void *opaque) CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; struct boot_info *bi = env->load_info; + uint64_t map_size = mmubooke_initial_mapsize(env); + ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); cpu_reset(cs); @@ -796,11 +789,15 @@ static void ppce500_cpu_reset(void *opaque) env->gpr[4] = 0; env->gpr[5] = 0; env->gpr[6] = EPAPR_MAGIC; - env->gpr[7] = mmubooke_initial_mapsize(env); + env->gpr[7] = map_size; env->gpr[8] = 0; env->gpr[9] = 0; env->nip = bi->entry; - mmubooke_create_initial_mapping(env); + /* create initial mapping */ + booke206_set_tlb(tlb, 0, 0, map_size); +#ifdef CONFIG_KVM + env->tlb_dirty = true; +#endif } static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 8c09ef92e4..01db102625 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -41,8 +41,6 @@ struct PPCE500MachineClass { void ppce500_init(MachineState *machine); -hwaddr booke206_page_size_to_tlb(uint64_t size); - #define TYPE_PPCE500_MACHINE "ppce500-base-machine" OBJECT_DECLARE_TYPE(PPCE500MachineState, PPCE500MachineClass, PPCE500_MACHINE) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index e08739a443..93b16320d4 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -33,6 +33,7 @@ #include "hw/hw.h" #include "hw/sysbus.h" #include "sysemu/hw_accel.h" +#include "hw/ppc/ppc.h" #include "e500.h" #include "qom/object.h" @@ -70,30 +71,12 @@ static void spin_reset(DeviceState *dev) } } -static void mmubooke_create_initial_mapping(CPUPPCState *env, - target_ulong va, - hwaddr pa, - hwaddr len) -{ - ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1); - hwaddr size; - - size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT); - tlb->mas1 = MAS1_VALID | size; - tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M; - tlb->mas7_3 = pa & TARGET_PAGE_MASK; - tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; -#ifdef CONFIG_KVM - env->tlb_dirty = true; -#endif -} - static void spin_kick(CPUState *cs, run_on_cpu_data data) { CPUPPCState *env = cpu_env(cs); SpinInfo *curspin = data.host_ptr; - hwaddr map_size = 64 * MiB; - hwaddr map_start; + hwaddr map_start, map_size = 64 * MiB; + ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1); cpu_synchronize_state(cs); stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); @@ -107,7 +90,12 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data) env->gpr[9] = 0; map_start = ldq_p(&curspin->addr) & ~(map_size - 1); - mmubooke_create_initial_mapping(env, 0, map_start, map_size); + /* create initial mapping */ + booke206_set_tlb(tlb, 0, map_start, map_size); + tlb->mas2 |= MAS2_M; +#ifdef CONFIG_KVM + env->tlb_dirty = true; +#endif cs->halted = 0; cs->exception_index = -1; diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index d5d119ea7f..070524b02e 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -116,6 +116,11 @@ enum { #define PPC_SERIAL_MM_BAUDBASE 399193 +#ifndef CONFIG_USER_ONLY +void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa, + hwaddr len); +#endif + /* ppc_booke.c */ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags); #endif From patchwork Mon Nov 4 00:18:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7156BD11198 for ; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:23:01 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan , "Edgar E . Iglesias" Subject: [PULL 64/67] hw/ppc: Consolidate ppc440 initial mapping creation functions Date: Mon, 4 Nov 2024 10:18:53 +1000 Message-ID: <20241104001900.682660-65-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=npiggin@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: BALATON Zoltan Add a utility function and use it to replace very similar create_initial_mapping functions in 440 based machines. Signed-off-by: BALATON Zoltan Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Nicholas Piggin --- hw/ppc/ppc440_bamboo.c | 28 +++----------------------- hw/ppc/ppc_booke.c | 10 ++++++++++ hw/ppc/sam460ex.c | 45 ++++++++++-------------------------------- hw/ppc/virtex_ml507.c | 28 +++----------------------- include/hw/ppc/ppc.h | 2 ++ 5 files changed, 28 insertions(+), 85 deletions(-) diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 96d9ce65c2..a55f108434 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -110,29 +110,6 @@ static int bamboo_load_device_tree(MachineState *machine, return 0; } -/* Create reset TLB entries for BookE, spanning the 32bit addr space. */ -static void mmubooke_create_initial_mapping(CPUPPCState *env, - target_ulong va, - hwaddr pa) -{ - ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; - - tlb->attr = 0; - tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1U << 31; /* up to 0x80000000 */ - tlb->EPN = va & TARGET_PAGE_MASK; - tlb->RPN = pa & TARGET_PAGE_MASK; - tlb->PID = 0; - - tlb = &env->tlb.tlbe[1]; - tlb->attr = 0; - tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1U << 31; /* up to 0xffffffff */ - tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; - tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; - tlb->PID = 0; -} - static void main_cpu_reset(void *opaque) { PowerPCCPU *cpu = opaque; @@ -143,8 +120,9 @@ static void main_cpu_reset(void *opaque) env->gpr[3] = FDT_ADDR; env->nip = entry; - /* Create a mapping for the kernel. */ - mmubooke_create_initial_mapping(env, 0, 0); + /* Create a mapping spanning the 32bit addr space. */ + booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1U << 31); + booke_set_tlb(&env->tlb.tlbe[1], 0x80000000, 0x80000000, 1U << 31); } static void bamboo_init(MachineState *machine) diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index ca22da196a..c8849e66ff 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -31,6 +31,16 @@ #include "hw/loader.h" #include "kvm_ppc.h" +void booke_set_tlb(ppcemb_tlb_t *tlb, target_ulong va, hwaddr pa, + target_ulong size) +{ + tlb->attr = 0; + tlb->prot = PAGE_RWX << 4 | PAGE_VALID; + tlb->size = size; + tlb->EPN = va & TARGET_PAGE_MASK; + tlb->RPN = pa & TARGET_PAGE_MASK; + tlb->PID = 0; +} /* Timer Control Register */ diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 1fce093ac8..78e2a46e75 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -213,38 +213,6 @@ static int sam460ex_load_device_tree(MachineState *machine, return fdt_size; } -/* Create reset TLB entries for BookE, mapping only the flash memory. */ -static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) -{ - ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; - - /* on reset the flash is mapped by a shadow TLB, - * but since we don't implement them we need to use - * the same values U-Boot will use to avoid a fault. - */ - tlb->attr = 0; - tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 0x10000000; /* up to 0xffffffff */ - tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; - tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; - tlb->PID = 0; -} - -/* Create reset TLB entries for BookE, spanning the 32bit addr space. */ -static void mmubooke_create_initial_mapping(CPUPPCState *env, - target_ulong va, - hwaddr pa) -{ - ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; - - tlb->attr = 0; - tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0x80000000 */ - tlb->EPN = va & TARGET_PAGE_MASK; - tlb->RPN = pa & TARGET_PAGE_MASK; - tlb->PID = 0; -} - static void main_cpu_reset(void *opaque) { PowerPCCPU *cpu = opaque; @@ -253,20 +221,27 @@ static void main_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); - /* either we have a kernel to boot or we jump to U-Boot */ + /* + * On reset the flash is mapped by a shadow TLB, but since we + * don't implement them we need to use the same values U-Boot + * will use to avoid a fault. + * either we have a kernel to boot or we jump to U-Boot + */ if (bi->entry != UBOOT_ENTRY) { env->gpr[1] = (16 * MiB) - 8; env->gpr[3] = FDT_ADDR; env->nip = bi->entry; /* Create a mapping for the kernel. */ - mmubooke_create_initial_mapping(env, 0, 0); + booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1 << 31); env->gpr[6] = tswap32(EPAPR_MAGIC); env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ } else { env->nip = UBOOT_ENTRY; - mmubooke_create_initial_mapping_uboot(env); + /* Create a mapping for U-Boot. */ + booke_set_tlb(&env->tlb.tlbe[0], 0xf0000000, 0xf0000000, 0x10000000); + env->tlb.tlbe[0].RPN |= 4; } } diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 235281e939..f378e5c4a9 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -67,29 +67,6 @@ static struct boot_info void *vfdt; } boot_info; -/* Create reset TLB entries for BookE, spanning the 32bit addr space. */ -static void mmubooke_create_initial_mapping(CPUPPCState *env, - target_ulong va, - hwaddr pa) -{ - ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; - - tlb->attr = 0; - tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1U << 31; /* up to 0x80000000 */ - tlb->EPN = va & TARGET_PAGE_MASK; - tlb->RPN = pa & TARGET_PAGE_MASK; - tlb->PID = 0; - - tlb = &env->tlb.tlbe[1]; - tlb->attr = 0; - tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1U << 31; /* up to 0xffffffff */ - tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; - tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; - tlb->PID = 0; -} - static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk) { PowerPCCPU *cpu; @@ -139,8 +116,9 @@ static void main_cpu_reset(void *opaque) env->gpr[3] = bi->fdt; env->nip = bi->bootstrap_pc; - /* Create a mapping for the kernel. */ - mmubooke_create_initial_mapping(env, 0, 0); + /* Create a mapping spanning the 32bit addr space. */ + booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1U << 31); + booke_set_tlb(&env->tlb.tlbe[1], 0x80000000, 0x80000000, 1U << 31); env->gpr[6] = tswap32(EPAPR_MAGIC); env->gpr[7] = bi->ima_size; } diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 070524b02e..8a14d623f8 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -119,6 +119,8 @@ enum { #ifndef CONFIG_USER_ONLY void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa, hwaddr len); +void booke_set_tlb(ppcemb_tlb_t *tlb, target_ulong va, hwaddr pa, + target_ulong size); #endif /* ppc_booke.c */ From patchwork Mon Nov 4 00:18:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD33DD11194 for ; Mon, 4 Nov 2024 00:25:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7ksz-0002dp-Ma; Sun, 03 Nov 2024 19:24:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7ks8-0001N7-9B; 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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:23:04 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= , =?utf-8?b?RnLDqWTDqXJp?= =?utf-8?b?YyBCYXJyYXQ=?= Subject: [PULL 65/67] MAINTAINERS: Remove myself from the PowerNV machines Date: Mon, 4 Nov 2024 10:18:54 +1000 Message-ID: <20241104001900.682660-66-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Cédric Le Goater It's been an amazing experience working on PowerNV systems all these years. Now it's time for IBM to take the lead on the QEMU machine and shape its future. I'm stepping back as the maintainer of PowerNV. Cc: Nicholas Piggin Cc: Frédéric Barrat Signed-off-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 64b4ffa91c..baf8c9b379 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1495,7 +1495,6 @@ F: tests/functional/test_ppc64_hv.py F: tests/functional/test_ppc64_tuxrun.py PowerNV (Non-Virtualized) -M: Cédric Le Goater M: Nicholas Piggin R: Frédéric Barrat L: qemu-ppc@nongnu.org From patchwork Mon Nov 4 00:18:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54762D11194 for ; Mon, 4 Nov 2024 00:27:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7ksZ-00025r-El; Sun, 03 Nov 2024 19:23:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7ksG-0001gz-Cp; Sun, 03 Nov 2024 19:23:17 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7ksE-0002rg-IP; Sun, 03 Nov 2024 19:23:16 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-720d5ada03cso2294366b3a.1; Sun, 03 Nov 2024 16:23:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679790; x=1731284590; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kQvvTBs9o0+GQ/IwCIJ/WgPOMyuLV1oDDUGAzHCQ7y8=; b=cAHgmpgV0UsE4dmyigW8WVoLberXmD82C7wMXJmE8ZNLkABR10GW5cmSwbT/BHiTO9 pMYA28vPIlj+3PmgPH4CGzEIr2JOIKnaA/8bTRSjtVeom3vehyEnVSLOzS0GlAyCC1Ds YoOYcTuRLhHFU6ytoP3iR9qtVtAGzV5Wjg8Fkg5wt0zRaMFH4JyeYwan9cVde/zOGwLW JIItvCvv1R8etp5Y41yGc5wumNeTiz9BGE8fWOXupmCoXwBxUYHDheyKCTEdJmSp3CES sXdZ7PARffl1AezKt4Zbmpg+rn6oQTcHvrMPIt+H0aFM6CIVh3dJ2jZh86Zu80dAq+ew ndqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679790; x=1731284590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kQvvTBs9o0+GQ/IwCIJ/WgPOMyuLV1oDDUGAzHCQ7y8=; b=kmZYJdxpXc7BMHqpcN6lJetxWge3LyUKrlSSnjk+uU/BBVDmOUZEyxW8X/te+WDjUD s08FLcdbBMOiZhY5a1MeoeQdp8zRJzBnRXMqo+HYMRBROk9oPDzkLvShsczls5Ihi6yS axf07keBoQoMKZOp3rHJ9VN/ZkCzaREMCvwF/OM2aGfbCEttNab/kjbeBKNaT9f437cg NWU5Bso19wpkHAK8XrQFfis0joDhsp3Em8vh6/CgoIJEZoKkXfOx50dn2mp4SEoQaLhK EOg26ahgREjyezOTFHy5DvrY/vRQLHaMoU2R74CM3iVh+o6R/FkGvIx2rKPuG8qe8nNj 1aOg== X-Forwarded-Encrypted: i=1; AJvYcCXpVy4mhjOunlgm1VGGe8Ofsc9FkW0bkNJnJMhkUEMdANj5cAkLrKvOkAnAANEe+Rvc+IfL5eVQvQ==@nongnu.org X-Gm-Message-State: AOJu0Yy7PHrw+IzoBHPXsWRxsGkdccBY/CAbLILpqwtaCI2HQgNeDQXM 56y7QTbUycCVWh7e41BQQbH04Rxs0SUancSNNlimKtENSDIXrUuYvfos8A== X-Google-Smtp-Source: AGHT+IGOyBcaFl4ICxeZZhHqBgL5UPV28AiP5bTcNaCZ5cYzHR37tcJpUSyai9vK8rxvMYQ2ZXRkOQ== X-Received: by 2002:a05:6a00:92a1:b0:71e:4414:eb21 with SMTP id d2e1a72fcca58-720b9db35a3mr20566009b3a.17.1730679788463; Sun, 03 Nov 2024 16:23:08 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.23.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:23:08 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= , Michael Kowal , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= Subject: [PULL 66/67] MAINTAINERS: Remove myself from XIVE Date: Mon, 4 Nov 2024 10:18:55 +1000 Message-ID: <20241104001900.682660-67-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=npiggin@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Cédric Le Goater Working on XIVE has been one of the most complex and fascinating experiences for me. It's been a real journey, and now it's time for IBM to take over and guide its future. I'm stepping back as the maintainer of XIVE. Cc: Michael Kowal Cc: Nicholas Piggin Cc: Frédéric Barrat Signed-off-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index baf8c9b379..840eebc944 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2618,7 +2618,6 @@ F: tests/qtest/fw_cfg-test.c T: git https://github.com/philmd/qemu.git fw_cfg-next XIVE -M: Cédric Le Goater R: Frédéric Barrat L: qemu-ppc@nongnu.org S: Odd Fixes From patchwork Mon Nov 4 00:18:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13860756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8552D11198 for ; Mon, 4 Nov 2024 00:28:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t7ksr-0002Rf-6L; Sun, 03 Nov 2024 19:23:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t7ksG-0001h8-J2; Sun, 03 Nov 2024 19:23:17 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t7ksF-0002rm-5f; Sun, 03 Nov 2024 19:23:16 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-20cd76c513cso27134195ad.3; Sun, 03 Nov 2024 16:23:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730679792; x=1731284592; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NeqjtniyFe+naXM0wN5zvD9S7mKNuzwkdgW2O7zUpxg=; b=GSgl8X4S9O+cpNGiu4GIm9OhD2H6X8THT230gg0UfYQntNRtZlP6/KfGJO8yx1qFum BF0W8KPnP9qAO2sLM8UzYQDl0XodTIC9Mtp6bdawAdlbgpJHYOQ2eMCWvFw/5CaLN04j Qz26Rsrw5rshvRtBEc1Rz+T6OMArsTDbsyRfHhy/u2pNBtjXAQghBPhGEK6LFXc6u6YM Z0feeCFe+gQcar5UjCBOam1Qd7/uac8YiGGmMBYKSwrSQbDMMHoiebRIYkPb659EMNld SCLBESxtMY+Niz5gc8VTrqZJQEqleTkp48Q/BBzUPPyvsPDt3+2LyHnvPx95rBbWFFud e1QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730679792; x=1731284592; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NeqjtniyFe+naXM0wN5zvD9S7mKNuzwkdgW2O7zUpxg=; b=p2m5Q6m8I8fQGusj0JzLKLmXNxcL6FIptEpp0cvmVd5qw43/fBj/d+40sxg4NnJJn2 w1CJ47kpMLV+Y9vrwrrsN7mTe2IS5uSWvuZr3g+kJYRAMdMP/b0FdPJyHeSaRU53VcmV iGshEaSl5mghbYEGClxnOM2wePXJRhZRqxvR2Iz5A5Ovogw1nqA/TLzC7q0ChIu+xWxx ii1vERP0XVQnLjbVInpEk3+WAsLvVSk8m/m2RQDO5HS6eR+WYfrXayOBOVfzwdWPj3wa i1KoqcM66WDC75jEiftmEzn6QQlCcARZmxUv0BXSGIXtC+xFM6hYZLLTMwNFksz3kiOD 4eVg== X-Forwarded-Encrypted: i=1; AJvYcCWJDbmDFxRuwh2y+ui4CcM8x5/22miBZ5kRAKPJTDHBLkRLulg1U/gbYMNHnDI1bsxORX+A7VYnIA==@nongnu.org X-Gm-Message-State: AOJu0YyjXtgGAVO7omOWtC9M2mS7YaYpY3bBT/ekY6QcoJ0nPu4z0Lrl gO68Hyn2uF/ENRx7D/tPrBPgMoZGE7M1QAKUOHYcgpLKGBUmYnlZwUhj/w== X-Google-Smtp-Source: AGHT+IEtBE06YU7PZoGPaNAsB65o7X9omExtWF2/sRQQigapfkdHtn8lnVaQijgwcH3mOmG6sGKVtQ== X-Received: by 2002:a17:903:124d:b0:20c:b9ca:c12d with SMTP id d9443c01a7336-210f76d685fmr254347285ad.38.1730679791692; Sun, 03 Nov 2024 16:23:11 -0800 (PST) Received: from wheely.local0.net (124-171-217-17.tpgi.com.au. [124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee45a0081esm5900648a12.59.2024.11.03.16.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 16:23:11 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, David Gibson , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PULL 67/67] MAINTAINERS: Remove myself as reviewer Date: Mon, 4 Nov 2024 10:18:56 +1000 Message-ID: <20241104001900.682660-68-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com> References: <20241104001900.682660-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=npiggin@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: David Gibson I've now well and truly moved on from ppc and qemu maintenance. I'm occupied with other things and am pretty much just ignoring mails on these topics I'm CCed on. Time to remove myself. I'm still listed as a reviewer for Device Tree, I'll keep this for now, since I do have some interest and it's lower volume. Signed-off-by: David Gibson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- MAINTAINERS | 2 -- 1 file changed, 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 840eebc944..a4ad10226f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1471,7 +1471,6 @@ F: tests/functional/test_ppc_40p.py sPAPR (pseries) M: Nicholas Piggin R: Daniel Henrique Barboza -R: David Gibson R: Harsh Prateek Bora L: qemu-ppc@nongnu.org S: Odd Fixes @@ -1562,7 +1561,6 @@ F: tests/functional/test_ppc_amiga.py Virtual Open Firmware (VOF) M: Alexey Kardashevskiy -R: David Gibson L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/ppc/spapr_vof*