From patchwork Mon Nov 4 06:35:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Su X-Patchwork-Id: 13860950 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5367618D64D for ; Mon, 4 Nov 2024 06:41:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730702518; cv=none; b=XXgM98Lm9iPgofqyBGL3noXUhDIk7IzKFULq9FHigTLX1ZStnaujdaxtnmv4ywNscVXjoRc89vCz5m8jI2/QyABwcFU4vBvb8T12odULSUXWttXaS1RnQvtw8++YYoffFkL3j+/90DOfcXfaLELh+nG00rls6aOKLsSwLN/rLwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730702518; c=relaxed/simple; bh=Gk/pDh5H1hn8kUf1miRAm6KpEDmFIe71Wx1tlq+NTtw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rR54PBwfxliK4shOchrppRM2tK7AMK2WOXI3xxjpCFZKu24V9ciY0qzpY95Kkt3I4gb7ZnSWHAT7Ymk6yqiYgrBXRHHl278/j5GB160d/YFulthh7c11VBoIVK8Z8PwcF42JvSEPYBvN09zXVLycl1zA3+pTZGeKL2vGKIjY/8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YPaOwWbx; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YPaOwWbx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730702518; x=1762238518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gk/pDh5H1hn8kUf1miRAm6KpEDmFIe71Wx1tlq+NTtw=; b=YPaOwWbxCUt+RkQghmXT26a8OxcaIAjv25JCoKi5vhurn4jCyQA4tGTx n6qTlRlOIryXMdeS+PHTZj+SNRyqtYcBS+VQ0uShLegKw4js6f1h6Aivi dUxMXnF3vBfztpuksfH3lqBLGcugXOnY43NXGR0UDOqQTwkcE7FUq/CI+ m6SdGgILqrhdxpgFmJ1Bkz94yiV8j1lK/1ulGWFQ6nOeIifEpMvDxDMkS gRe4N5O8ws70O2ORzmGP9TKgIB1sktFb7ruCHuecYXYNBnmIUAcZa5+cV 4N6hKCyG9AwcLkjF+88+K0ay31XG7holIKguFkc+9zwbQkUV7yRYxgqVW A==; X-CSE-ConnectionGUID: b+dHdAm1QvykoAhhY+ugRQ== X-CSE-MsgGUID: hf6bgEE6QhGTLFAzNNFL1A== X-IronPort-AV: E=McAfee;i="6700,10204,11245"; a="41776703" X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="41776703" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2024 22:41:58 -0800 X-CSE-ConnectionGUID: Gqn+6iRgSimo9hgHqTNwwQ== X-CSE-MsgGUID: vBa3VDV7SiibdDMABX3R+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="83902894" Received: from st-server.bj.intel.com ([10.240.193.102]) by fmviesa010.fm.intel.com with ESMTP; 03 Nov 2024 22:41:54 -0800 From: Tao Su To: kvm@vger.kernel.org, x86@kernel.org Cc: seanjc@google.com, pbonzini@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chao.gao@intel.com, xiaoyao.li@intel.com, jiaan.lu@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 1/4] x86: KVM: Advertise SHA512 CPUID to userspace Date: Mon, 4 Nov 2024 14:35:56 +0800 Message-Id: <20241104063559.727228-2-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241104063559.727228-1-tao1.su@linux.intel.com> References: <20241104063559.727228-1-tao1.su@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SHA512 is a new set of instructions in the latest Intel platform Clearwater Forest, which contains VSHA512MSG1, VSHA512MSG2, VSHA512RNDS2. SHA512 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 0]. SHA512 is on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Considering SHA512 itself has not truly kernel usages, hide this one in /proc/cpuinfo. These instructions only operate in xmm, ymm registers and have no new VMX controls, so there is no additional host enabling required for guests to use these instructions, i.e. advertising SHA512 CPUID to userspace is safe. Tested-by: Jiaan Lu Tested-by: Xuelian Guo Signed-off-by: Tao Su --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 913fd3a7bac6..896794528b81 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -317,6 +317,7 @@ #define X86_FEATURE_ZEN1 (11*32+31) /* CPU based on Zen1 microarchitecture */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ +#define X86_FEATURE_SHA512 (12*32+ 0) /* SHA512 instructions */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 41786b834b16..5c7772567a4e 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -698,7 +698,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | + F(SHA512) | F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | F(AMX_FP16) | F(AVX_IFMA) | F(LAM) ); From patchwork Mon Nov 4 06:35:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Su X-Patchwork-Id: 13860951 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16F4518E029 for ; Mon, 4 Nov 2024 06:42:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730702521; cv=none; b=dUXV7j48TeTP3o5KoT5IoYcGPnCwW3rcUaLC9HSVaXTZw/YOdwroZ63p5s1zbJ1CjIbizSm/tZFYBF4S7JO7SZ/+bGC0PS78VMwcDfN68Tit/zIZBnMfHGeUDygr1LDLM/HJLlxR62K33arqtwrth0RBMrbKHeR1HUi9pDa0w/E= ARC-Message-Signature: i=1; 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d="scan'208";a="83902905" Received: from st-server.bj.intel.com ([10.240.193.102]) by fmviesa010.fm.intel.com with ESMTP; 03 Nov 2024 22:41:57 -0800 From: Tao Su To: kvm@vger.kernel.org, x86@kernel.org Cc: seanjc@google.com, pbonzini@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chao.gao@intel.com, xiaoyao.li@intel.com, jiaan.lu@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 2/4] x86: KVM: Advertise SM3 CPUID to userspace Date: Mon, 4 Nov 2024 14:35:57 +0800 Message-Id: <20241104063559.727228-3-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241104063559.727228-1-tao1.su@linux.intel.com> References: <20241104063559.727228-1-tao1.su@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SM3 is a new set of instructions in the latest Intel platform Clearwater Forest, which contains VSM3MSG1, VSM3MSG2, VSM3RNDS2. SM3 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 1]. SM3 is on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Considering SM3 itself has no truly kernel usages, hide this one in /proc/cpuinfo. These instructions only operate in xmm registers and have no new VMX controls, so there is no additional host enabling required for guests to use these instructions, i.e. advertising SM3 CPUID to userspace is safe. Tested-by: Jiaan Lu Tested-by: Xuelian Guo Signed-off-by: Tao Su --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 896794528b81..460f4f93b039 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -318,6 +318,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_SHA512 (12*32+ 0) /* SHA512 instructions */ +#define X86_FEATURE_SM3 (12*32+ 1) /* SM3 instructions */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 5c7772567a4e..e9f7489ba569 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -698,8 +698,8 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 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d="scan'208";a="83902915" Received: from st-server.bj.intel.com ([10.240.193.102]) by fmviesa010.fm.intel.com with ESMTP; 03 Nov 2024 22:42:00 -0800 From: Tao Su To: kvm@vger.kernel.org, x86@kernel.org Cc: seanjc@google.com, pbonzini@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chao.gao@intel.com, xiaoyao.li@intel.com, jiaan.lu@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 3/4] x86: KVM: Advertise SM4 CPUID to userspace Date: Mon, 4 Nov 2024 14:35:58 +0800 Message-Id: <20241104063559.727228-4-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241104063559.727228-1-tao1.su@linux.intel.com> References: <20241104063559.727228-1-tao1.su@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SM4 is a new set of instructions in the latest Intel platform Clearwater Forest, which contains VSM4KEY4, VSM4RNDS4. SM4 is enumerated via CPUID.(EAX=7,ECX=1):EAX[bit 2]. SM4 is on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Considering SM4 itself has no truly kernel usages, hide this one in /proc/cpuinfo. These instructions only operate in xmm, ymm registers and have no new VMX controls, so there is no additional host enabling required for guests to use these instructions, i.e. advertising SM4 CPUID to userspace is safe. Tested-by: Jiaan Lu Tested-by: Xuelian Guo Signed-off-by: Tao Su --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 460f4f93b039..d96277dceabf 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -319,6 +319,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_SHA512 (12*32+ 0) /* SHA512 instructions */ #define X86_FEATURE_SM3 (12*32+ 1) /* SM3 instructions */ +#define X86_FEATURE_SM4 (12*32+ 2) /* SM4 instructions */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index e9f7489ba569..160b060121b2 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -698,7 +698,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 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d="scan'208";a="83902929" Received: from st-server.bj.intel.com ([10.240.193.102]) by fmviesa010.fm.intel.com with ESMTP; 03 Nov 2024 22:42:03 -0800 From: Tao Su To: kvm@vger.kernel.org, x86@kernel.org Cc: seanjc@google.com, pbonzini@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chao.gao@intel.com, xiaoyao.li@intel.com, jiaan.lu@intel.com, xuelian.guo@intel.com, tao1.su@linux.intel.com Subject: [PATCH 4/4] KVM: x86: Advertise AVX-VNNI-INT16 CPUID to userspace Date: Mon, 4 Nov 2024 14:35:59 +0800 Message-Id: <20241104063559.727228-5-tao1.su@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241104063559.727228-1-tao1.su@linux.intel.com> References: <20241104063559.727228-1-tao1.su@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 AVX-VNNI-INT16 is a new set of instructions in the latest Intel platform Clearwater Forest, which can multiply and add unsigned and signed words with and without saturation. AVX-VNNI-INT16 is enumerated via CPUID.(EAX=7,ECX=1):EDX[bit 10]. Advertise AVX-VNNI-INT16 if it's supported in hardware. There are no new VMX controls for the feature, i.e. the instructions can't be intercepted and only use xmm, ymm registers. Tested-by: Jiaan Lu Tested-by: Xuelian Guo Signed-off-by: Tao Su --- arch/x86/kvm/cpuid.c | 4 ++-- arch/x86/kvm/reverse_cpuid.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 160b060121b2..68cde739a5a3 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -704,8 +704,8 @@ void kvm_set_cpu_caps(void) ); kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, - F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) | - F(AMX_COMPLEX) | F(AVX10) + F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(AMX_COMPLEX) | + F(AVX_VNNI_INT16) | F(PREFETCHITI) | F(AVX10) ); kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 0d17d6b70639..e46220ece83c 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -46,6 +46,7 @@ enum kvm_only_cpuid_leafs { #define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4) #define X86_FEATURE_AVX_NE_CONVERT KVM_X86_FEATURE(CPUID_7_1_EDX, 5) #define X86_FEATURE_AMX_COMPLEX KVM_X86_FEATURE(CPUID_7_1_EDX, 8) +#define X86_FEATURE_AVX_VNNI_INT16 KVM_X86_FEATURE(CPUID_7_1_EDX, 10) #define X86_FEATURE_PREFETCHITI KVM_X86_FEATURE(CPUID_7_1_EDX, 14) #define X86_FEATURE_AVX10 KVM_X86_FEATURE(CPUID_7_1_EDX, 19)