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[2001:b011:7001:120c:5816:f057:fc2f:b780]) by smtp.gmail.com with ESMTPSA id d5sm14784421pfo.83.2019.03.12.06.15.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Mar 2019 06:15:41 -0700 (PDT) Date: Tue, 12 Mar 2019 06:14:57 -0700 Message-Id: <20190312131526.14710-1-palmer@sifive.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PULL] target/riscv: Convert to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-03-11 18:26:37 +0000) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf3 for you to fetch changes up to a971f8ae0e8ab6fab1eee199961b1ea2f4d876f7: target/riscv: Remove decode_RV32_64G() (2019-03-12 03:08:34 -0700) ---------------------------------------------------------------- target/riscv: Convert to decodetree Bastian: this patchset converts the RISC-V decoder to decodetree in four major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-15]: Many of the gen_* functions are called by the decode functions for 16-bit and 32-bit functions. If we move translation code from the gen_* functions to the generated trans_* functions of decode-tree, we get a lot of duplication. Therefore, we mostly generate calls to the old gen_* function which are properly replaced after step 2). Each of the trans_ functions are grouped into files corresponding to their ISA extension, e.g. addi which is in RV32I is translated in the file 'trans_rvi.inc.c'. 2) Convert 16-bit instructions to decodetree [Patch 16-18]: All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus, we convert the arguments in the 16 bit trans_ function to the arguments of the corresponding 32 bit instruction and call the 32 bit trans_ function. 3) Remove old manual decoding in gen_* function [Patch 19-29]: this move all manual translation code into the trans_* instructions of decode tree, such that we can remove the old decode_* functions. Palmer: This, with some additional cleanup patches, passed Alistar's testing on rv32 and rv64 as well as my testing on rv64, so I think it's good to go. I've run my standard test against this exact tag. I haven't tested the OSX build because I didn't find an OSX machine (I'm traveling), but I removed the offending commits so hopefully we're safe. ---------------------------------------------------------------- Bastian Koppelmann (29): target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert RVXM insns to decodetree target/riscv: Convert RV32A insns to decodetree target/riscv: Convert RV64A insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Remove gen_jalr() target/riscv: Remove manual decoding from gen_branch() target/riscv: Remove manual decoding from gen_load() target/riscv: Remove manual decoding from gen_store() target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Remove shift and slt insn manual decoding target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Rename trans_arith to gen_arith target/riscv: Remove gen_system() target/riscv: Remove decode_RV32_64G() target/riscv/Makefile.objs | 19 + target/riscv/insn16.decode | 129 ++ target/riscv/insn32-64.decode | 72 + target/riscv/insn32.decode | 201 +++ target/riscv/insn_trans/trans_privileged.inc.c | 110 ++ target/riscv/insn_trans/trans_rva.inc.c | 218 +++ target/riscv/insn_trans/trans_rvc.inc.c | 327 +++++ target/riscv/insn_trans/trans_rvd.inc.c | 442 ++++++ target/riscv/insn_trans/trans_rvf.inc.c | 439 ++++++ target/riscv/insn_trans/trans_rvi.inc.c | 568 ++++++++ target/riscv/insn_trans/trans_rvm.inc.c | 120 ++ target/riscv/translate.c | 1847 ++++-------------------- 12 files changed, 2897 insertions(+), 1595 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn32-64.decode create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c create mode 100644 target/riscv/insn_trans/trans_rva.inc.c create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c