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AJvYcCWNOmOo/LQduVeCd5d/kwJn7EysHP8eGf3dIk/HEj/zDb0+KIU3n3JtOa2G5Pnj4wqs2llo0vTjhKDgaDf/Lo55@lists.infradead.org X-Gm-Message-State: AOJu0YxwSorqJQEJrmXDXfsJyNyoQ4tgMAPyFI0oGyvlJXrhjo7UCTcI gDvtIpvT/Cj+RAuSlXXayb/ZHuxMQqK6md9rH/VhJ5UsSb+ggrxdK97u8g== X-Google-Smtp-Source: AGHT+IHmPYcPWfZhwOxujigyXrVRSB8kRoNxKABpVBwVCQzAOZBWznyCKjCQL89t1FiTLIwjVZF9zw== X-Received: by 2002:a05:620a:14e:b0:7ac:ae32:286a with SMTP id af79cd13be357-7b193f041d5mr4080201485a.34.1730835141086; Tue, 05 Nov 2024 11:32:21 -0800 (PST) Received: from newman.cs.purdue.edu ([128.10.127.250]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b2f3a9b991sm553343285a.127.2024.11.05.11.32.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2024 11:32:20 -0800 (PST) From: Jiasheng Jiang To: jic23@kernel.org, lars@metafoo.de, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, u.kleine-koenig@baylibre.com, tgamblin@baylibre.com, fabrice.gasnier@st.com, benjamin.gaignard@linaro.org, lee@kernel.org Cc: linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiasheng Jiang Subject: [PATCH] iio: trigger: stm32-timer-trigger: Add check for clk_enable() Date: Tue, 5 Nov 2024 19:32:12 +0000 Message-Id: <20241105193212.2082-1-jiashengjiangcool@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241105_113222_730767_8D930A7A X-CRM114-Status: GOOD ( 14.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add check for the return value of clk_enable() in order to catch the potential exception. Fixes: 3192ade7b6f6 ("iio: trigger: stm32-timer: enable clock when in master mode") Fixes: 90938ca432e6 ("iio: trigger: stm32-timer: add enable attribute") Fixes: 93fbe91b5521 ("iio: Add STM32 timer trigger driver") Signed-off-by: Jiasheng Jiang --- drivers/iio/trigger/stm32-timer-trigger.c | 40 +++++++++++++++++++---- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c index 0684329956d9..0d5bb808c61d 100644 --- a/drivers/iio/trigger/stm32-timer-trigger.c +++ b/drivers/iio/trigger/stm32-timer-trigger.c @@ -119,7 +119,7 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv, unsigned int frequency) { unsigned long long prd, div; - int prescaler = 0; + int prescaler = 0, ret; u32 ccer; /* Period and prescaler values depends of clock rate */ @@ -153,7 +153,13 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv, mutex_lock(&priv->lock); if (!priv->enabled) { priv->enabled = true; - clk_enable(priv->clk); + ret = clk_enable(priv->clk); + if (ret) { + mutex_unlock(&priv->lock); + return dev_err_probe(priv->dev, ret, + "failed to enable clock: %d\n", + ret); + } } regmap_write(priv->regmap, TIM_PSC, prescaler); @@ -307,7 +313,7 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev, struct stm32_timer_trigger *priv = dev_get_drvdata(dev); struct iio_trigger *trig = to_iio_trigger(dev); u32 mask, shift, master_mode_max; - int i; + int i, ret; if (stm32_timer_is_trgo2_name(trig->name)) { mask = TIM_CR2_MMS2; @@ -326,7 +332,13 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev, if (!priv->enabled) { /* Clock should be enabled first */ priv->enabled = true; - clk_enable(priv->clk); + ret = clk_enable(priv->clk); + if (ret) { + mutex_unlock(&priv->lock); + return dev_err_probe(priv->dev, ret, + "failed to enable clock: %d\n", + ret); + } } regmap_update_bits(priv->regmap, TIM_CR2, mask, i << shift); @@ -482,6 +494,7 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev, int val, int val2, long mask) { struct stm32_timer_trigger *priv = iio_priv(indio_dev); + int ret; switch (mask) { case IIO_CHAN_INFO_RAW: @@ -496,7 +509,13 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev, if (val) { if (!priv->enabled) { priv->enabled = true; - clk_enable(priv->clk); + ret = clk_enable(priv->clk); + if (ret) { + mutex_unlock(&priv->lock); + return dev_err_probe(priv->dev, ret, + "failed to enable clock: %d\n", + ret); + } } regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); } else { @@ -601,7 +620,7 @@ static int stm32_set_enable_mode(struct iio_dev *indio_dev, unsigned int mode) { struct stm32_timer_trigger *priv = iio_priv(indio_dev); - int sms = stm32_enable_mode2sms(mode); + int sms = stm32_enable_mode2sms(mode), ret; if (sms < 0) return sms; @@ -611,7 +630,14 @@ static int stm32_set_enable_mode(struct iio_dev *indio_dev, */ mutex_lock(&priv->lock); if (sms == 6 && !priv->enabled) { - clk_enable(priv->clk); + ret = clk_enable(priv->clk); + if (ret) { + mutex_unlock(&priv->lock); + return dev_err_probe(priv->dev, ret, + "failed to enable clock: %d\n", + ret); + } + priv->enabled = true; } mutex_unlock(&priv->lock);