From patchwork Wed Nov 6 16:03:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865143 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7D1A204948; Wed, 6 Nov 2024 16:03:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909043; cv=none; b=Li0pNoPjx+8zR/Zq+AeAD99ba/IfdtdFUFUcXFnf5Ge0rJJXgjF75LUjE7L4rLq5aOIhhBprOEMGwEOQgB30QgFnZbprqB4AyU/YXrtPQIyR5cUBgN6Rztibm3vGwu7qyNEgEmMGy520b4k6QLkHNsTnf5IQDrNPEhKCyv6ZW68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909043; c=relaxed/simple; bh=n0O22ogoVo6OZXgADqeoCHWd9EUR5G2fGF+bLVlYGTA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kxpiIz2oikt9veBGF5cb6CZkfqET8VFJO8csqaU/6E6XjUhUnKPbFQuuy62Y+/Z8mVg/hA/RTf2FW+2N5jMGm7X79ReMfd57sMfYtM6tDzwsB8Q9KYlaimtYPdVQKUMLunE73HWcBo7jEcBbfBfrgHy2vRjnqn/tXMfdT0P01lU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=bqCjkOeO; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bqCjkOeO" Received: by mail.gandi.net (Postfix) with ESMTPSA id D5EEC4000C; Wed, 6 Nov 2024 16:03:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909038; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w0h0STs8I6iL7FEbvTaex0RoYlDDG69yp2h2qtyDFI4=; b=bqCjkOeOTmbg6o34HMblXg+UIczqzp8EpjQc5cA002RhOOccz3hjwm41UNPcf+IbrAZc2+ mT4uALzCzA/zKyO9kY84zmAIsccp+I/1/aCf+HsnRYAlDieEs+Rd9jE9RjlrJKlXOrKo7X Lyl4jGM2LDpc7qaPT1qh8UDQvoF3pAWZZX+qeNm0W29bglpCYZAO5lYUUJDU8rcyTRwcOj /k31gB8zi366G/kb3A21EFe0dXWg1AOnXlp5BMu8UNxNJyaiv+UTB63UWdyMkx50pvnYv8 NReSAsPLN5oBIK+FNDXP8y7clAelYbuLiLFQSd6U83D1rYPmo3xSAQmj1ccNdw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:52 +0100 Subject: [PATCH v2 01/10] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-1-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Some compatibles expose a single clock. For those, we used to let them using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>). Switch away from that: enforce a cell for all compatibles. This is more straight forward, and avoids devicetree changes whenever a compatible goes from exposing a single clock to multiple ones. Also, dt-bindings get simpler. *This is an ABI break*. Change it while EyeQ5 platform support is at its infancy, without any user. More clocks might hide in each OLB as some registers are still unknown. Signed-off-by: Théo Lebrun Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) --- .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 24 +--------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml index f7e606d45ebcfc46ffe076e23a2ed514bfff9b8f..6d11472ba5a704d5d20f43776e5867f507a39242 100644 --- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -41,9 +41,7 @@ properties: enum: [ 1, 2 ] '#clock-cells': - description: - Cell is clock index. Optional if compatible has a single clock. - enum: [ 0, 1 ] + const: 1 clocks: maxItems: 1 @@ -312,26 +310,6 @@ allOf: properties: '#reset-cells': false - # Compatibles exposing a single clock. - - if: - properties: - compatible: - contains: - enum: - - mobileye,eyeq6h-central-olb - - mobileye,eyeq6h-east-olb - - mobileye,eyeq6h-west-olb - - mobileye,eyeq6h-ddr0-olb - - mobileye,eyeq6h-ddr1-olb - then: - properties: - '#clock-cells': - const: 0 - else: - properties: - '#clock-cells': - const: 1 - # Only EyeQ5 has pinctrl in OLB. - if: not: From patchwork Wed Nov 6 16:03:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865144 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DAE820495E; Wed, 6 Nov 2024 16:04:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909043; cv=none; b=U650FIAPWvS+Xq7u5iGSEHzc9k13caTab7crtJtEvUg4pOx4BAmDa1lGDhR3CvDKglapjus+tFraUdWr5Pn9pKLZUq6XKQIbVDIh3b9BM7j8hBCyM0LQ29UvqJeORtE94OmVUiE+knmVKsaT95IBccuDOKXvhYEE3pjPiWQ2mHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909043; c=relaxed/simple; bh=3woLQ1O5xn3KQhSqABRWdyezQL0RB3AHSxjAVr1Kar4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QQ/r8OfCKXKixvgeBFurEik95jm3neNcBxqjgSNv3ppJjE1KXQOO+C3F7c+6L5puB0VuSl7gnPfFu+/RTqG++bnyAIwrk39c2hq+ODBOOpEOYEXDE1iSUSP+Vo83+qiKlTwRsAA5LNrdeVcXAX9QXZOLtGTPa8qzWYuGvr49DPU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BZ67JaIl; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BZ67JaIl" Received: by mail.gandi.net (Postfix) with ESMTPSA id 7F76E4000E; Wed, 6 Nov 2024 16:03:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909039; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XbSQpx6+P5te4JBOfJJ+Yvd01YB99e7I0NZ06uZJ9QI=; b=BZ67JaIlG3gOsJQ7UFS/LgdHQFisOepCXrAJKo38yPsnFzJOevKPFiFrleYEoczlhp6i8O iAgJFB/+1H4g7kU5Iqx4TjqXf0tpr3YBBxpULQVzc4v+73Q5kLbhjmu/EqV/fjsJVQRh+6 /mujgXGxPJ9grQ8xnVvk26i+gSiCDW5x1z2IW3x0JTCIv9Xwt7JYUrpSo0OWeFdz7D8PqA r/0zjQkaxTA3ALSEDswlBDNkR1LMsFFQAYnB4IwkMAqUwpvM470cjcABC0mlCUU8MnmBXO IP2cbEwF3InywmQriZokF9o35byOxMpDKtiXa9QyWr1KumO7YlOnGRV842cNWw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:53 +0100 Subject: [PATCH v2 02/10] dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-2-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add #defines for Mobileye clock controller: - EyeQ5 core 0 thru 3 clocks. Internally: EQ5C_PLL_CPU: already exposed └── EQ5C_CPU_OCC: unexposed, no reason to do so ├── EQ5C_CPU_CORE0: new! ├── EQ5C_CPU_CORE1: new! ├── EQ5C_CPU_CORE2: new! └── EQ5C_CPU_CORE3: new! - EyeQ5 peripheral clocks. Internally: EQ5C_PLL_PER: already exposed ├── EQ5C_PER_OCC: new! │ ├── EQ5C_PER_SPI: new! │ ├── EQ5C_PER_I2C: new! │ ├── EQ5C_PER_GPIO: new! │ └── EQ5C_PER_UART: new! ├── EQ5C_PER_EMMC: new! └── EQ5C_PER_OCC_PCI: new! - EyeQ6H central OLB. Internally: EQ6HC_CENTRAL_PLL_CPU: new! └── EQ6HC_CENTRAL_CPU_OCC: new! - EyeQ6H west OLB. Internally: EQ6HC_WEST_PLL_PER: new! └── EQ6HC_WEST_PER_OCC: new! └── EQ6HC_WEST_PER_UART: new! Signed-off-by: Théo Lebrun Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/mobileye,eyeq5-clk.h | 44 +++++++++++++++++++------- 1 file changed, 33 insertions(+), 11 deletions(-) diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h index b433c1772c28fae818b3a6ba428d1f89000f9206..f353c2988035f7c9fb84e4b59c6c4a220436454b 100644 --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -6,24 +6,46 @@ #ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H #define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H -#define EQ5C_PLL_CPU 0 -#define EQ5C_PLL_VMP 1 -#define EQ5C_PLL_PMA 2 -#define EQ5C_PLL_VDI 3 -#define EQ5C_PLL_DDR0 4 -#define EQ5C_PLL_PCI 5 -#define EQ5C_PLL_PER 6 -#define EQ5C_PLL_PMAC 7 -#define EQ5C_PLL_MPC 8 -#define EQ5C_PLL_DDR1 9 +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 -#define EQ5C_DIV_OSPI 10 +#define EQ5C_DIV_OSPI 10 + +/* EQ5C_PLL_CPU children */ +#define EQ5C_CPU_CORE0 11 +#define EQ5C_CPU_CORE1 12 +#define EQ5C_CPU_CORE2 13 +#define EQ5C_CPU_CORE3 14 + +/* EQ5C_PLL_PER children */ +#define EQ5C_PER_OCC 15 +#define EQ5C_PER_UART 16 +#define EQ5C_PER_SPI 17 +#define EQ5C_PER_I2C 18 +#define EQ5C_PER_GPIO 19 +#define EQ5C_PER_EMMC 20 +#define EQ5C_PER_OCC_PCI 21 #define EQ6LC_PLL_DDR 0 #define EQ6LC_PLL_CPU 1 #define EQ6LC_PLL_PER 2 #define EQ6LC_PLL_VDI 3 +#define EQ6HC_CENTRAL_PLL_CPU 0 +#define EQ6HC_CENTRAL_CPU_OCC 1 + +#define EQ6HC_WEST_PLL_PER 0 +#define EQ6HC_WEST_PER_OCC 1 +#define EQ6HC_WEST_PER_UART 2 + #define EQ6HC_SOUTH_PLL_VDI 0 #define EQ6HC_SOUTH_PLL_PCIE 1 #define EQ6HC_SOUTH_PLL_PER 2 From patchwork Wed Nov 6 16:03:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865145 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67FDD1DE8BA; Wed, 6 Nov 2024 16:04:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909044; cv=none; b=UM7BJgi3IpdGpRjLj7xDHVqMcq0GADDuV3031pKtE3rtG6V1RnPZTJjYO0JigGrupNNiYzT+bNMCIU68vrTVKHXwErsWoffBq5q8WyBj6xnx4G14D53rSYsbkjeMXtueDc9hu562V3qA9uGoQiqJqGxgQ8ZOc42ozKxOlrSlim8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909044; c=relaxed/simple; bh=IbL1dIsMDKSWk+juOOze/+/g65R93/+X2wY8wHACvmo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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bh=8kmyA2fOJCwI24a+4je8+bVYsLftxYiEpbBDgDU16Vo=; b=G/ir37kBGTvaZGJ0gPqyaKBMyktO21l8P6dLhFieA6QHGnl/fZtG//NjAvaoR0E+gGE4iL 08fIRSHfXl/0On86fLQtClQWAc+aKQuF3kE4mmSZG7kpZVqsf4Pe9Y+OXJxuuh4KOlwI+d NoimqrOqheX91I26Rh3RkHPgIl8yo/z2RsFyEDx3cYtiV0BpOONIz6IMubDkpFoZMb+pz2 ZyPLtmdfpbRnP2BLN/M+Faj1dJleZPCN7SGDCV5rKUuFPAQ2WSlsfmtz+87niLp3QkYZXs 3OSeKoY9hBrJtNFYDVZ4KJgX7xcZZ5Shr4T+W5pYUr2HGwmEXvEn0IV+01B6TA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:54 +0100 Subject: [PATCH v2 03/10] clk: fixed-factor: add clk_hw_register_fixed_factor_index() function Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-3-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Add non-devres version of clk_hw_register_fixed_factor(), with parent targeted using its index. Signed-off-by: Théo Lebrun --- drivers/clk/clk-fixed-factor.c | 11 +++++++++++ include/linux/clk-provider.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 8fba63fc70c554df0d646dba75c5d70d0b184319..e62ae8794d445f685156276d5135448f340fca3f 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -241,6 +241,17 @@ struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device * } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy_fwname); +struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev, + const char *name, unsigned int index, unsigned long flags, + unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, + flags, mult, div, 0, 0, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_index); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 75444e250a7875a4fa90c9dea7a90b198f6be2b8..99ae3ffb94bc5ce2b8493509cf3548b03209852b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1142,6 +1142,9 @@ struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device * struct device_node *np, const char *name, const char *fw_name, unsigned long flags, unsigned int mult, unsigned int div, unsigned long acc); +struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev, + const char *name, unsigned int index, unsigned long flags, + unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, From patchwork Wed Nov 6 16:03:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865146 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD0E8204F72; Wed, 6 Nov 2024 16:04:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fqGJ54zq" Received: by mail.gandi.net (Postfix) with ESMTPSA id D0F0940010; Wed, 6 Nov 2024 16:03:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909040; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iKhRzgiEUNdm1NA9uvOtWIMNNDJizhjx+IFpddS8/Og=; b=fqGJ54zqt6XDdIMCkXo2K03xHAkiBbCCrJReJSOOfo8bnJBQspYmxlf7fPvJiDb365ugan wcHOyDHBh26onDKBkC1oKEzE4hlV9S2QGJqCczn0ajg53EKvwLy0Yt2bvYHsdJJ3W1TyjC z5YfCnPdTxadFPK21sh1sq1EUo86VjA+bx1LsdmV9Zr26eFSquJCEeaxvfQeHIHv0F9kI0 j2n5HSSzbkXk+0dIYXpfbmu1GVcjXpOTffVGPmngou4AO7wS9JKfbV54zei+Kpwoy66Nu/ GpJYnWdQ8bYlz0yxatfiENUkoopE8fE7AukUbNbX7pvqH164zUGNwLqkI1UVnA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:55 +0100 Subject: [PATCH v2 04/10] clk: eyeq: require clock index with phandle in all cases Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-4-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com We used to let compatibles with a single clock exposed to not have a cell. Switch away from that and enforce a cell in all cases. This is done at the same time as some compatibles (mobileye,eyeq6h-{central,west}-olb) go from one to more clocks exposed. Let's do the same switch and avoid future devicetree work if/when others follow. Signed-off-by: Théo Lebrun --- drivers/clk/clk-eyeq.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 77f1afb020a0247b9d73b59a88845b21a0d83b5e..ed4dab303d9121cd8bf453448b4c86547ea9244c 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -367,11 +367,7 @@ static int eqc_probe(struct platform_device *pdev) eqc_probe_init_divs(dev, data, base, cells); - /* When providing a single clock, require no cell. */ - if (clk_count == 1) - return of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]); - else - return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); } /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */ @@ -637,11 +633,7 @@ static void __init eqc_early_init(struct device_node *np, } } - /* When providing a single clock, require no cell. */ - if (clk_count == 1) - ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]); - else - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); if (ret) { pr_err("failed registering clk provider: %d\n", ret); goto err; From patchwork Wed Nov 6 16:03:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865147 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95090204F77; Wed, 6 Nov 2024 16:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909045; cv=none; b=aQ4jfXeITewrs8kMJw118CT+T71QLLitSbD/AYtSLUTDBMF+exPx1mIShqlAh1/sU9BJb6MDBgCVxPLFyzJPVUqttS0zLRxYpv7XQY6VQGRy15R4L6hCBLf5mFbg73s+YVQTgHKTLAW+0Dmuj98HoDVm9A9lZXdUuCC31LNa8rM= ARC-Message-Signature: i=1; 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Wed, 6 Nov 2024 16:04:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909041; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YjHb8NB7PP/2BMRmRJKo9PzhOnlLh14fP0V1UcwxxaA=; b=Wl0lm+/VBwFJUpWkaL+x0DsutLyrxzbhunoGJVtvBWsvC4DlUG6IdBxeRUwQOdh9lnrynd isYzjr2aTEzOymOOVyimFIbkQu4cuG3qBIJyPktDr2021VlLuzx+getSWGhD+RttDnD2nl IRrWS1AOSeRHyJJDu+CIdx512CQNS4NWXj2h4wcZfYqxHO8txnMGuusRk/SClRTPJf60I5 YdsaLqleBzXztG5VHrUIEZQTyWVF4uzg/oQlPWUcbkWp+TbT9GJQXAQiNabx4sxhZd2n3F 8hw9JqvhycNESMd9U34DfDr4lfs8YJwG2aE49eu0eTYlVWHsXt1tViBCRpITOw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:56 +0100 Subject: [PATCH v2 05/10] clk: eyeq: add fixed factor clocks infrastructure Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-5-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Driver can currently host two types of clocks: - PLLs derived directly from the main crystal (taken using a fwhandle). - Divider clocks derived from those PLLs. PLLs can be instantiated from of_clk_init() or platform device probe, using two separate clock providers. Divider clocks are all instantiated at platform device probe. Add a third type of clocks: fixed factors. Those can be instantiated at both stages. They can be parented to any clock from the driver. Early match data and match data store the list of fixed factor clocks. Signed-off-by: Théo Lebrun --- drivers/clk/clk-eyeq.c | 81 +++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 73 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index ed4dab303d9121cd8bf453448b4c86547ea9244c..85beec6b5b46f2d3485042bf1aa3e395a29f84b1 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -2,11 +2,14 @@ /* * PLL clock driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms. * - * This controller handles read-only PLLs, all derived from the same main - * crystal clock. It also exposes divider clocks, those are children to PLLs. - * Parent clock is expected to be constant. This driver's registers live in - * a shared region called OLB. Some PLLs are initialised early by of_clk_init(); - * if so, two clk providers are registered. + * This controller handles: + * - Read-only PLLs, all derived from the same main crystal clock. + * - It also exposes divider clocks, those are children to PLLs. + * - Fixed factor clocks, children to PLLs. + * + * Parent clock is expected to be constant. This driver's registers live in a + * shared region called OLB. Some PLLs and fixed-factors are initialised early + * by of_clk_init(); if so, two clk providers are registered. * * We use eqc_ as prefix, as-in "EyeQ Clock", but way shorter. * @@ -86,6 +89,14 @@ struct eqc_div { u8 width; }; +struct eqc_fixed_factor { + unsigned int index; + const char *name; + unsigned int mult; + unsigned int div; + unsigned int parent; +}; + struct eqc_match_data { unsigned int pll_count; const struct eqc_pll *plls; @@ -93,6 +104,9 @@ struct eqc_match_data { unsigned int div_count; const struct eqc_div *divs; + unsigned int fixed_factor_count; + const struct eqc_fixed_factor *fixed_factors; + const char *reset_auxdev_name; const char *pinctrl_auxdev_name; @@ -103,6 +117,9 @@ struct eqc_early_match_data { unsigned int early_pll_count; const struct eqc_pll *early_plls; + unsigned int early_fixed_factor_count; + const struct eqc_fixed_factor *early_fixed_factors; + /* * We want our of_xlate callback to EPROBE_DEFER instead of dev_err() * and EINVAL. For that, we must know the total clock count. @@ -276,6 +293,35 @@ static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data } } +static void eqc_probe_init_fixed_factors(struct device *dev, + const struct eqc_match_data *data, + struct clk_hw_onecell_data *cells) +{ + const struct eqc_fixed_factor *ff; + struct clk_hw *hw, *parent_hw; + unsigned int i; + + for (i = 0; i < data->fixed_factor_count; i++) { + ff = &data->fixed_factors[i]; + parent_hw = cells->hws[ff->parent]; + + if (IS_ERR(parent_hw)) { + /* Parent is in early clk provider. */ + hw = clk_hw_register_fixed_factor_index(dev, ff->name, + ff->parent, 0, ff->mult, ff->div); + } else { + /* Avoid clock lookup when we already have the hw reference. */ + hw = clk_hw_register_fixed_factor_parent_hw(dev, ff->name, + parent_hw, 0, ff->mult, ff->div); + } + + cells->hws[ff->index] = hw; + if (IS_ERR(hw)) + dev_warn(dev, "failed registering %s: %pe\n", + ff->name, hw); + } +} + static void eqc_auxdev_release(struct device *dev) { struct auxiliary_device *adev = to_auxiliary_dev(dev); @@ -349,10 +395,11 @@ static int eqc_probe(struct platform_device *pdev) KBUILD_MODNAME, data->pinctrl_auxdev_name, ret); } - if (data->pll_count + data->div_count == 0) + if (data->pll_count + data->div_count + data->fixed_factor_count == 0) return 0; /* Zero clocks, we are done. */ - clk_count = data->pll_count + data->div_count + data->early_clk_count; + clk_count = data->pll_count + data->div_count + + data->fixed_factor_count + data->early_clk_count; cells = kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL); if (!cells) return -ENOMEM; @@ -367,6 +414,8 @@ static int eqc_probe(struct platform_device *pdev) eqc_probe_init_divs(dev, data, base, cells); + eqc_probe_init_fixed_factors(dev, data, cells); + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); } @@ -580,7 +629,8 @@ static void __init eqc_early_init(struct device_node *np, void __iomem *base; int ret; - clk_count = early_data->early_pll_count + early_data->late_clk_count; + clk_count = early_data->early_pll_count + early_data->early_fixed_factor_count + + early_data->late_clk_count; cells = kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL); if (!cells) { ret = -ENOMEM; @@ -633,6 +683,21 @@ static void __init eqc_early_init(struct device_node *np, } } + for (i = 0; i < early_data->early_fixed_factor_count; i++) { + const struct eqc_fixed_factor *ff = &early_data->early_fixed_factors[i]; + struct clk_hw *parent_hw = cells->hws[ff->parent]; + struct clk_hw *hw; + + hw = clk_hw_register_fixed_factor_parent_hw(NULL, ff->name, + parent_hw, 0, ff->mult, ff->div); + cells->hws[ff->index] = hw; + if (IS_ERR(hw)) { + pr_err("failed registering %s: %pe\n", ff->name, hw); + ret = PTR_ERR(hw); + goto err; + } + } + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells); if (ret) { pr_err("failed registering clk provider: %d\n", ret); From patchwork Wed Nov 6 16:03:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865148 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A58A20697C; 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arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bFNf7IoA" Received: by mail.gandi.net (Postfix) with ESMTPSA id 1AB1340014; Wed, 6 Nov 2024 16:04:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909041; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5T4Fcf8pDe/s97a+8Luzm6fLDVba2rh+YE341LO5Rh8=; b=bFNf7IoAG9Faeos4HL8Ix7tzbq61ap2OqpU2vgHb6yTozkeIH+RZ654vzrSBi7Gw8rUOYb yS5Ub6PAAoRGWYY6lYm4eSJdTOHI5y4QG4iyXYTmAk4vZfgX+VtZkuh1/IduJdIpLWfpd2 Wob6mcVom6eHKk9SQb1W1dPnIU313I5zsmE5N/L7f2mMXhlPLT6r1CjPct5ubOUtSqyuhl xEqhgqK/gEvCivMsxqUP0KV+D0g1ODaJdG1D3Ys11DctiokHyhAGIaJu5KhOQeYkLcddKZ SUUCnnrO7MOUvgdIwt2lX5hs+O6fDO9MozwQp6yVMZ+rQHlobzUQksGDNQF2sg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:57 +0100 Subject: [PATCH v2 06/10] clk: eyeq: add EyeQ5 fixed factor clocks Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-6-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Expose additional clocks on EyeQ5. Some indexes come from dt-bindings headers, others are private to the driver. Few clocks are early (of_clk_init() stage: core clocks and UART clock), others can wait until platform device probe. The source for this list is downstream Mobileye kernel and some internal documentation. Signed-off-by: Théo Lebrun --- drivers/clk/clk-eyeq.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 85beec6b5b46f2d3485042bf1aa3e395a29f84b1..542909085bcedb0f6b5b3cffbdb5761da9981cbc 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -436,6 +436,90 @@ static const struct eqc_pll eqc_eyeq5_plls[] = { { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg64 = 0x074 }, }; +enum { + /* + * EQ5C_PLL_CPU children. + * EQ5C_PER_OCC_PCI is the last clock exposed in dt-bindings. + */ + EQ5C_CPU_OCC = EQ5C_PER_OCC_PCI + 1, + EQ5C_CPU_SI_CSS0, + EQ5C_CPU_CPC, + EQ5C_CPU_CM, + EQ5C_CPU_MEM, + EQ5C_CPU_OCC_ISRAM, + EQ5C_CPU_ISRAM, + EQ5C_CPU_OCC_DBU, + EQ5C_CPU_SI_DBU_TP, + + /* + * EQ5C_PLL_VDI children. + */ + EQ5C_VDI_OCC_VDI, + EQ5C_VDI_VDI, + EQ5C_VDI_OCC_CAN_SER, + EQ5C_VDI_CAN_SER, + EQ5C_VDI_I2C_SER, + + /* + * EQ5C_PLL_PER children. + */ + EQ5C_PER_PERIPH, + EQ5C_PER_CAN, + EQ5C_PER_TIMER, + EQ5C_PER_CCF, + EQ5C_PER_OCC_MJPEG, + EQ5C_PER_HSM, + EQ5C_PER_MJPEG, + EQ5C_PER_FCMU_A, +}; + +static const struct eqc_fixed_factor eqc_eyeq5_early_fixed_factors[] = { + /* EQ5C_PLL_CPU children */ + { EQ5C_CPU_OCC, "occ-cpu", 1, 1, EQ5C_PLL_CPU }, + { EQ5C_CPU_SI_CSS0, "si-css0", 1, 1, EQ5C_CPU_OCC }, + { EQ5C_CPU_CORE0, "core0", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CORE1, "core1", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CORE2, "core2", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CORE3, "core3", 1, 1, EQ5C_CPU_SI_CSS0 }, + + /* EQ5C_PLL_PER children */ + { EQ5C_PER_OCC, "occ-periph", 1, 16, EQ5C_PLL_PER }, + { EQ5C_PER_UART, "uart", 1, 1, EQ5C_PER_OCC }, +}; + +static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] = { + /* EQ5C_PLL_CPU children */ + { EQ5C_CPU_CPC, "cpc", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_CM, "cm", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_MEM, "mem", 1, 1, EQ5C_CPU_SI_CSS0 }, + { EQ5C_CPU_OCC_ISRAM, "occ-isram", 1, 2, EQ5C_PLL_CPU }, + { EQ5C_CPU_ISRAM, "isram", 1, 1, EQ5C_CPU_OCC_ISRAM }, + { EQ5C_CPU_OCC_DBU, "occ-dbu", 1, 10, EQ5C_PLL_CPU }, + { EQ5C_CPU_SI_DBU_TP, "si-dbu-tp", 1, 1, EQ5C_CPU_OCC_DBU }, + + /* EQ5C_PLL_VDI children */ + { EQ5C_VDI_OCC_VDI, "occ-vdi", 1, 2, EQ5C_PLL_VDI }, + { EQ5C_VDI_VDI, "vdi", 1, 1, EQ5C_VDI_OCC_VDI }, + { EQ5C_VDI_OCC_CAN_SER, "occ-can-ser", 1, 16, EQ5C_PLL_VDI }, + { EQ5C_VDI_CAN_SER, "can-ser", 1, 1, EQ5C_VDI_OCC_CAN_SER }, + { EQ5C_VDI_I2C_SER, "i2c-ser", 1, 20, EQ5C_PLL_VDI }, + + /* EQ5C_PLL_PER children */ + { EQ5C_PER_PERIPH, "periph", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_CAN, "can", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_SPI, "spi", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_I2C, "i2c", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_TIMER, "timer", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_GPIO, "gpio", 1, 1, EQ5C_PER_OCC }, + { EQ5C_PER_EMMC, "emmc-sys", 1, 10, EQ5C_PLL_PER }, + { EQ5C_PER_CCF, "ccf-ctrl", 1, 4, EQ5C_PLL_PER }, + { EQ5C_PER_OCC_MJPEG, "occ-mjpeg", 1, 2, EQ5C_PLL_PER }, + { EQ5C_PER_HSM, "hsm", 1, 1, EQ5C_PER_OCC_MJPEG }, + { EQ5C_PER_MJPEG, "mjpeg", 1, 1, EQ5C_PER_OCC_MJPEG }, + { EQ5C_PER_FCMU_A, "fcmu-a", 1, 20, EQ5C_PLL_PER }, + { EQ5C_PER_OCC_PCI, "occ-pci-sys", 1, 8, EQ5C_PLL_PER }, +}; + static const struct eqc_div eqc_eyeq5_divs[] = { { .index = EQ5C_DIV_OSPI, @@ -451,7 +535,11 @@ static const struct eqc_early_match_data eqc_eyeq5_early_match_data __initconst .early_pll_count = ARRAY_SIZE(eqc_eyeq5_early_plls), .early_plls = eqc_eyeq5_early_plls, - .late_clk_count = ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs), + .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq5_early_fixed_factors), + .early_fixed_factors = eqc_eyeq5_early_fixed_factors, + + .late_clk_count = ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs) + + ARRAY_SIZE(eqc_eyeq5_fixed_factors), }; static const struct eqc_match_data eqc_eyeq5_match_data = { @@ -461,10 +549,14 @@ static const struct eqc_match_data eqc_eyeq5_match_data = { .div_count = ARRAY_SIZE(eqc_eyeq5_divs), .divs = eqc_eyeq5_divs, + .fixed_factor_count = ARRAY_SIZE(eqc_eyeq5_fixed_factors), + .fixed_factors = eqc_eyeq5_fixed_factors, + .reset_auxdev_name = "reset", .pinctrl_auxdev_name = "pinctrl", - .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls), + .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls) + + ARRAY_SIZE(eqc_eyeq5_early_fixed_factors), }; static const struct eqc_pll eqc_eyeq6l_plls[] = { From patchwork Wed Nov 6 16:03:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865149 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8D95206E92; Wed, 6 Nov 2024 16:04:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909047; cv=none; b=s64RDX9kWWQXJia+gYEfA6shxr6oFlXpSeLlegBScoHXqH5+02esp3Wcv8gtkUPPKjLJ1VToR8BEVCnLGmRibsYBezov0h8Kcv9FChevgEFiFsMoXaQ5HFSHyGnOsUK98OT1oqsK5Iz/S4gQS4OWoaKmnvu2zu8XJvyhfxBSmJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909047; c=relaxed/simple; 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a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909042; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XazLFxEo9IWiQOl5eAorhjqPNi1XrTqdIgPa4icG4b0=; b=VTn2Q+ivLAXpz5OACWcRFgmERlNW/tu81gQ30zXrOdMFeNUjDZUGIfW645IWG8glSgYF9d /7cIKJbAeadmacBJ1gGR19yqimGARIZmGkTUX4K85lKTE9xzUcCocCVG7jLggY1N+NBtXE OibL6Tk6sPWy/pILZJYEbHe7qRFZdbXHObY5pf+9TrOnkAIKeC/BJqo7ga7b8g0Cf/RjDF +T2gXP7dROqIAt/4gqH2hqhPQySSdroG7G3a5Z/wrwzbaodBnW+Fxhm2ehVxon2zBmzX6/ COc9lo6k7Rv8Rx/GdmxDuGyk17PD6wsfJ2TIOgN4epZfvD+YRUiF8J+yJSPqbg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:58 +0100 Subject: [PATCH v2 07/10] clk: eyeq: add EyeQ6H central fixed factor clocks Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-7-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Previous setup was: - pll-cpu clock registered from driver at of_clk_init(); - occ-cpu clock registered from DT using fixed-factor-clock compatible. Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use that capability to register occ-cpu. Also switch from hard-coded index 0 for pll-cpu to using the EQ6HC_CENTRAL_PLL_CPU constant by exposed dt-bindings headers. occ-cpu is exposed at of_clk_init() because it gets used by both the DT CPU nodes and the GIC timer. Signed-off-by: Théo Lebrun --- drivers/clk/clk-eyeq.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 542909085bcedb0f6b5b3cffbdb5761da9981cbc..a042e9735b68f85c1ad79ec963b0268410b87ad4 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -695,12 +695,19 @@ builtin_platform_driver(eqc_driver); /* Required early for GIC timer. */ static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = { - { .index = 0, .name = "pll-cpu", .reg64 = 0x02C }, + { .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C }, +}; + +static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = { + { EQ6HC_CENTRAL_CPU_OCC, "occ-cpu", 1, 1, EQ6HC_CENTRAL_PLL_CPU }, }; static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __initconst = { .early_pll_count = ARRAY_SIZE(eqc_eyeq6h_central_early_plls), .early_plls = eqc_eyeq6h_central_early_plls, + + .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_central_early_fixed_factors), + .early_fixed_factors = eqc_eyeq6h_central_early_fixed_factors, }; /* Required early for UART. */ From patchwork Wed Nov 6 16:03:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865150 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A304207A3D; Wed, 6 Nov 2024 16:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909047; cv=none; b=uQKqbEVuWLIT7nlLpr2Ds9gjK9ZuZEP3cVg0w/Lev82htaReSqSI9P8Q9Gtb6/ZzUyJ82IRWGzDtEGjTKOU5YWj2/QLTNS3vjAhQTv8s5rjPgbFv7NfY9YvbgnGEuJDP9Uc7K+ASSRbQqCaGj5HpIFgBC//C05yE911TOm0DLak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909047; c=relaxed/simple; bh=nyUodiUE5Z3VtI1jwRsUMURI24XLiUYhr19zHvPlfFY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KJ2fMwldmE9eOUIDjMrcMuwIAJzjX3utYuW6uaGXNLqY3OuMYfqZ43CNuTBzgh6jivINNJ4TXE0zAyJ+NfpboAgdL99io+lNUESUlgu6Fkf51sxbO464HosUwCIWbOXwqs8Sq8T8WW/aicoFI4A7CUZaIiu2xK1gJo98YvbK0KI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=WFEVXRYR; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="WFEVXRYR" Received: by mail.gandi.net (Postfix) with ESMTPSA id 4C0224000A; Wed, 6 Nov 2024 16:04:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909042; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=T7FqLocYcFog0SorrKtPjnpXfi49tIFlcAwi+Odxh3g=; b=WFEVXRYR6DSw5pMBPJcTDVEZSAHF11ffiELMiMoTwIo1dK0lT+PQ2I+rOg8feaqdr6UfSy 8XDqZNezlrX4VDZejHrGZxK7MQ/NTKkfbCQyOqKAP047nJtmAcFr0iedNYIyEbeKHbW5Z1 nNrrVYNSxIB+t1kryBi94w/6GykOEcJWULhfQLt0Qtw2NeSxZawg9hkBUcFpwVPhMVNvl9 X3OBY1YI+nUPij6iu2WmGX5vqpmR/470++XHsxmCYZsPqQj4XBSybnivBfjBarG2h5vmoD 3c+AvSnIL1SbsIcQO2As+rDYHv8A1dDwYOOz59pAIpxhZmAayt2lag4VlDjSZw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:03:59 +0100 Subject: [PATCH v2 08/10] clk: eyeq: add EyeQ6H west fixed factor clocks Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-8-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Previous setup was: - pll-west clock registered from driver at of_clk_init(); - Both OCC and UART clocks registered from DT using fixed-factor-clock compatible. Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use that capability to register west-per-occ and west-per-uart (giving them proper names at the same time). Also switch from hard-coded index 0 for pll-west to using the EQ6HC_WEST_PLL_PER constant by exposed dt-bindings headers. All get exposed at of_clk_init() because they get used by the AMBA PL011 serial ports. Those are instantiated before platform bus infrastructure. Signed-off-by: Théo Lebrun --- drivers/clk/clk-eyeq.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index a042e9735b68f85c1ad79ec963b0268410b87ad4..640c25788487f8cf6fb4431ed6fb612cf099f114 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -712,12 +712,20 @@ static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __i /* Required early for UART. */ static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = { - { .index = 0, .name = "pll-west", .reg64 = 0x074 }, + { .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg64 = 0x074 }, +}; + +static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = { + { EQ6HC_WEST_PER_OCC, "west-per-occ", 1, 10, EQ6HC_WEST_PLL_PER }, + { EQ6HC_WEST_PER_UART, "west-per-uart", 1, 1, EQ6HC_WEST_PER_OCC }, }; static const struct eqc_early_match_data eqc_eyeq6h_west_early_match_data __initconst = { .early_pll_count = ARRAY_SIZE(eqc_eyeq6h_west_early_plls), .early_plls = eqc_eyeq6h_west_early_plls, + + .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_west_early_fixed_factors), + .early_fixed_factors = eqc_eyeq6h_west_early_fixed_factors, }; static void __init eqc_early_init(struct device_node *np, From patchwork Wed Nov 6 16:04:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13865151 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38D5D20823C; Wed, 6 Nov 2024 16:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909048; cv=none; b=JzpgZy3SlYum0OQW99clyBQ+cLSv6CdcxxEYOm3mfCyFjNVRIPiQXMY7TaGoFzS3gtgp3eD7qvg4cbZ76AtgJNHrBxnN/Nsva75pc6hXC5xChqFxX1JxMRsV7mz/Tueal0eL8V590nRMtnHR7G390aovaOLi30GJxAxaKnZ/67E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730909048; 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Wed, 6 Nov 2024 16:04:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909043; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vBvALQBz6nzlJoEhBr0vnmX8yOjbMQW6G7cmJmWOtDo=; b=WjQduhOpP2qgKp7NnvyQZ0Fc9UeB/YqzChY9QhIHMAfoteJe/ZV1ZddCVx77DbHnIia2GX 2zbpPNjWcQP3KCY1AN6h1Hd/4fn120s7LQXzDwZRtKSssFVnpVFR4i8/owv1IRo4yv5bu8 eEmtdEa/WNeT9joKqbjesEXMZbTa78doVrLZSrb5J2xmUL8UHhPzsmCGkl3lvq+gCR5ORh /C7btTVfFb3XYPNBhNvohsHmkrJNJUvEkU1GcuACSnCVNZIyILenHEKKaX0GYBIEIi9w8V V4gMPEbKXrCRGbb6Grxag4Zn1vyohT+u4DnB4BZMrxqszdzI/MvV2clMD/go0A== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:04:00 +0100 Subject: [PATCH v2 09/10] MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-9-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Change the structure of the clock tree: rather than individual devicetree nodes registering each fixed factor clock derived from OLB PLLs, have the OLB node provide the necessary clocks. Remove eyeq5-clocks.dtsi and move the three remaining "fixed-clock"s to the main eyeq5.dtsi file. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi | 270 -------------------------- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 30 ++- 2 files changed, 24 insertions(+), 276 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi deleted file mode 100644 index 17a342cc744e57dc1f21262abdbfa97d4e4d58f3..0000000000000000000000000000000000000000 --- a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright 2023 Mobileye Vision Technologies Ltd. - */ - -#include - -/ { - /* Fixed clock */ - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - }; - -/* PLL_CPU derivatives */ - occ_cpu: occ-cpu { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_CPU>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ - compatible = "fixed-factor-clock"; - clocks = <&occ_cpu>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - cpc_clk: cpc-clk { - compatible = "fixed-factor-clock"; - clocks = <&si_css0_ref_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - core0_clk: core0-clk { - compatible = "fixed-factor-clock"; - clocks = <&si_css0_ref_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - core1_clk: core1-clk { - compatible = "fixed-factor-clock"; - clocks = <&si_css0_ref_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - core2_clk: core2-clk { - compatible = "fixed-factor-clock"; - clocks = <&si_css0_ref_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - core3_clk: core3-clk { - compatible = "fixed-factor-clock"; - clocks = <&si_css0_ref_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - cm_clk: cm-clk { - compatible = "fixed-factor-clock"; - clocks = <&si_css0_ref_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - mem_clk: mem-clk { - compatible = "fixed-factor-clock"; - clocks = <&si_css0_ref_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - occ_isram: occ-isram { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_CPU>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - isram_clk: isram-clk { /* gate ClkRstGen_isram */ - compatible = "fixed-factor-clock"; - clocks = <&occ_isram>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - occ_dbu: occ-dbu { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_CPU>; - #clock-cells = <0>; - clock-div = <10>; - clock-mult = <1>; - }; - si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ - compatible = "fixed-factor-clock"; - clocks = <&occ_dbu>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; -/* PLL_VDI derivatives */ - occ_vdi: occ-vdi { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_VDI>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ - compatible = "fixed-factor-clock"; - clocks = <&occ_vdi>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - occ_can_ser: occ-can-ser { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_VDI>; - #clock-cells = <0>; - clock-div = <16>; - clock-mult = <1>; - }; - can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ - compatible = "fixed-factor-clock"; - clocks = <&occ_can_ser>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - i2c_ser_clk: i2c-ser-clk { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_VDI>; - #clock-cells = <0>; - clock-div = <20>; - clock-mult = <1>; - }; -/* PLL_PER derivatives */ - occ_periph: occ-periph { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_PER>; - #clock-cells = <0>; - clock-div = <16>; - clock-mult = <1>; - }; - periph_clk: periph-clk { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - can_clk: can-clk { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - spi_clk: spi-clk { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - i2c_clk: i2c-clk { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "i2c_clk"; - }; - timer_clk: timer-clk { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "timer_clk"; - }; - gpio_clk: gpio-clk { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "gpio_clk"; - }; - emmc_sys_clk: emmc-sys-clk { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_PER>; - #clock-cells = <0>; - clock-div = <10>; - clock-mult = <1>; - clock-output-names = "emmc_sys_clk"; - }; - ccf_ctrl_clk: ccf-ctrl-clk { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_PER>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "ccf_ctrl_clk"; - }; - occ_mjpeg_core: occ-mjpeg-core { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_PER>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clock-output-names = "occ_mjpeg_core"; - }; - hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ - compatible = "fixed-factor-clock"; - clocks = <&occ_mjpeg_core>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "hsm_clk"; - }; - mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ - compatible = "fixed-factor-clock"; - clocks = <&occ_mjpeg_core>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "mjpeg_core_clk"; - }; - fcmu_a_clk: fcmu-a-clk { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_PER>; - #clock-cells = <0>; - clock-div = <20>; - clock-mult = <1>; - clock-output-names = "fcmu_a_clk"; - }; - occ_pci_sys: occ-pci-sys { - compatible = "fixed-factor-clock"; - clocks = <&olb EQ5C_PLL_PER>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clock-output-names = "occ_pci_sys"; - }; - pclk: pclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; /* 250MHz */ - }; - tsu_clk: tsu-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; /* 125MHz */ - }; -}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 0708771c193d064fa56be2c7f6115672b5c24d8d..5d73e8320b8efc1b4f68923482bf188c4345f1cb 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ #include -#include "eyeq5-clocks.dtsi" +#include / { #address-cells = <2>; @@ -17,7 +17,7 @@ cpu@0 { device_type = "cpu"; compatible = "img,i6500"; reg = <0>; - clocks = <&core0_clk>; + clocks = <&olb EQ5C_CPU_CORE0>; }; }; @@ -64,6 +64,24 @@ cpu_intc: interrupt-controller { #interrupt-cells = <1>; }; + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + }; + + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + + tsu_clk: tsu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; + soc: soc { #address-cells = <2>; #size-cells = <2>; @@ -76,7 +94,7 @@ uart0: serial@800000 { reg-io-width = <4>; interrupt-parent = <&gic>; interrupts = ; - clocks = <&uart_clk>, <&occ_periph>; + clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names = "uartclk", "apb_pclk"; resets = <&olb 0 10>; pinctrl-names = "default"; @@ -89,7 +107,7 @@ uart1: serial@900000 { reg-io-width = <4>; interrupt-parent = <&gic>; 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arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Cb2ut640" Received: by mail.gandi.net (Postfix) with ESMTPSA id 8C4EA4000F; Wed, 6 Nov 2024 16:04:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730909044; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dNYxA9PoraKNMZJ+/mQFXcEzKQ9APotFg7LB3yegiRc=; b=Cb2ut640R43SAZ7IA+B+ILhnfx6FHLLV3spFTdsf59KYpm7TJcJaQHEjFvwbEUXK0lLSOy +GCR1Zakp/kxeJKjhi9LCydVtuw2YMnlSznxqU0nfZRgvNwZxBcWLF5/5dLfJKGEV+J/0z zueL8POuCLf50dlxER5BBirr2mkIWSUxHqfoNNYplNm3Ceu+EzTL6KZvrhZFEBYOTTgg7P 6uPB8j1G/rOLXsNRFeNby3J/hnhPcqN1afBnAWM2hjKOmwadBV9UHFmzoefSUKWTNK5GQe x502sFojlYfTa7cdhjaEdng60gU9fJk7JjR4QUlMZgRutq4Juc/uwavVN2YuBQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 06 Nov 2024 17:04:01 +0100 Subject: [PATCH v2 10/10] MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241106-mbly-clk-v2-10-84cfefb3f485@bootlin.com> References: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> In-Reply-To: <20241106-mbly-clk-v2-0-84cfefb3f485@bootlin.com> To: Vladimir Kondratiev , =?utf-8?q?Gr?= =?utf-8?q?=C3=A9gory_Clement?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-GND-Sasl: theo.lebrun@bootlin.com Change the declaration of clocks: remove all fixed clocks and declare system-controllers (OLB) as clock providers. Remove eyeq6h-fixed-clocks.dtsi and move the crystal clock to the main eyeq6h.dtsi file. Signed-off-by: Théo Lebrun --- .../boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi | 52 --------------- arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 73 ++++++++++++++++++++-- 2 files changed, 69 insertions(+), 56 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi deleted file mode 100644 index 5fa99e06fde7e8f4942aafe5f6064e2c6f7d83fd..0000000000000000000000000000000000000000 --- a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright 2023 Mobileye Vision Technologies Ltd. - */ - -#include - -/ { - xtal: clock-30000000 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - }; - - pll_west: clock-2000000000-west { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - - pll_cpu: clock-2000000000-cpu { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - - /* pll-cpu derivatives */ - occ_cpu: clock-2000000000-occ-cpu { - compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - /* pll-west derivatives */ - occ_periph_w: clock-200000000 { - compatible = "fixed-factor-clock"; - clocks = <&pll_west>; - #clock-cells = <0>; - clock-div = <10>; - clock-mult = <1>; - }; - uart_clk: clock-200000000-uart { - compatible = "fixed-factor-clock"; - clocks = <&occ_periph_w>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - -}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi index 1db3c3cda2e395025075387bcb66ea0737fd37f6..4a1a43f351d39625b520a16d035cacd2e29d157c 100644 --- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -5,7 +5,7 @@ #include -#include "eyeq6h-fixed-clocks.dtsi" +#include / { #address-cells = <2>; @@ -17,7 +17,7 @@ cpu@0 { device_type = "cpu"; compatible = "img,i6500"; reg = <0>; - clocks = <&occ_cpu>; + clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>; }; }; @@ -32,19 +32,42 @@ cpu_intc: interrupt-controller { #interrupt-cells = <1>; }; + xtal: clock-30000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; + olb_acc: system-controller@d2003000 { + compatible = "mobileye,eyeq6h-acc-olb", "syscon"; + reg = <0x0 0xd2003000 0x0 0x1000>; + #reset-cells = <1>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + + olb_central: system-controller@d3100000 { + compatible = "mobileye,eyeq6h-central-olb", "syscon"; + reg = <0x0 0xd3100000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + uart0: serial@d3331000 { compatible = "arm,pl011", "arm,primecell"; reg = <0 0xd3331000 0x0 0x1000>; reg-io-width = <4>; interrupt-parent = <&gic>; interrupts = ; - clocks = <&occ_periph_w>, <&occ_periph_w>; + clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>; clock-names = "uartclk", "apb_pclk"; }; @@ -56,6 +79,15 @@ pinctrl_west: pinctrl@d3337000 { pinctrl-single,function-mask = <0xffff>; }; + olb_west: system-controller@d3338000 { + compatible = "mobileye,eyeq6h-west-olb", "syscon"; + reg = <0x0 0xd3338000 0x0 0x1000>; + #reset-cells = <1>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + pinctrl_east: pinctrl@d3357000 { compatible = "pinctrl-single"; reg = <0x0 0xd3357000 0x0 0xb0>; @@ -64,6 +96,23 @@ pinctrl_east: pinctrl@d3357000 { pinctrl-single,function-mask = <0xffff>; }; + olb_east: system-controller@d3358000 { + compatible = "mobileye,eyeq6h-east-olb", "syscon"; + reg = <0x0 0xd3358000 0x0 0x1000>; + #reset-cells = <1>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + + olb_south: system-controller@d8013000 { + compatible = "mobileye,eyeq6h-south-olb", "syscon"; + reg = <0x0 0xd8013000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + pinctrl_south: pinctrl@d8014000 { compatible = "pinctrl-single"; reg = <0x0 0xd8014000 0x0 0xf8>; @@ -72,6 +121,22 @@ pinctrl_south: pinctrl@d8014000 { pinctrl-single,function-mask = <0xffff>; }; + olb_ddr0: system-controller@e4080000 { + compatible = "mobileye,eyeq6h-ddr0-olb", "syscon"; + reg = <0x0 0xe4080000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + + olb_ddr1: system-controller@e4081000 { + compatible = "mobileye,eyeq6h-ddr1-olb", "syscon"; + reg = <0x0 0xe4081000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + gic: interrupt-controller@f0920000 { compatible = "mti,gic"; reg = <0x0 0xf0920000 0x0 0x20000>; @@ -89,7 +154,7 @@ gic: interrupt-controller@f0920000 { timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&occ_cpu>; + clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>; }; }; };