From patchwork Wed Nov 6 18:47:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher S M Hall X-Patchwork-Id: 13865280 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F895208236 for ; Wed, 6 Nov 2024 18:58:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730919533; cv=none; b=H9yDPwsKExZn7AaUvVzuw8chLxoi5ag5E2DRtTJK+VMWu5vWrLDJw+oiz6TJI7UICIXpK22RxNj23Mqi9fPFdX6SjwxKptd1PmZ3PssdtweKPImtiZyNp0DgJJb4zU89CUtUKnvM6L7OZd0LSsNk7d+PyHXQK22cOclKVcSRnYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730919533; c=relaxed/simple; bh=INK4rzX+ifNzPtwqxjtgntQ3Qurtmz7AEunuf4qJjOk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A0f6qCE3JqUXrJZkdhjh9Ljz263eF2/K003l/gwJY8Ilp25SkAlBZxIgK3fuYEL0DqFkKvJu2TcjBmod9EaTlZqpqx6SNFh2oZ1++LpZqKr0nFNYdebV6ToWxPQdceczrTCNWxHJJKkw2OUkt3XNFPPdtrpFQxR1XVycWrQkLao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MvgGWj18; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MvgGWj18" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730919532; x=1762455532; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=INK4rzX+ifNzPtwqxjtgntQ3Qurtmz7AEunuf4qJjOk=; b=MvgGWj18SERubq3k8El8ZnW7+p1yLcq98v+fql9V617SLj4DCKka/Sd3 rahlEjvwTzB4mjFhvgiEmhgzciDgbPC3WTDrqvo6zWzI0Gd1kmujzVvDa lh6Z0KMT5KTEghPRohcM3Cqk4499mlJlnQkwSsM3hmSUg9DVo5od5YMJA 5Z/oTecU4CsHhcIL0bWMN07W5FZ/aoF+uZzl6Fq4ZrC+4s8oK/jdIx05a vGw2DmHXy1smM5dJ70TbfxYps1+5u85uv3uGpglm4IRkNLwOUo/ZTKyP/ Mh2hl90KL777zyQGSKcbeiDHO+5Y2EyFmg9fYJJB3xHkGoZ0fZNtmMk4R w==; X-CSE-ConnectionGUID: Jl78tZOlTg6yloIC571n1w== X-CSE-MsgGUID: vIkAfIebREycNzq6V8wcPQ== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="30959461" X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="30959461" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 10:58:50 -0800 X-CSE-ConnectionGUID: DpTZbD/STjWSZBTG9XBUTA== X-CSE-MsgGUID: qAptyY6BREqCWIYLP13feA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="89813790" Received: from timelab-spr11.ch.intel.com ([143.182.136.151]) by orviesa004.jf.intel.com with ESMTP; 06 Nov 2024 10:56:39 -0800 From: Christopher S M Hall To: intel-wired-lan@lists.osuosl.org Cc: david.zage@intel.com, vinicius.gomes@intel.com, netdev@vger.kernel.org, rodrigo.cadore@l-acoustics.com, vinschen@redhat.com, Michal Swiatkowski , Mor Bar-Gabay , Avigail Dahan Subject: [PATCH iwl-net v3 1/6] igc: Ensure the PTM cycle is reliably triggered Date: Wed, 6 Nov 2024 18:47:17 +0000 Message-Id: <20241106184722.17230-2-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241106184722.17230-1-christopher.s.hall@intel.com> References: <20241106184722.17230-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Writing to clear the PTM status 'valid' bit while the PTM cycle is triggered results in unreliable PTM operation. To fix this, clear the PTM 'trigger' and status after each PTM transaction. The issue can be reproduced with the following: $ sudo phc2sys -R 1000 -O 0 -i tsn0 -m Note: 1000 Hz (-R 1000) is unrealistically large, but provides a way to quickly reproduce the issue. PHC2SYS exits with: "ioctl PTP_OFFSET_PRECISE: Connection timed out" when the PTM transaction fails Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Reviewed-by: Michal Swiatkowski Tested-by: Mor Bar-Gabay Tested-by: Avigail Dahan Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc_defines.h | 1 + drivers/net/ethernet/intel/igc/igc_ptp.c | 70 ++++++++++++-------- 2 files changed, 42 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 8e449904aa7d..2ff292f5f63b 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -593,6 +593,7 @@ #define IGC_PTM_STAT_T4M1_OVFL BIT(3) /* T4 minus T1 overflow */ #define IGC_PTM_STAT_ADJUST_1ST BIT(4) /* 1588 timer adjusted during 1st PTM cycle */ #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */ +#define IGC_PTM_STAT_ALL GENMASK(5, 0) /* Used to clear all status */ /* PCIe PTM Cycle Control */ #define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec) ((msec) & 0x3ff) /* PTM Cycle Time (msec) */ diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 946edbad4302..c640e346342b 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -974,13 +974,40 @@ static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat) } } +static void igc_ptm_trigger(struct igc_hw *hw) +{ + u32 ctrl; + + /* To "manually" start the PTM cycle we need to set the + * trigger (TRIG) bit + */ + ctrl = rd32(IGC_PTM_CTRL); + ctrl |= IGC_PTM_CTRL_TRIG; + wr32(IGC_PTM_CTRL, ctrl); + /* Perform flush after write to CTRL register otherwise + * transaction may not start + */ + wrfl(); +} + +static void igc_ptm_reset(struct igc_hw *hw) +{ + u32 ctrl; + + ctrl = rd32(IGC_PTM_CTRL); + ctrl &= ~IGC_PTM_CTRL_TRIG; + wr32(IGC_PTM_CTRL, ctrl); + /* Write to clear all status */ + wr32(IGC_PTM_STAT, IGC_PTM_STAT_ALL); +} + static int igc_phc_get_syncdevicetime(ktime_t *device, struct system_counterval_t *system, void *ctx) { - u32 stat, t2_curr_h, t2_curr_l, ctrl; struct igc_adapter *adapter = ctx; struct igc_hw *hw = &adapter->hw; + u32 stat, t2_curr_h, t2_curr_l; int err, count = 100; ktime_t t1, t2_curr; @@ -994,25 +1021,13 @@ static int igc_phc_get_syncdevicetime(ktime_t *device, * are transitory. Repeating the process returns valid * data eventually. */ - - /* To "manually" start the PTM cycle we need to clear and - * then set again the TRIG bit. - */ - ctrl = rd32(IGC_PTM_CTRL); - ctrl &= ~IGC_PTM_CTRL_TRIG; - wr32(IGC_PTM_CTRL, ctrl); - ctrl |= IGC_PTM_CTRL_TRIG; - wr32(IGC_PTM_CTRL, ctrl); - - /* The cycle only starts "for real" when software notifies - * that it has read the registers, this is done by setting - * VALID bit. - */ - wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); + igc_ptm_trigger(hw); err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat, stat, IGC_PTM_STAT_SLEEP, IGC_PTM_STAT_TIMEOUT); + igc_ptm_reset(hw); + if (err < 0) { netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n"); return err; @@ -1021,15 +1036,7 @@ static int igc_phc_get_syncdevicetime(ktime_t *device, if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID) break; - if (stat & ~IGC_PTM_STAT_VALID) { - /* An error occurred, log it. */ - igc_ptm_log_error(adapter, stat); - /* The STAT register is write-1-to-clear (W1C), - * so write the previous error status to clear it. - */ - wr32(IGC_PTM_STAT, stat); - continue; - } + igc_ptm_log_error(adapter, stat); } while (--count); if (!count) { @@ -1255,7 +1262,7 @@ void igc_ptp_stop(struct igc_adapter *adapter) void igc_ptp_reset(struct igc_adapter *adapter) { struct igc_hw *hw = &adapter->hw; - u32 cycle_ctrl, ctrl; + u32 cycle_ctrl, ctrl, stat; unsigned long flags; u32 timadj; @@ -1290,14 +1297,19 @@ void igc_ptp_reset(struct igc_adapter *adapter) ctrl = IGC_PTM_CTRL_EN | IGC_PTM_CTRL_START_NOW | IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) | - IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) | - IGC_PTM_CTRL_TRIG; + IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT); wr32(IGC_PTM_CTRL, ctrl); /* Force the first cycle to run. */ - wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); + igc_ptm_trigger(hw); + + if (readx_poll_timeout_atomic(rd32, IGC_PTM_STAT, stat, + stat, IGC_PTM_STAT_SLEEP, + IGC_PTM_STAT_TIMEOUT)) + netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n"); + igc_ptm_reset(hw); break; default: /* No work to do. */ From patchwork Wed Nov 6 18:47:18 2024 Content-Type: text/plain; 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06 Nov 2024 10:56:40 -0800 From: Christopher S M Hall To: intel-wired-lan@lists.osuosl.org Cc: david.zage@intel.com, vinicius.gomes@intel.com, netdev@vger.kernel.org, rodrigo.cadore@l-acoustics.com, vinschen@redhat.com, Michal Swiatkowski , Mor Bar-Gabay , Avigail Dahan Subject: [PATCH iwl-net v3 2/6] igc: Lengthen the hardware retry time to prevent timeouts Date: Wed, 6 Nov 2024 18:47:18 +0000 Message-Id: <20241106184722.17230-3-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241106184722.17230-1-christopher.s.hall@intel.com> References: <20241106184722.17230-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Lengthen the hardware retry timer to four microseconds. The i225/i226 hardware retries if it receives an inappropriate response from the upstream device. If the device retries too quickly, the root port does not respond. The issue can be reproduced with the following: $ sudo phc2sys -R 1000 -O 0 -i tsn0 -m Note: 1000 Hz (-R 1000) is unrealistically large, but provides a way to quickly reproduce the issue. PHC2SYS exits with: "ioctl PTP_OFFSET_PRECISE: Connection timed out" when the PTM transaction fails Fixes: 6b8aa753a9f9 ("igc: Decrease PTM short interval from 10 us to 1 us") Reviewed-by: Michal Swiatkowski Tested-by: Mor Bar-Gabay Tested-by: Avigail Dahan Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc_defines.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 2ff292f5f63b..84521a4c35b4 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -574,7 +574,7 @@ #define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2) #define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8) -#define IGC_PTM_SHORT_CYC_DEFAULT 1 /* Default short cycle interval */ +#define IGC_PTM_SHORT_CYC_DEFAULT 4 /* Default short cycle interval */ #define IGC_PTM_CYC_TIME_DEFAULT 5 /* Default PTM cycle time */ #define IGC_PTM_TIMEOUT_DEFAULT 255 /* Default timeout for PTM errors */ From patchwork Wed Nov 6 18:47:19 2024 Content-Type: text/plain; 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06 Nov 2024 10:56:40 -0800 From: Christopher S M Hall To: intel-wired-lan@lists.osuosl.org Cc: david.zage@intel.com, vinicius.gomes@intel.com, netdev@vger.kernel.org, rodrigo.cadore@l-acoustics.com, vinschen@redhat.com, Michal Swiatkowski , Mor Bar-Gabay , Avigail Dahan Subject: [PATCH iwl-net v3 3/6] igc: Move ktime snapshot into PTM retry loop Date: Wed, 6 Nov 2024 18:47:19 +0000 Message-Id: <20241106184722.17230-4-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241106184722.17230-1-christopher.s.hall@intel.com> References: <20241106184722.17230-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Move ktime_get_snapshot() into the loop. If a retry does occur, a more recent snapshot will result in a more accurate cross-timestamp. Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Reviewed-by: Michal Swiatkowski Tested-by: Mor Bar-Gabay Tested-by: Avigail Dahan Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc_ptp.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index c640e346342b..516abe7405de 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -1011,16 +1011,16 @@ static int igc_phc_get_syncdevicetime(ktime_t *device, int err, count = 100; ktime_t t1, t2_curr; - /* Get a snapshot of system clocks to use as historic value. */ - ktime_get_snapshot(&adapter->snapshot); - + /* Doing this in a loop because in the event of a + * badly timed (ha!) system clock adjustment, we may + * get PTM errors from the PCI root, but these errors + * are transitory. Repeating the process returns valid + * data eventually. + */ do { - /* Doing this in a loop because in the event of a - * badly timed (ha!) system clock adjustment, we may - * get PTM errors from the PCI root, but these errors - * are transitory. Repeating the process returns valid - * data eventually. - */ + /* Get a snapshot of system clocks to use as historic value. */ + ktime_get_snapshot(&adapter->snapshot); + igc_ptm_trigger(hw); err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat, From patchwork Wed Nov 6 18:47:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher S M Hall X-Patchwork-Id: 13865282 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06ACA207A1A for ; Wed, 6 Nov 2024 18:58:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730919535; cv=none; b=o2AZ5+h+FHHizYkaD6Xad4/IG+CpH0OFvaKuOvaXl4oTm0Vy0Ha0dCIR0XJWQG61R9bl3HvOeedmVLwTkR9WdXOBG3Xhnka48YBcKQrdttRYI/zvNAtkf4Oq2zAguCZ4j8PkwPJtl1dg6LLOcO0PRwr21+h1q+rOEfwPSeEg8f0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730919535; c=relaxed/simple; bh=QOTNwCbXC0dEBBEghJ97he0ts6uyFWd6JAr1mw42WaI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ejj58tfBpamBGdqaahysrhxErHaNldNaLcLCcYEx9zgPZee5fIZ+MzRL7OfrtGGOnhto2SL6gTtkS2D0CpH64e9akiti2fBjqqyLNQRaBs42bS1IoL2+ye3H26RLCGUESO9O22NB0JoTaOilN96rroZWuGhGeuepZzUi9Ofccz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XenMr2lm; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XenMr2lm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730919534; x=1762455534; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QOTNwCbXC0dEBBEghJ97he0ts6uyFWd6JAr1mw42WaI=; b=XenMr2lmssLaaEdzlCwcQmqR4FOWRiJRC5KpiRBxHSkFHXTSa3Azw0Q0 VVibS6MnePV/jKn8YJQRHmb1XBnCtjvOhtjwbXMUoiJDAHmrAxV536xRT biGO9389q8me9HMOhH7HV46AyPLXQOU+s8vQ+qCh0Aq3Fjc8BCcpgJX16 h7NV4wDDvOoPLriUCiFVUbtd+yH+H+MpC70mkJOWCu2ri/join7e9zVOT s0YdaNR+I47e3KE5nJZes+3OKkxagYmlqPLHLFCAibj3hjy2LvA7KwrUJ E7alOiZqsrgbLiFhYD8uYstkAFVheoJ4FhfCz6FzWq09QZ+w0q+G2D4HU g==; X-CSE-ConnectionGUID: Kpk7y74tTBK70hD/Xkp8Ug== X-CSE-MsgGUID: Rfqhq+PKTlGJpvBmBg/klA== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="30959470" X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="30959470" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 10:58:51 -0800 X-CSE-ConnectionGUID: Wt116T5XSFmacTxaz98PaQ== X-CSE-MsgGUID: kiB6UEE4S4ecp80eDo+RnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="89813797" Received: from timelab-spr11.ch.intel.com ([143.182.136.151]) by orviesa004.jf.intel.com with ESMTP; 06 Nov 2024 10:56:41 -0800 From: Christopher S M Hall To: intel-wired-lan@lists.osuosl.org Cc: david.zage@intel.com, vinicius.gomes@intel.com, netdev@vger.kernel.org, rodrigo.cadore@l-acoustics.com, vinschen@redhat.com Subject: [PATCH iwl-net v3 4/6] igc: Handle the IGC_PTP_ENABLED flag correctly Date: Wed, 6 Nov 2024 18:47:20 +0000 Message-Id: <20241106184722.17230-5-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241106184722.17230-1-christopher.s.hall@intel.com> References: <20241106184722.17230-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org All functions in igc_ptp.c called from igc_main.c should check the IGC_PTP_ENABLED flag. Adding check for this flag to stop and reset functions. Fixes: 5f2958052c58 ("igc: Add basic skeleton for PTP") Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc_ptp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 516abe7405de..343205bffc35 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -1244,8 +1244,12 @@ void igc_ptp_suspend(struct igc_adapter *adapter) **/ void igc_ptp_stop(struct igc_adapter *adapter) { + if (!(adapter->ptp_flags & IGC_PTP_ENABLED)) + return; + igc_ptp_suspend(adapter); + adapter->ptp_flags &= ~IGC_PTP_ENABLED; if (adapter->ptp_clock) { ptp_clock_unregister(adapter->ptp_clock); netdev_info(adapter->netdev, "PHC removed\n"); @@ -1266,6 +1270,9 @@ void igc_ptp_reset(struct igc_adapter *adapter) unsigned long flags; u32 timadj; + if (!(adapter->ptp_flags & IGC_PTP_ENABLED)) + return; + /* reset the tstamp_config */ igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 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06 Nov 2024 10:56:41 -0800 From: Christopher S M Hall To: intel-wired-lan@lists.osuosl.org Cc: david.zage@intel.com, vinicius.gomes@intel.com, netdev@vger.kernel.org, rodrigo.cadore@l-acoustics.com, vinschen@redhat.com Subject: [PATCH iwl-net v3 5/6] igc: Cleanup PTP module if probe fails Date: Wed, 6 Nov 2024 18:47:21 +0000 Message-Id: <20241106184722.17230-6-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241106184722.17230-1-christopher.s.hall@intel.com> References: <20241106184722.17230-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Make sure that the PTP module is cleaned up if the igc_probe() fails by calling igc_ptp_stop() on exit. Fixes: d89f88419f99 ("igc: Add skeletal frame for Intel(R) 2.5G Ethernet Controller support") Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc_main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 6e70bca15db1..cc89b72c85af 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -7169,6 +7169,7 @@ static int igc_probe(struct pci_dev *pdev, err_register: igc_release_hw_control(adapter); + igc_ptp_stop(adapter); err_eeprom: if (!igc_check_reset_block(hw)) igc_reset_phy(hw); From patchwork Wed Nov 6 18:47:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher S M Hall X-Patchwork-Id: 13865285 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D23D5209697 for ; Wed, 6 Nov 2024 18:58:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730919537; cv=none; b=g1MjfS9cNoeptk+7aivM/2RXoArxrQR9jIGzUWI4pdSznc8USBc71uIOfmyTEHwnzGOe/AUXDEV9eE2UiB9gwAKMQOlRsBmjuu/xOigRX/QkM6L2gwsMPDJ2XL5i88X6vo4xQt+nO2hekaNO/fTZSX/01yEXM1xybKPlZ32zcfI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730919537; c=relaxed/simple; bh=bt7XG36pg3234h1RpdS9ZPjF7IWhCP4yi40vlCJTGls=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FYh8L+uh9TtJteFOHgFQI6HroAVEZANbS38C5fTlxNdCER4VXrdGRqDxmHArXCZSj5ck/coNqILAgPXsD2XsbJ3ML2g1nk0gxmOyRg9KiaIIzkR1IXZ/+uNdpAUZhI3h9ej4MaI9R5+55TZrXUZ9K75kyqWjSkglX2NUmhDFHgk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EfWCG2lT; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EfWCG2lT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730919536; x=1762455536; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bt7XG36pg3234h1RpdS9ZPjF7IWhCP4yi40vlCJTGls=; b=EfWCG2lTRxdlbQzy7X8xFy6KB+FsFsa7gyCgMLDf9qPIBZYoyvDrrOS5 XAkbUetksPoa15fi1LRzuMTeZ4W1eZZbEX7D1UdSiAqHdpIRh+pARmZvX fnb4976XlONMjZuGj71yF28uK7acu/EWIa82PxmkqcjPuIBldHj9Yk8ej om6SFdEQ9Z4CYlxme06PthLeYscZiGOTjoVqWn7U9hn6OU0IdqM0/WY+c NQJcBGpKGS2thNeVqW1BaQpSh8x6ljQMmvU1SK92i+0KU/O5FoPbu4tLV gcx1i1dzYForV8nivzQbWY2ozvbXOmFqNDWi+6dcKXQbsFHlzjlg3wtU2 A==; X-CSE-ConnectionGUID: rWnzaxu4TQG64i0xrUZxvQ== X-CSE-MsgGUID: 0aUIYvv5Qze9S9UpHQZLSw== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="30959485" X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="30959485" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 10:58:52 -0800 X-CSE-ConnectionGUID: clNr92t9TmaCBl+JWltSiw== X-CSE-MsgGUID: ITsS1WUlQ0i0Ncor/HuHYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="89813801" Received: from timelab-spr11.ch.intel.com ([143.182.136.151]) by orviesa004.jf.intel.com with ESMTP; 06 Nov 2024 10:56:42 -0800 From: Christopher S M Hall To: intel-wired-lan@lists.osuosl.org Cc: david.zage@intel.com, vinicius.gomes@intel.com, netdev@vger.kernel.org, rodrigo.cadore@l-acoustics.com, vinschen@redhat.com Subject: [PATCH iwl-net v3 6/6] igc: Add lock preventing multiple simultaneous PTM transactions Date: Wed, 6 Nov 2024 18:47:22 +0000 Message-Id: <20241106184722.17230-7-christopher.s.hall@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241106184722.17230-1-christopher.s.hall@intel.com> References: <20241106184722.17230-1-christopher.s.hall@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Add a mutex around the PTM transaction to prevent multiple transactors Multiple processes try to initiate a PTM transaction, one or all may fail. This can be reproduced by running two instances of the following: $ sudo phc2sys -O 0 -i tsn0 -m PHC2SYS exits with: "ioctl PTP_OFFSET_PRECISE: Connection timed out" when the PTM transaction fails Note: Normally two instance of PHC2SYS will not run, but one process should not break another. Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Signed-off-by: Christopher S M Hall --- drivers/net/ethernet/intel/igc/igc.h | 1 + drivers/net/ethernet/intel/igc/igc_ptp.c | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h index eac0f966e0e4..323db1e2be38 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -319,6 +319,7 @@ struct igc_adapter { struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ ktime_t ptp_reset_start; /* Reset time in clock mono */ struct system_time_snapshot snapshot; + struct mutex ptm_lock; /* Only allow one PTM transaction at a time */ char fw_version[32]; diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 343205bffc35..612ed26a29c5 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -974,6 +974,7 @@ static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat) } } +/* The PTM lock: adapter->ptm_lock must be held when calling igc_ptm_trigger() */ static void igc_ptm_trigger(struct igc_hw *hw) { u32 ctrl; @@ -990,6 +991,7 @@ static void igc_ptm_trigger(struct igc_hw *hw) wrfl(); } +/* The PTM lock: adapter->ptm_lock must be held when calling igc_ptm_reset() */ static void igc_ptm_reset(struct igc_hw *hw) { u32 ctrl; @@ -1068,9 +1070,16 @@ static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp, { struct igc_adapter *adapter = container_of(ptp, struct igc_adapter, ptp_caps); + int ret; - return get_device_system_crosststamp(igc_phc_get_syncdevicetime, - adapter, &adapter->snapshot, cts); + /* This blocks until any in progress PTM transactions complete */ + mutex_lock(&adapter->ptm_lock); + + ret = get_device_system_crosststamp(igc_phc_get_syncdevicetime, + adapter, &adapter->snapshot, cts); + mutex_unlock(&adapter->ptm_lock); + + return ret; } static int igc_ptp_getcyclesx64(struct ptp_clock_info *ptp, @@ -1169,6 +1178,7 @@ void igc_ptp_init(struct igc_adapter *adapter) spin_lock_init(&adapter->ptp_tx_lock); spin_lock_init(&adapter->free_timer_lock); spin_lock_init(&adapter->tmreg_lock); + mutex_init(&adapter->ptm_lock); adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; @@ -1181,6 +1191,7 @@ void igc_ptp_init(struct igc_adapter *adapter) if (IS_ERR(adapter->ptp_clock)) { adapter->ptp_clock = NULL; netdev_err(netdev, "ptp_clock_register failed\n"); + mutex_destroy(&adapter->ptm_lock); } else if (adapter->ptp_clock) { netdev_info(netdev, "PHC added\n"); adapter->ptp_flags |= IGC_PTP_ENABLED; @@ -1210,10 +1221,12 @@ static void igc_ptm_stop(struct igc_adapter *adapter) struct igc_hw *hw = &adapter->hw; u32 ctrl; + mutex_lock(&adapter->ptm_lock); ctrl = rd32(IGC_PTM_CTRL); ctrl &= ~IGC_PTM_CTRL_EN; wr32(IGC_PTM_CTRL, ctrl); + mutex_unlock(&adapter->ptm_lock); } /** @@ -1255,6 +1268,7 @@ void igc_ptp_stop(struct igc_adapter *adapter) netdev_info(adapter->netdev, "PHC removed\n"); adapter->ptp_flags &= ~IGC_PTP_ENABLED; } + mutex_destroy(&adapter->ptm_lock); } /** @@ -1294,6 +1308,7 @@ void igc_ptp_reset(struct igc_adapter *adapter) if (!igc_is_crosststamp_supported(adapter)) break; + mutex_lock(&adapter->ptm_lock); wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT); wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT); @@ -1317,6 +1332,7 @@ void igc_ptp_reset(struct igc_adapter *adapter) netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n"); igc_ptm_reset(hw); + mutex_unlock(&adapter->ptm_lock); break; default: /* No work to do. */