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Signed-off-by: Ilkka Koskinen --- tools/perf/util/arm-spe.c | 65 ++++++++++++++++++++++++--------------- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index dbf13f47879c..b222557cc27a 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -103,6 +103,18 @@ struct arm_spe_queue { u32 flags; }; +struct data_src { + struct midr_range midr_range; + void (*ds_synth)(const struct arm_spe_record *record, + union perf_mem_data_src *data_src); +}; + +#define DS(range, func) \ + { \ + .midr_range = range, \ + .ds_synth = arm_spe__synth_##func, \ + } + static void arm_spe_dump(struct arm_spe *spe __maybe_unused, unsigned char *buf, size_t len) { @@ -430,19 +442,6 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } -static const struct midr_range common_ds_encoding_cpus[] = { - MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), - MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), - MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), - MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), - {}, -}; - static void arm_spe__sample_flags(struct arm_spe_queue *speq) { const struct arm_spe_record *record = &speq->decoder->record; @@ -532,6 +531,19 @@ static void arm_spe__synth_data_source_common(const struct arm_spe_record *recor } } +static const struct data_src data_sources[] = { + DS(MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), data_source_common), + {}, +}; + static void arm_spe__synth_memory_level(const struct arm_spe_record *record, union perf_mem_data_src *data_src) { @@ -555,12 +567,14 @@ static void arm_spe__synth_memory_level(const struct arm_spe_record *record, data_src->mem_lvl |= PERF_MEM_LVL_REM_CCE1; } -static bool arm_spe__is_common_ds_encoding(struct arm_spe_queue *speq) +static bool arm_spe__synth_ds(struct arm_spe_queue *speq, + const struct arm_spe_record *record, + union perf_mem_data_src *data_src) { struct arm_spe *spe = speq->spe; - bool is_in_cpu_list; + const struct data_src *src = data_sources; u64 *metadata = NULL; - u64 midr = 0; + u64 midr; /* Metadata version 1 assumes all CPUs are the same (old behavior) */ if (spe->metadata_ver == 1) { @@ -592,18 +606,21 @@ static bool arm_spe__is_common_ds_encoding(struct arm_spe_queue *speq) midr = metadata[ARM_SPE_CPU_MIDR]; } - is_in_cpu_list = is_midr_in_range_list(midr, common_ds_encoding_cpus); - if (is_in_cpu_list) - return true; - else - return false; + while (src->midr_range.model) { + if (is_midr_in_range(midr, &src->midr_range)) { + src->ds_synth(record, data_src); + return true; + } + src++; + } + + return false; } static u64 arm_spe__synth_data_source(struct arm_spe_queue *speq, const struct arm_spe_record *record) { union perf_mem_data_src data_src = { .mem_op = PERF_MEM_OP_NA }; - bool is_common = arm_spe__is_common_ds_encoding(speq); if (record->op & ARM_SPE_OP_LD) data_src.mem_op = PERF_MEM_OP_LOAD; @@ -612,9 +629,7 @@ static u64 arm_spe__synth_data_source(struct arm_spe_queue *speq, else return 0; - if (is_common) - arm_spe__synth_data_source_common(record, &data_src); - else + if (!arm_spe__synth_ds(speq, record, &data_src)) arm_spe__synth_memory_level(record, &data_src); if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) { From patchwork Wed Nov 6 19:37:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilkka Koskinen X-Patchwork-Id: 13865504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEAB0D59F6C for ; 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The field is IMPDEF. Signed-off-by: Ilkka Koskinen --- .../util/arm-spe-decoder/arm-spe-decoder.h | 9 +++++ tools/perf/util/arm-spe.c | 39 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h index 358c611eeddb..4bcd627e859f 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -67,6 +67,15 @@ enum arm_spe_common_data_source { ARM_SPE_COMMON_DS_DRAM = 0xe, }; +enum arm_spe_ampereone_data_source { + ARM_SPE_AMPEREONE_LOCAL_CHIP_CACHE_OR_DEVICE = 0x0, + ARM_SPE_AMPEREONE_SLC = 0x3, + ARM_SPE_AMPEREONE_REMOTE_CHIP_CACHE = 0x5, + ARM_SPE_AMPEREONE_DDR = 0x7, + ARM_SPE_AMPEREONE_L1D = 0x8, + ARM_SPE_AMPEREONE_L2D = 0x9, +}; + struct arm_spe_record { enum arm_spe_sample_type type; int err; diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index b222557cc27a..40847a3d18b0 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -531,6 +531,44 @@ static void arm_spe__synth_data_source_common(const struct arm_spe_record *recor } } +/* + * Source is IMPDEF. Here we convert the source code used on AmpereOne cores + * to the common (Neoverse, Cortex) to avoid duplicating the decoding code. + */ +static void arm_spe__synth_data_source_ampereone(const struct arm_spe_record *record, + union perf_mem_data_src *data_src) +{ + struct arm_spe_record common_record; + + switch (record->source) { + case ARM_SPE_AMPEREONE_LOCAL_CHIP_CACHE_OR_DEVICE: + common_record.source = ARM_SPE_COMMON_DS_PEER_CORE; + break; + case ARM_SPE_AMPEREONE_SLC: + common_record.source = ARM_SPE_COMMON_DS_SYS_CACHE; + break; + case ARM_SPE_AMPEREONE_REMOTE_CHIP_CACHE: + common_record.source = ARM_SPE_COMMON_DS_REMOTE; + break; + case ARM_SPE_AMPEREONE_DDR: + common_record.source = ARM_SPE_COMMON_DS_DRAM; + break; + case ARM_SPE_AMPEREONE_L1D: + common_record.source = ARM_SPE_COMMON_DS_L1D; + break; + case ARM_SPE_AMPEREONE_L2D: + common_record.source = ARM_SPE_COMMON_DS_L2; + break; + default: + /* Assign a bogus value that's not used for common coding */ + common_record.source = 0xffff; + break; + } + + common_record.op = record->op; + arm_spe__synth_data_source_common(&common_record, data_src); +} + static const struct data_src data_sources[] = { DS(MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), data_source_common), DS(MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), data_source_common), @@ -541,6 +579,7 @@ static const struct data_src data_sources[] = { DS(MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), data_source_common), DS(MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), data_source_common), DS(MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), data_source_common), + DS(MIDR_ALL_VERSIONS(MIDR_AMPERE1A), data_source_ampereone), {}, };