From patchwork Thu Nov 7 15:03:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13866618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35B48D43370 for ; Thu, 7 Nov 2024 15:05:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.831922.1247301 (Exim 4.92) (envelope-from ) id 1t944R-0007OM-OI; Thu, 07 Nov 2024 15:05:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 831922.1247301; Thu, 07 Nov 2024 15:05:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t944R-0007OF-Lb; Thu, 07 Nov 2024 15:05:15 +0000 Received: by outflank-mailman (input) for mailman id 831922; Thu, 07 Nov 2024 15:05:14 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t944Q-0007O4-FV for xen-devel@lists.xenproject.org; Thu, 07 Nov 2024 15:05:14 +0000 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on20611.outbound.protection.outlook.com [2a01:111:f403:2009::611]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ae30684d-9d19-11ef-a0c6-8be0dac302b0; Thu, 07 Nov 2024 16:05:10 +0100 (CET) Received: from BN0PR10CA0010.namprd10.prod.outlook.com (2603:10b6:408:143::14) by PH7PR12MB5655.namprd12.prod.outlook.com (2603:10b6:510:138::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.19; Thu, 7 Nov 2024 15:05:04 +0000 Received: from BN2PEPF00004FBA.namprd04.prod.outlook.com (2603:10b6:408:143:cafe::c3) by BN0PR10CA0010.outlook.office365.com (2603:10b6:408:143::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.20 via Frontend Transport; Thu, 7 Nov 2024 15:05:04 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF00004FBA.mail.protection.outlook.com (10.167.243.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.17 via Frontend Transport; Thu, 7 Nov 2024 15:05:04 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 7 Nov 2024 09:05:02 -0600 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 7 Nov 2024 09:05:01 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ae30684d-9d19-11ef-a0c6-8be0dac302b0 X-Custom-Connection: eyJyZW1vdGVpcCI6IjJhMDE6MTExOmY0MDM6MjAwOTo6NjExIiwiaGVsbyI6Ik5BTTEwLUJONy1vYmUub3V0Ym91bmQucHJvdGVjdGlvbi5vdXRsb29rLmNvbSJ9 X-Custom-Transaction: eyJpZCI6ImFlMzA2ODRkLTlkMTktMTFlZi1hMGM2LThiZTBkYWMzMDJiMCIsInRzIjoxNzMwOTkxOTEwLjYxMTc0MSwic2VuZGVyIjoiYXlhbi5rdW1hci5oYWxkZXJAYW1kLmNvbSIsInJlY2lwaWVudCI6Inhlbi1kZXZlbEBsaXN0cy54ZW5wcm9qZWN0Lm9yZyJ9 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DME6xoVjRXZlvstwq4Zrhxo16w7gPKrHXVheuHarjcXxpaealqr3nptwT8DVDwrPQaZsGcHOV8XfMDl4+K3etxz6OCaD/MlLZZL+i+GfOeloAlMF44GcqjpDM8OfeiBNzpOhY1TbzixEhPUCOMteLe1hFl6rwCeeX/+tki3jWq5rbLGDfcb5/0rCtaeyVGNvGOH+hikl6eboDZGKul32Un4YzwSXUnpLafdQNG0Nz7tq0ftTkiAb9CCLtgWzM5tErBEnqYcaKOz6toUHySC/1i0KPk0h4DNZCcNeLgcG4uokopwJejGTe7EATDJ1IL/Nmgs8QAAz6HPg/XtKOAuUbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=65rTsyDXUybu7MXHbDYZzPLCUNdM5/rzSPP6wjr9au8=; b=inmt3LozASUdzCQDo0JB8YUfCI3OEybTe/heJfmf7nDsxAjWGop6NNFidluGKXfWmmvwq+d8Ko78869MT74X+i3gXrdxkkpSzLA5quwTFSHi7wPOAJTtHDFxZp3XyEKk51i4/6yQ2znqShj6Uy4QrxonHwK8bGLSAIKApW+mlfrojnJTeS3+dvYsUsCpHVWldExWz6T0tTKFbyYF04jaf82LpZ18kzZPxiJqd4UMrB6B6xp3FjszQVfiHKaXVdp5ghMAJ8lt/RweyJltBDqXwRo0xnuVwniOZ+EO7XWU26UIc9Rpg2JELSc18zRJr+Ykr5bxfm6S51fyCEh8Wbqj/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=65rTsyDXUybu7MXHbDYZzPLCUNdM5/rzSPP6wjr9au8=; b=Cf7krAZ6FFTbjlL6QIInnim1y0tfcZRwL1OhIbEN2IOa58XWnJdGHo5HYbrzNrdQA0RLx8JrewZUk4yHUVSiCUHgwZTvLI2JyI/pR/L7J5QIvbjeVghbJtNvVqU6UiChQguiBR4HaK8MuA5qWrioHi6UQpKv6cuiGffHicgLl9g= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v5 1/3] xen/arm: mpu: Create boot-time MPU protection regions Date: Thu, 7 Nov 2024 15:03:28 +0000 Message-ID: <20241107150330.181143-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241107150330.181143-1-ayan.kumar.halder@amd.com> References: <20241107150330.181143-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBA:EE_|PH7PR12MB5655:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e489901-b447-40fe-fe72-08dcff3d8f3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: DZcSaOariQJuiwEVdVJjFrytsE5IITo5MjPaXJ07oD/W+ahX2kquNSr9C26LG58N6B78HmBn7du/p64/SItid9E5hHL7vuf39Z2Y1uR+ognDHkphUJrQ8pUnj5koB0jxb5Y5Qkg5j4/qkaLq6HqK2D+oJWLVX+AG9dP0GWwOg2QEMTwILaUMBGUy5gsEdGm9QOZGSyy5zfvr5Gz3j6vdglTXoM2eEUMl+LZSAkjYj62bFI9sseNYVIWDIivXvVazPCYpC762yEZAdMbuLG48uBMdnJMpNxjkACAYVqK1rq34GkZyplQTC4V7V9pJI5k2D07MpaUb8L5wE/kCLCae2PcLcxUc7ZWFG6FB7EfcDBcLOCqpI7IBRisAURqXXy9++ajgIytYVOu89nzhD8B9kVa7UcE2/PS3J7w40bsC/kQGp1if7pQfPec8fVQVOUjmnYGjZOdiNf69k3ZlU0/2aZJaPMC2VI/6lIqSGOyjPX1CUCKHBWxm7XPAtP5NbZS5ZbVwJCxFE3JKNy8rdYKnW2JNXEjqlYoMIqnAO5jRDzqYKIxdMvQxekm6RoWICecwFWlqKHayl9TB8Bw6XIEqAmD8dO0GYrUE0G2hMO60ytMpT17ogIahpHjGciUCp6bnjKUOCc6ixjy2IWnoFKamuktrrO+CHK1bN57X/R9z9vTj3Xu6A73Y/25rOS8yh57OBNefu/8csZpYzcj/oqPTg8rAySiShXdDnaFbtwB2tSVP5Qj/Ba3lgFT2XRkFY0rUAlzjdZaaghqm1vgDPoMSB5tfUyLXOrtpAhplbvOLieMzEtKsPy81RWNE0Bug+/f05grpmKgsiOtqkXTCa5H1Hv6c18bHedFfsuZ7zeWNZ7WkwqRjMtH8stL8TI/zyKn9jXCfK3Z7yMvCGk/akXuGVbfFqsyxXvB3gqjrXgcR8Ij3Xz8SbB/RhZ7IgXnygMyEsgJi0+OgyNEL8pP5nj/K2g29x+JxZirhvIKofBsLx6mDLk8eLah/wfSL5x4313kkdmHlEdPzdSMVocQtjCaheAdLxVKtuN5QaLE+fYu9NgTCdxB7Hj7NEb3Vr1BXrnBNt2UsRmWtJV02APM/2DkydIGyfkvcPEizFByjVsKGRfTCx5aHdG11hedvG9CkNle+WO44Gq551Wn3lLLLMpPQ5HD9j3mQ7lWB1vVlONHCkR70LlFg08f/yAnnvEX6uxJnk82wIMdh3ud9RnH/VDgAvMd01scGgaBcWuEQmiprBMDfnU4yFAEfjjfmnp5tbMs0779wNqu9ZDsWfi2yUIpHllDSYxvpVvHtq333dgLWr2sKdwqpzyUQ3yBOVSQwAib697H+cSARxeyXS506PiFmLoGrT6fLtm/zyz1b/fHI3QKW4TsO1YBbCHJDJ/+19tN94S4AtbWtEGyLWQj4UDj6BA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 15:05:04.0369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e489901-b447-40fe-fe72-08dcff3d8f3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5655 Define enable_boot_cpu_mm() for the Armv8-R AArch64. Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from normal memory. To do this, Xen maps the following sections of the binary as separate regions (with permissions) :- 1. Text (Read only at EL2, execution is permitted) 2. RO data (Read only at EL2) 3. RO after init data and RW data (Read/Write at EL2) 4. Init Text (Read only at EL2, execution is permitted) 5. Init data and BSS (Read/Write at EL2) Before creating a region, we check if the count exceeds the number defined in MPUIR_EL2. If so, then the boot fails. Also we check if the region is empty or not. IOW, if the start and end address are same, we skip mapping the region. To map a region, Xen uses the PRBAR_EL2, PRLAR_EL2 and PRSELR_EL2 registers. One can refer to ARM DDI 0600B.a ID062922 G1.3 "General System Control Registers", to get the definitions of these registers. Also, refer to G1.2 "Accessing MPU memory region registers", the following ``` The MPU provides two register interfaces to program the MPU regions: - Access to any of the MPU regions via PRSELR_ELx, PRBAR_ELx, and PRLAR_ELx. ``` We use the above mechanism to create the MPU memory regions. Also, the compiler needs the flag ("-march=armv8-r") in order to build Xen for Armv8-R AArch64 MPU based systems. There will be no need for us to explicitly define MPU specific registers. Signed-off-by: Ayan Kumar Halder Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu > --- Changes from :- v1 - 1. Fix some of the coding style issues. 2. Reword the help message. 3. Updat the commit message. v2 - Add clarification for the use of page and page size. v3 - 1. Add a new file arm64/mpu/mm.c to contain the build assertion for page size. 2. Enclosed the check for the start address within "#ifdef CONFIG_MPU". v4 - 1. Increment the region selector in prepare_xen_region 2. Ensure that the first 8 bits of MPUIR_EL2 are read, to determine the maximum number of supported regions. 3. Remove the inclusion of mm.h. *MPU_REGION* macros have been moved from mm.h to mpu.h. The reason being mm.h cannot be included in an assembly file. 4. Add the build flags for "Armv8-R AArch64 MPU". As a result, we don't need to define MPU registers. So, removed xen/arch/arm/include/asm/arm64/mpu/sysregs.h. xen/arch/arm/arch.mk | 4 + xen/arch/arm/arm64/mpu/Makefile | 1 + xen/arch/arm/arm64/mpu/head.S | 122 +++++++++++++++++++++++++++ xen/arch/arm/include/asm/arm64/mpu.h | 25 ++++++ xen/arch/arm/include/asm/mm.h | 2 +- xen/arch/arm/xen.lds.S | 1 + 6 files changed, 154 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm64/mpu/head.S create mode 100644 xen/arch/arm/include/asm/arm64/mpu.h diff --git a/xen/arch/arm/arch.mk b/xen/arch/arm/arch.mk index 022dcda192..9c4bedfb3b 100644 --- a/xen/arch/arm/arch.mk +++ b/xen/arch/arm/arch.mk @@ -9,7 +9,11 @@ CFLAGS-$(CONFIG_ARM_32) += -msoft-float CFLAGS-$(CONFIG_ARM_32) += -mcpu=cortex-a15 CFLAGS-$(CONFIG_ARM_32) += -mno-unaligned-access +ifeq ($(CONFIG_MPU),y) +CFLAGS-$(CONFIG_ARM_64) += -march=armv8-r +else CFLAGS-$(CONFIG_ARM_64) += -mcpu=generic +endif CFLAGS-$(CONFIG_ARM_64) += -mgeneral-regs-only # No fp registers etc $(call cc-option-add,CFLAGS-$(CONFIG_ARM_64),CC,-mno-outline-atomics) diff --git a/xen/arch/arm/arm64/mpu/Makefile b/xen/arch/arm/arm64/mpu/Makefile index b18cec4836..a8a750a3d0 100644 --- a/xen/arch/arm/arm64/mpu/Makefile +++ b/xen/arch/arm/arm64/mpu/Makefile @@ -1 +1,2 @@ +obj-y += head.o obj-y += mm.o diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S new file mode 100644 index 0000000000..37e4b455bb --- /dev/null +++ b/xen/arch/arm/arm64/mpu/head.S @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include + +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * Inputs: + * sel: region selector + * base: reg storing base address (should be page-aligned) + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + msr PRSELR_EL2, \sel + isb + msr PRBAR_EL2, \prbar + msr PRLAR_EL2, \prlar + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* + * Failure caused due to insufficient MPU regions. + */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different MPU + * regions. + * + * Inputs: + * lr : Address to return to. + * + * Clobbers x0 - x5 + * + */ +FUNC(enable_boot_cpu_mm) + /* Get the number of regions specified in MPUIR_EL2 */ + mrs x5, MPUIR_EL2 + and x5, x5, #NUM_MPU_REGIONS_MASK + + /* x0: region sel */ + mov x0, xzr + /* Xen text section. */ + ldr x1, =_stext + ldr x2, =_etext + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen read-only data section. */ + ldr x1, =_srodata + ldr x2, =_erodata + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + ldr x1, =__ro_after_init_start + ldr x2, =__init_begin + prepare_xen_region x0, x1, x2, x3, x4, x5 + + /* Xen code section. */ + ldr x1, =__init_begin + ldr x2, =__init_data_begin + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen data and BSS section. */ + ldr x1, =__init_data_begin + ldr x2, =__bss_end + prepare_xen_region x0, x1, x2, x3, x4, x5 + + ret +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h new file mode 100644 index 0000000000..f8a029f1a1 --- /dev/null +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * mpu.h: Arm Memory Protection Unit definitions. + */ + +#ifndef __ARM64_MPU_H__ +#define __ARM64_MPU_H__ + +#define MPU_REGION_SHIFT 6 +#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT) +#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1)) + +#define NUM_MPU_REGIONS_SHIFT 8 +#define NUM_MPU_REGIONS (_AC(1, UL) << NUM_MPU_REGIONS_SHIFT) +#define NUM_MPU_REGIONS_MASK (NUM_MPU_REGIONS - 1) +#endif /* __ARM64_MPU_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 5abd4b0d1c..59b774b7b8 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -16,7 +16,7 @@ #if defined(CONFIG_MMU) # include -#else +#elif !defined(CONFIG_MPU) # error "Unknown memory management layout" #endif diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index d1e579e8a8..bbccff1a03 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -147,6 +147,7 @@ SECTIONS *(.altinstr_replacement) } :text . = ALIGN(PAGE_SIZE); + __init_data_begin = .; .init.data : { *(.init.rodata) *(.init.rodata.*) From patchwork Thu Nov 7 15:03:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13866617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D869D4336F for ; Thu, 7 Nov 2024 15:05:28 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.831923.1247310 (Exim 4.92) (envelope-from ) id 1t944W-0007em-4G; Thu, 07 Nov 2024 15:05:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 831923.1247310; Thu, 07 Nov 2024 15:05:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t944W-0007ef-1P; Thu, 07 Nov 2024 15:05:20 +0000 Received: by outflank-mailman (input) for mailman id 831923; Thu, 07 Nov 2024 15:05:18 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t944U-0007dL-Pw for xen-devel@lists.xenproject.org; Thu, 07 Nov 2024 15:05:18 +0000 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on20604.outbound.protection.outlook.com [2a01:111:f403:2418::604]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b0ee9450-9d19-11ef-99a3-01e77a169b0f; Thu, 07 Nov 2024 16:05:15 +0100 (CET) Received: from SJ0PR13CA0045.namprd13.prod.outlook.com (2603:10b6:a03:2c2::20) by IA0PR12MB8280.namprd12.prod.outlook.com (2603:10b6:208:3df::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.19; Thu, 7 Nov 2024 15:05:09 +0000 Received: from SJ1PEPF00002318.namprd03.prod.outlook.com (2603:10b6:a03:2c2:cafe::3a) by SJ0PR13CA0045.outlook.office365.com (2603:10b6:a03:2c2::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.14 via Frontend Transport; Thu, 7 Nov 2024 15:05:08 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF00002318.mail.protection.outlook.com (10.167.242.228) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.17 via Frontend Transport; Thu, 7 Nov 2024 15:05:07 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 7 Nov 2024 09:05:07 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 7 Nov 2024 09:05:05 -0600 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 7 Nov 2024 09:05:04 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b0ee9450-9d19-11ef-99a3-01e77a169b0f X-Custom-Connection: eyJyZW1vdGVpcCI6IjJhMDE6MTExOmY0MDM6MjQxODo6NjA0IiwiaGVsbyI6Ik5BTTEyLUJOOC1vYmUub3V0Ym91bmQucHJvdGVjdGlvbi5vdXRsb29rLmNvbSJ9 X-Custom-Transaction: eyJpZCI6ImIwZWU5NDUwLTlkMTktMTFlZi05OWEzLTAxZTc3YTE2OWIwZiIsInRzIjoxNzMwOTkxOTE1LjAzNTEyNSwic2VuZGVyIjoiYXlhbi5rdW1hci5oYWxkZXJAYW1kLmNvbSIsInJlY2lwaWVudCI6Inhlbi1kZXZlbEBsaXN0cy54ZW5wcm9qZWN0Lm9yZyJ9 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=zG2HohGWpSyX4aVaue0OBpr1WDIw/uAtr6OONtLnR2YOzY6pKAMJIIUA2PW9cig/7zoijKVG2Saf3AwOmXrhWSFwE8bOfJZXPP/aB1X0Bx0AVzowyC9yt1RNchnfXkkAxtr40Uu3aW0AevMCx/wAV5vBHMKaZPCZymyjHeZhTZqyoggvovK9dxo+y7GmQAfFnzk5lZiPgGirc4rjQ1CN/ja1AkAkPY7g429D/ZRdM4yFqTPVgagqVU4jeM0av6oHRksnnuttxQ5TwaMtk5o3xnwkKSrSXqEC6eSWLiH7aArGosE3h32TzxmqZ7UUqqwUy8611143jMmOYuLjdZtqvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iC2GdZCuxuVwaZw2qvbMt7m8oDLf7Amskjm7zxYii5I=; b=QvakQ16TsKOmj15y9eNAU1yDysl6F+NBwIMngJTu+7F97ZBBP7tgwFhs5qIG8f5FGa4cYurkWZ2WiYrJrn91MUaitSozVNO0Qh7w8Lcz9tfqR3liyv2bt1hPGyZuSh4ImDbeSYquHZgo9yZn3rFiTHSr+JsiTIqONOIsb4Potg90ipkTHi4Ae8gNU7BLexHYLx/sOmbQgRucNFlhbpPUQ6n+HgHsgYXcRiJ7c9QuKkuByBVp+mWPDLMP4pf+p9yUNVu/ka4UwslIyOxTF9KMY/dwmUzeky+vVcJKvBzBXKl7bmaW4w10AZ1+G+fZzQaCR9r8MIbvLVr8ceymRAZ1gw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iC2GdZCuxuVwaZw2qvbMt7m8oDLf7Amskjm7zxYii5I=; b=H8dBc+BTvfW6v30lhc4wL1FDq17zA90QxbyH5wd8nsK/5ORtvI+OdAsuNoWQWFDjHvDda4Y7/kcK70d9Gr3xSYjgzYaZSsXnpfda1r8CcDHhaH9klJdAfgqQamnLH/HZmZIDneCqilnj9VT1VcX9fImIjQ5ZvaaIhnvtSGpt+Ls= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Luca Fancellu , Julien Grall Subject: [PATCH v5 2/3] xen/arm: mpu: Enable MPU Date: Thu, 7 Nov 2024 15:03:29 +0000 Message-ID: <20241107150330.181143-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241107150330.181143-1-ayan.kumar.halder@amd.com> References: <20241107150330.181143-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|IA0PR12MB8280:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e5faa20-b652-4a31-38ec-08dcff3d91a9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: Zu/P9rrT3uaYyihTHUBa+Db5CkACcB50pI8NiZ/mOMMsFnzi7wCzm3p34BJgrxZ+s8H8O7Twak3WpO0EsgagYR0En2viUq/M0Vpuj/gn1rsVBsizWSV/a3PpRyHwMM1sPvdDK16q4B1l8CeVe7MP9ecM10dUxC5mXmxHi3ut41aa9KibHdcWGwjG/Rn5z/kahoPXKdynjXpJlsDcTyXGiv0lH+SNBC1mCwhAF/Tcp4qM5KapM55AHVbBgYk7PwP1BzONeJrFGoMMSN5Os/779wJ75kbNTnQ9cBFcWhDrthp2fdBAnofiQhppBYtDTVJZRQpv+S08CJpLb/RL+RN1DVpTmv0Sb6jAdzgfGRT7tFA687mKpAso7XbFytE0S7SJ0dfOuxAusy4cZiaDGakdPwtCKoqUxGAWoFFyxoyz0n3jZN7xxhKidAe3roGfXEfWH65P2uTv71VDlHb8d4CLqfHaIswwZrMY38PPHpqYJr/AvJVv9h/b4iLFja8chIZSkjDHzB8gKdkU1H3ff61EvDfl8oCxXee5Hbaklz7vecKFv7uqTp7G2/3hSovZ/eVeAkGwjgnr5UFnVt2v9ZWDEFpXru5T5PNFLcjXCM14qzgZhxUFvjNmQfCn7RG6w3WkgHDneh93oNIESVvnNs/OhuZMTr+6fQ/4RPvDYnZjKESOdHnMztBFbvly2dUrFiLKyohull6zLsMGTsPnH5iBTqnWCBgUqy2HYlGsco/FPUviw8beb1z15PuNQHn8T54D2Nz4EyDlEmhLVoG592PpxSWkLxGB46gh743Cnw4TMaEdu6bIyCh/R1xeZ3V2yxmWMC3lCPUlIwwKxxOBBeY5VVGTkWm5lCy9/1HIvmAGxi0fJ0j2yeX4atxA/fMCxtI0LGKaUkQofiZOALyeBwP6TXpysXakQALzOUxBsNETfDAUf8sY0XCh7fgMfy0fLncOf20ieX4PIM5MMwWjUBANH9w4Mv7GhzVZPK5r+58mwRrGnEQ2uO/zBqX0l+8g5jG4JEM+7U07VuXrUt144km5o4F7ytBCZ2LrySQpiREjN/j8deYH2A/lV+S0pwNJRsIN/73qKSfurXdIdJOfHUgBkcgeJDBA6SXgYLR5IcPu34PGl2eFTUkxQR8NMSAFJXz9rq4UnuKBDjwOQE268qHo64F7xTIZDSd/PJSq3WhykEAbnIkgbgAPtWnXYTuk6IZBrR4/BpyR4wOezAAyXgZ+L5j5QMW9oWiS0RnHOz1jrDPTQX61JtiwVbgZg2MkUrZeOywUKr4RFBFHZpH7skerbYvLGKSLPLvxqsTwYJI4lIs3QKSC34cljzn1SBP7T0nm52YJuv3pf6gi7m8w5VmTgJ9Njq/25Qh1q4ZWgYL4N4/LJPXR0dnDm0TqEan4SZRqphOtaHxy0rwdOAp8r5QQ4Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 15:05:07.9923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e5faa20-b652-4a31-38ec-08dcff3d91a9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8280 After the regions have been created, now we enable the MPU. For this we disable the background region so that the new memory map created for the regions take effect. Also, we treat all RW regions as non executable and the data cache is enabled. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu Acked-by: Julien Grall --- Changes from :- v2 - 1. Extracted from the previous patch into a new one. 2. Disabled background region. v3 - 1. Removed dsb before setting SCTLR_EL2. The reason being From ARM DDI 0487K.a D23-7349: "Direct writes to these registers (includes SCTLR_EL2) are not allowed to affect any instructions appearing in program order before the direct write." So, we don't need a synchronization barrier before writing to SCTLR_EL2. Further, we do have synchronization barriers after writing the MPU region registers (which happens before we read SCTLR_EL2). So, SCTLR_EL2 is written after the MPU registers are synchronized. And, thus adding a 'isb' to flush the instruction pipeline ensures that the subsequent instructions are fetched after the MPU has been enabled. 2. Saved and restored lr in enable_boot_cpu_mm(). v4 - 1. Moved the definition of SCTLR_ELx_BR from sysregs.h from head.S. The reason being sysregs.h does not exist any longer (refer to previous patch for details) and SCTLR_ELx_BR is used in head.S only. (I have preserved the R-b abd A-b, let me know if that is ok). xen/arch/arm/arm64/mpu/head.S | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 37e4b455bb..a449aeca67 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -5,6 +5,9 @@ #include +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + #define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ #define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ #define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ @@ -69,6 +72,29 @@ FUNC_LOCAL(fail_insufficient_regions) b 1b END(fail_insufficient_regions) +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch64 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + mrs x0, SCTLR_EL2 + bic x0, x0, #SCTLR_ELx_BR /* Disable Background region */ + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + orr x0, x0, #SCTLR_Axx_ELx_WXN /* Enable WXN */ + msr SCTLR_EL2, x0 + isb + + ret +END(enable_mpu) + /* * Maps the various sections of Xen (described in xen.lds.S) as different MPU * regions. @@ -111,6 +137,7 @@ FUNC(enable_boot_cpu_mm) ldr x2, =__bss_end prepare_xen_region x0, x1, x2, x3, x4, x5 + b enable_mpu ret END(enable_boot_cpu_mm) From patchwork Thu Nov 7 15:03:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13866616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D231D4336D for ; Thu, 7 Nov 2024 15:05:27 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.831924.1247316 (Exim 4.92) (envelope-from ) id 1t944W-0007hh-F1; Thu, 07 Nov 2024 15:05:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 831924.1247316; Thu, 07 Nov 2024 15:05:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t944W-0007gz-99; Thu, 07 Nov 2024 15:05:20 +0000 Received: by outflank-mailman (input) for mailman id 831924; Thu, 07 Nov 2024 15:05:19 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1t944V-0007O4-0w for xen-devel@lists.xenproject.org; Thu, 07 Nov 2024 15:05:19 +0000 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on20611.outbound.protection.outlook.com [2a01:111:f403:2406::611]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b0e37569-9d19-11ef-a0c6-8be0dac302b0; Thu, 07 Nov 2024 16:05:15 +0100 (CET) Received: from BN9PR03CA0349.namprd03.prod.outlook.com (2603:10b6:408:f6::24) by IA1PR12MB7589.namprd12.prod.outlook.com (2603:10b6:208:42b::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.30; Thu, 7 Nov 2024 15:05:10 +0000 Received: from BN2PEPF00004FBF.namprd04.prod.outlook.com (2603:10b6:408:f6:cafe::d2) by BN9PR03CA0349.outlook.office365.com (2603:10b6:408:f6::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.18 via Frontend Transport; Thu, 7 Nov 2024 15:05:10 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF00004FBF.mail.protection.outlook.com (10.167.243.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.17 via Frontend Transport; Thu, 7 Nov 2024 15:05:09 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 7 Nov 2024 09:05:09 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 7 Nov 2024 09:05:08 -0600 Received: from xcbayankuma40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 7 Nov 2024 09:05:07 -0600 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b0e37569-9d19-11ef-a0c6-8be0dac302b0 X-Custom-Connection: eyJyZW1vdGVpcCI6IjJhMDE6MTExOmY0MDM6MjQwNjo6NjExIiwiaGVsbyI6Ik5BTTAyLVNOMS1vYmUub3V0Ym91bmQucHJvdGVjdGlvbi5vdXRsb29rLmNvbSJ9 X-Custom-Transaction: eyJpZCI6ImIwZTM3NTY5LTlkMTktMTFlZi1hMGM2LThiZTBkYWMzMDJiMCIsInRzIjoxNzMwOTkxOTE1LjA1OTA1OSwic2VuZGVyIjoiYXlhbi5rdW1hci5oYWxkZXJAYW1kLmNvbSIsInJlY2lwaWVudCI6Inhlbi1kZXZlbEBsaXN0cy54ZW5wcm9qZWN0Lm9yZyJ9 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yDVjq3XWmm4foMccpqq1euTtZGCuRZk8EwDrqk793MnTgH/Q0TS8KviT+EEr2xk3VRnreo4vpumIxg1+V8mqhGBrk0QPrjMYfc4v9rv+gC/MJkXPd79D1dwNdSf/A+4cg5k5fWG8xXMahgwsa3YULEonWCovYwGLAzh7zcLdwwErQwp9PHjzQValhQL55gZsbMZRhBUgFm9sx0JZY+KytzHGyxGOOaRVGkXYY+dbL62i9rS0FNAc35UYbHi1R3/cOM7UMvBUqRATM+0wL+fuVDZe/fVNrJwGIUnPJs57L8DoJ0KIKlY7gTQSrACbSKSEe8Dv8A0VgAImcLuTcBZx0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qAQiWvLjbBtQ0a4CEJ8gt3eXVztXmRRY74/RrFG2CcQ=; b=dQUtunZGcf1cLMk5S8n4C1z3fpT2jduif1yrS3YICOlQwhhD9n1We/J0N1s2PpYOBA9l7hbLASBYxn+i7i7EpPk084jOUV50+yz87m7nEbVS33zyHEGQivXwj+CHsCkejuPO5QQv/EcW64bffwBPQWVi3FvzEDLPFiNDbzLHpB//EQJU4BRt+7sG0o5dVBzjlAIgpr8md5LiJy+iMyBIU4hdkZHXTR9v+pC31eG4A8J5P1phaU11t862ni1mUUcjh0k+ZtGEBm36UU1AjmUJeueQumwTY1lDFb96lUVDk7+VdvsJMX/RsBsax81Nnr/l0okGjzLG72CazwquP5LyOg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qAQiWvLjbBtQ0a4CEJ8gt3eXVztXmRRY74/RrFG2CcQ=; b=FPS30SLMDy9Tq9FitBYKUfPo2gBhbc5Blt8WFBXJ8A7hFG8Ua0a5QhmBOYqlLwl+FQ7tApvHRkXaBeNZQzL2z//Fnuuss2RA4p8nBxj0XHf8B7TRkGPVQWDWN2NfkABjgoJbm/cSCd0K1QuBNztvY6+pZQ8PJa2x1vazvtvgIyE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk , Luca Fancellu Subject: [PATCH v5 3/3] xen/arm: mpu: Implement a dummy enable_secondary_cpu_mm Date: Thu, 7 Nov 2024 15:03:30 +0000 Message-ID: <20241107150330.181143-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241107150330.181143-1-ayan.kumar.halder@amd.com> References: <20241107150330.181143-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBF:EE_|IA1PR12MB7589:EE_ X-MS-Office365-Filtering-Correlation-Id: 13e614b9-e260-4641-f8f0-08dcff3d92aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?l/M0TEy7ZZiQ1rZ46O9fBjHfhFBpAtC?= =?utf-8?q?+XHIXyYOWQr6YcaJZ+MMwtNCRJk6VB2Tw2z2QFDHzlHEWgBSlvhXbXw+uSrCjfInT?= =?utf-8?q?B25eRUQBGcaVb3HTHnbAf1x6d2LJJYLk6R0EkufBV+9iV5yQcozEHGixAwEnsghQC?= =?utf-8?q?8rJp8Skvo7YtnoEFpzTXoXznkKke9TTm7dtgol3oxjytoj5L0a693j5K6Siu0Lg3X?= =?utf-8?q?fof8sN11OpCE9kZ6zrkPpP6giRGDR4aVLR4XMRz+uGTTpisayw0jTRK8tZgrNbJis?= =?utf-8?q?nDtd7qVnx9kSPyKDKlk3gFZdHd+tViob57UQA0NjuWT0+yIE9vGCN9VJ0yx7ESAXo?= =?utf-8?q?rIrGI99PIPp12bztyCph6hnTb6XnT7T4++BeGruspwkWILzCE03CN3lHm4wwX5FO3?= =?utf-8?q?xxInJ009z3RIQm9R19tapsx7V85DGPCHBLcDFP+WvDePOanZeA+F/4p1InRuyiIFx?= =?utf-8?q?P6PBrFsz4LzHw8bKMayVMXkjF0Q+IY82TGfXEPcC8l+iFqrFzuG5+qe3BZVenzNh9?= =?utf-8?q?d+zDZFwQ5yJvO5SItsxUMjmSNfFSO2U4FuaxdLCFqVqv/8IhFaYjtb57x+d8FCDkM?= =?utf-8?q?N3wxBHB6T6prRMlAUf8AJ6ixL+oQ34UvH8tTUxNwFDcJikMcLDxK8cLBbIRoL+4jU?= =?utf-8?q?cA/hNhqXLO2U7pjpIw2vliGomYL0yFS8Yn/ANysWvZt7Wos10n5HFB2peU9ugCi2U?= =?utf-8?q?XYg7jvWbGN0EybYJgwDhrKPG1bkRCHeuSjRXVkkmxoLQ/p7VvGYWBskqG+qmSOm+f?= =?utf-8?q?G/J427qMnOCPxyUHmhbmT0RFvIn59maMAl030rh19P4jp/d/FLtR/k5XjDFTix9HM?= =?utf-8?q?HDE3oL0GwW/vVbSU0E3tZwFJrRxPAESgdSPhCTRUnvHcIf+jdX+CbIBgP+wXNJTVH?= =?utf-8?q?Hq24J3q1kKgAghR4EiKIlhW5Fi8ue71H2HqVUtQkGneKlqmokMe0O5K1tdgBJ7G5j?= =?utf-8?q?olmQ0jqDpOKILGMkCdUogeRh932DfFuP0Ui/CjqpmamNkEtKZtPFsb9RfPTz9IBVJ?= =?utf-8?q?eo3e9ARVKq28Ffd3bj0jdPREdahj/jjE2qF0P/u/VwgRVZTYpz4AXi5deeMs3aTdv?= =?utf-8?q?D34hMh//ilJhYQJ/SS2hqcRhm0gop0GXpjyRY/PCNg61y7zr+cemfT9N8vWmjYUiX?= =?utf-8?q?Q0wAbwPbZyaP9psQCNdEdHhC2cZkNxNSKDtaAA7MC8OMTTEx0Zlemmfvpqsi8fR8w?= =?utf-8?q?fQj5L4z2bPQs23N8SHddGB3FaHv+VVqISUKk6RBXKoH3UXb8P2XOSk8qQIQhu/9OS?= =?utf-8?q?VZrCLB+SdXV4Oab+NGi8E40CiEFhdSaLAGJ1nvF4fB4MocXWvbaM+O02xWp1+MGa0?= =?utf-8?q?ZG5xbGxqo91ymJ1XgOv+y2DFUVOQ15QbCg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 15:05:09.7752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13e614b9-e260-4641-f8f0-08dcff3d92aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7589 Secondary cpus initialization is not yet supported. Thus, we print an appropriate message and put the secondary cpus in WFE state. And we introduce to BUILD_BUG_ON to prevent users using from building Xen on multiprocessor based MPU systems. In Arm, there is no clean way to disable SMP. As of now, we wish to support MPU on UNP only. So, we have defined the default range of NR_CPUs to be 1 for MPU. Signed-off-by: Ayan Kumar Halder Reviewed-by: Luca Fancellu --- Changes from :- v1 - 1. NR_CPUS is defined as 1 for MPU 2. Added a message in enable_secondary_cpu_mm() v2 - 1. Added the range 2. Clarified in the commit message why/how we have disabled SMP. v3 - 1. BUILD_BUG_ON() is moved to smp.c. v4 - 1. Moved "default "1" if ARM && MPU” right after “default "256" if X86”. xen/arch/Kconfig | 2 ++ xen/arch/arm/arm64/mpu/head.S | 10 ++++++++++ xen/arch/arm/smp.c | 11 +++++++++++ 3 files changed, 23 insertions(+) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 308ce129a8..9f4835e37f 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -6,8 +6,10 @@ config PHYS_ADDR_T_32 config NR_CPUS int "Maximum number of CPUs" + range 1 1 if ARM && MPU range 1 16383 default "256" if X86 + default "1" if ARM && MPU default "8" if ARM && RCAR3 default "4" if ARM && QEMU default "4" if ARM && MPSOC diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index a449aeca67..731698aa3b 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -141,6 +141,16 @@ FUNC(enable_boot_cpu_mm) ret END(enable_boot_cpu_mm) +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +ENTRY(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index c11bba93ad..b372472188 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -6,6 +7,16 @@ #include #include +static void __init __maybe_unused build_assertions(void) +{ +#ifdef CONFIG_MPU + /* + * Currently, SMP is not enabled on MPU based systems. + */ + BUILD_BUG_ON(NR_CPUS > 1); +#endif +} + void arch_flush_tlb_mask(const cpumask_t *mask) { /* No need to IPI other processors on ARM, the processor takes care of it. */