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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Chiara Meiohas , Mark Bloch , Tariq Toukan Subject: [PATCH net 1/7] net/mlx5: E-switch, unload IB representors when unloading ETH representors Date: Thu, 7 Nov 2024 20:35:21 +0200 Message-ID: <20241107183527.676877-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107183527.676877-1-tariqt@nvidia.com> References: <20241107183527.676877-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|SN7PR12MB6813:EE_ X-MS-Office365-Filtering-Correlation-Id: 3544c244-4955-4bd8-0bdf-08dcff5b17be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: W+Lncn8pXmINL9t4KPiznPY124g30ert5V/WT/SdsBaNvSG8cFJgDEPM5TQ/Q6UDQNJtor1/yjzfZtwwvlTU2xPFcAT9s0DX3Q66VT1hCOWBEl4J5GfoJQ6LMUBnVQ3Z1gBkVxdBJC5rCxBOarPkAxJeDL6XyL1odhpqH41Sakrjib9tI7jQ45SJfJIDpnTloOhpRFtzsQfu1nSjnSNHjceC/JSrIs/7WjpjmLCjpRKXkYOSLwz/9Vd5JORekegQytC2321T9fgu66K28uoHmuW4VV52KGHahNKfoTW4AcLKoy/mJW5OUFYvxMReunkLBSHjl9flyxHNBil6RGrHWSmahgxqrlharisgvD0jFccBq8cDkmHtSaTdmJ12vVUDnWJX4akvf7R8hFllLNAjtVDCoC21HSoaOwFHyrA2K38l/h1IiWweNUNrXJL6krp2Vm53xfnGj1x11stqkL6ZRUNU5rKlEe4UxttiSEthrvKddbLiiOHiAnT5vtXoJ+wgBdOD5uzUu6pE53mCvqvPzTnJqpOU/GnFAHYSWDrhl1dkwsYUikWHTOrMhDfmn7W0LBGBmn5twltMgjIFsfmKqVxQBurCWyYn80wPkWYQNtNBqV2oc5YX0ORVw4l25CmVUPW+0Nrd51XL7m6r13JVxcxVNzknAwi+butJaJRJmhF9Shq0NaRJOsJ8WzMbti8WfupFMC/jlHwI90H0KfPO2sbO1DM+R2eLOsU9sxTqX97tgpT/1aJ9wl5CiUVTmgJurIPaPIwvVOGmXX22L2qyoHn/5GSM3KYGtwsUCbWawHXsp/sqrJ4+vJlz45EQilgndgVQuIg/KdVR3DSsvtlW2Fex3CTPRp5/ABRo6SltyGzAoF9gP0M8YGmRwO9iA/WRh9lieFjqKTy2wx3lMuq12nkldcs0rOIHoAUIBW736MK4DMQtDJT8ieyYR/Q13irxrnVkQJPBcWmom/8hdpla9kSyPnP8GzlLp8NMHoXFKhUAN34i3CmrlMdUP/KJeZIJCiglP3sDx4lxxPAi9sqEOGdKZ0Lk2WyEJZM1yit2whw/jl0iv0BDenFzPYsNoPmqDTHFYPYWtH4uAp9+njkxFyFkbOR87/A8vhm/u5ENeNLBoGkUtMM4pzJ35sC/6oinuYu7l9v+mO6vZv0GQQyKn6xx0mMoffljH5P53rlbFAULWIqm0SPBuBgItsjuNarKBuzsWg9QS3xLI6oPyzB8XnjUafeh5+agLUkCy+lPLzsC6dRnj9+5CQLgu9FFB79FCM9zpEr0YK4oUjHF9yarGqS5wI58uugfJkUNZpnO05VTj7p8ucjApAkpK2WthYFq415MxpN9quPBDfc4pRhEqUV2K5J3fSmrW5DDZK9oWcdMgGqAxMy0UNEA+Sug0T5oJjzgm5XvCrn3Om3K1rM42w== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 18:36:28.4267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3544c244-4955-4bd8-0bdf-08dcff5b17be X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6813 X-Patchwork-Delegate: kuba@kernel.org From: Chiara Meiohas IB representors depend on ETH representors, so the IB representors should not exist without the ETH ones. When unloading the ETH representors, the corresponding IB representors should be also unloaded. The commit 8d159eb2117b ("RDMA/mlx5: Use IB set_netdev and get_netdev functions") introduced the use of the ib_device_set_netdev API in IB repsresentors. ib_device_set_netdev() increments the refcount of the representor's netdev when loading an IB representor and decrements it when unloading. Without the unloading of the IB representor, the refcount of the representor's netdev remains greater than 0, preventing it from being unregistered. The patch uncovered an underlying bug where the eth representor is unloaded, without unloading the IB representor. This issue happened when using multiport E-switch and rebooting, causing the shutdown to hang when unloading the ETH representor because the refcount of the representor's netdevice was greater than 0. Call trace: unregister_netdevice: waiting for eth3 to become free. Usage count = 2 ref_tracker: eth%d@00000000661d60f7 has 1/1 users at ib_device_set_netdev+0x160/0x2d0 [ib_core] mlx5_ib_vport_rep_load+0x104/0x3f0 [mlx5_ib] mlx5_eswitch_reload_ib_reps+0xfc/0x110 [mlx5_core] mlx5_mpesw_work+0x236/0x330 [mlx5_core] process_one_work+0x169/0x320 worker_thread+0x288/0x3a0 kthread+0xb8/0xe0 ret_from_fork+0x2d/0x50 ret_from_fork_asm+0x11/0x20 Fixes: 8d159eb2117b ("RDMA/mlx5: Use IB set_netdev and get_netdev functions") Signed-off-by: Chiara Meiohas Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index f24f91d213f2..8cf61ae8b89d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -2527,8 +2527,11 @@ static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep, u8 rep_type) { if (atomic_cmpxchg(&rep->rep_data[rep_type].state, - REP_LOADED, REP_REGISTERED) == REP_LOADED) + REP_LOADED, REP_REGISTERED) == REP_LOADED) { + if (rep_type == REP_ETH) + __esw_offloads_unload_rep(esw, rep, REP_IB); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Parav Pandit , Amir Tzin , Tariq Toukan Subject: [PATCH net 2/7] net/mlx5: Fix msix vectors to respect platform limit Date: Thu, 7 Nov 2024 20:35:22 +0200 Message-ID: <20241107183527.676877-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107183527.676877-1-tariqt@nvidia.com> References: <20241107183527.676877-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE5:EE_|SN7PR12MB7936:EE_ X-MS-Office365-Filtering-Correlation-Id: f800106a-3933-4d9d-2623-08dcff5b1c6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: XVcpyPiDSS85TZRxTnPcmeNXkcK94rgBtjtk3394aJ8WP6P+FCOz35lKN8HmVVQZkznjETVbJSL06qBYeDv2vtECQ0CBN0kHtMSxJdVVmvsP5kQi+cMimSN23hQRBTS/1rOkW+icA6d3aZzAJ2U/9oV0dIIdNXa3P8CQ470RNxKY3bbTsRXvMYJV3E8k79Hp67TbCc6Pxgdxaqk+E6iHdbZtAereaWwz+NOM67CczOPA6YQhIuUxp5oPSQ9RjXKm1jsMlm2zCB03Af0XH33yXxGNVIXFr7XER1Z8GlMafyvzQ5g6FOvlaWgdCqs6DyVFCJKaUicuAzrCNjP6pRxCLsI0Eq1+RDkoFiHuz1GWqL7uPYsqXk9vwJgjCX9Qf2rZai1gmC6I7VOqTTBoy0SBo7RzVnzDTSpQYBzfvbd2j9Mp3ufPzVBcqK7fOxsPTPCs/bJ+EqxGXoFAaLscGupy0m+4Q84zEvNCqkSeMhqfMT1zaeekynSuwhQuh2Ikg8saH+ujyOtaGI7Xu0H71Z1ZUP8v31V47eRfQqTQo7Txi05re6Fu/vUvBES5lXZ0I9vcYIBx73/6x5rFpTnx3jkVOzD9BQjTTKXSZFH+HYEg+JL+2NkxrQ2gOZ03GjNy/mTxtRF+2Q2YLM/zdIoJbWYCVd5iZDRcT+NlZ24wfcm9KgsB+V9aaXwU3wW0F/0ZRXw0KFUJTKExIvFovPAbz+wzM9NgW1sHOJyzduVbjUH/GND5AIQMFnnm+HwNUa3XbTWJB8L5nREEjwz60mhWDnd9/un3LIDPhKO6pRnsgcABgsHWcidhkSh3ja/xYgeqqWNJJ7vvD5ipI51mFuPJZaBGd/2ksKy72MI+zpPGf39MJIa3sXyItZ/ZWqGJYq29nFV03e/kheLcI4UPR6Ri9OaPUzKWLWGoYesKtNsLyuMDX4xb5a/gNdoer0UUowWIi92lHlW+voCTzHzZeTI2HnzTfYqMTKSGpAPMj3IFOPuSoU0SsSYC42sYAaoUGgeWXJYnm1Feru+JViIwv3zhwkcBew6Ih14b+RvW95PINLXX5vdkq9DCVGJ5FSSLVJU4MozVFlJ/d7x6Y7R7jQhLkIIY70yQjB7QCp3WHNXv96dH4PJ5+IDzRF27O0oLzGpnTl3y4NUdRhcis8zZJeGTPpqa1WLsDEfwyXAQ+xVZHIb+6BE///tFfBGTl/+6EIJsISlh5Bu/qI20S93BY/ydGM0CFNSYDr1lnYDhgt6wzm8ciSa7J5AnvYI9RLTqam5O/95kzp/tL/PVN8L5Hh4b/ZwARP2SZFpQtNheHV3KTgouTt/EYiApag8ATDafTNDXrQKiq/+Qq3Z+YWFa+a0cvDbWCUZUNwWij0qO2p33My8shwgnYsA4BFpkNPsq2GAfMc4UDlN0V/zJOkSeOvP+AHjwSQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 18:36:36.2721 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f800106a-3933-4d9d-2623-08dcff5b1c6b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7936 X-Patchwork-Delegate: kuba@kernel.org From: Parav Pandit The number of PCI vectors allocated by the platform (which may be fewer than requested) is currently not honored when creating the SF pool; only the PCI MSI-X capability is considered. As a result, when a platform allocates fewer vectors (in non-dynamic mode) than requested, the PF and SF pools end up with an invalid vector range. This causes incorrect SF vector accounting, which leads to the following call trace when an invalid IRQ vector is allocated. This issue is resolved by ensuring that the platform's vector limit is respected for both the SF and PF pools. Workqueue: mlx5_vhca_event0 mlx5_sf_dev_add_active_work [mlx5_core] RIP: 0010:pci_irq_vector+0x23/0x80 RSP: 0018:ffffabd5cebd7248 EFLAGS: 00010246 RAX: ffff980880e7f308 RBX: ffff9808932fb880 RCX: 0000000000000001 RDX: 00000000000001ff RSI: 0000000000000200 RDI: ffff980880e7f308 RBP: 0000000000000200 R08: 0000000000000010 R09: ffff97a9116f0860 R10: 0000000000000002 R11: 0000000000000228 R12: ffff980897cd0160 R13: 0000000000000000 R14: ffff97a920fec0c0 R15: ffffabd5cebd72d0 FS: 0000000000000000(0000) GS:ffff97c7ff9c0000(0000) knlGS:0000000000000000 ? rescuer_thread+0x350/0x350 kthread+0x11b/0x140 ? __kthread_bind_mask+0x60/0x60 ret_from_fork+0x22/0x30 mlx5_core 0000:a1:00.0: mlx5_irq_alloc:321:(pid 6781): Failed to request irq. err = -22 mlx5_core 0000:a1:00.0: mlx5_irq_alloc:321:(pid 6781): Failed to request irq. err = -22 mlx5_core.sf mlx5_core.sf.6: MLX5E: StrdRq(1) RqSz(8) StrdSz(2048) RxCqeCmprss(0 enhanced) mlx5_core.sf mlx5_core.sf.7: firmware version: 32.43.356 mlx5_core.sf mlx5_core.sf.6 enpa1s0f0s4: renamed from eth0 mlx5_core.sf mlx5_core.sf.7: Rate limit: 127 rates are supported, range: 0Mbps to 195312Mbps mlx5_core 0000:a1:00.0: mlx5_irq_alloc:321:(pid 6781): Failed to request irq. err = -22 mlx5_core 0000:a1:00.0: mlx5_irq_alloc:321:(pid 6781): Failed to request irq. err = -22 mlx5_core 0000:a1:00.0: mlx5_irq_alloc:321:(pid 6781): Failed to request irq. err = -22 Fixes: 3354822cde5a ("net/mlx5: Use dynamic msix vectors allocation") Signed-off-by: Parav Pandit Signed-off-by: Amir Tzin Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 32 ++++++++++++++++--- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index 81a9232a03e1..7db9cab9bedf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -593,9 +593,11 @@ static void irq_pool_free(struct mlx5_irq_pool *pool) kvfree(pool); } -static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec) +static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec, + bool dynamic_vec) { struct mlx5_irq_table *table = dev->priv.irq_table; + int sf_vec_available = sf_vec; int num_sf_ctrl; int err; @@ -616,6 +618,13 @@ static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec) num_sf_ctrl = DIV_ROUND_UP(mlx5_sf_max_functions(dev), MLX5_SFS_PER_CTRL_IRQ); num_sf_ctrl = min_t(int, MLX5_IRQ_CTRL_SF_MAX, num_sf_ctrl); + if (!dynamic_vec && (num_sf_ctrl + 1) > sf_vec_available) { + mlx5_core_dbg(dev, + "Not enough IRQs for SFs control and completion pool, required=%d avail=%d\n", + num_sf_ctrl + 1, sf_vec_available); + return 0; + } + table->sf_ctrl_pool = irq_pool_alloc(dev, pcif_vec, num_sf_ctrl, "mlx5_sf_ctrl", MLX5_EQ_SHARE_IRQ_MIN_CTRL, @@ -624,9 +633,11 @@ static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec) err = PTR_ERR(table->sf_ctrl_pool); goto err_pf; } - /* init sf_comp_pool */ + sf_vec_available -= num_sf_ctrl; + + /* init sf_comp_pool, remaining vectors are for the SF completions */ table->sf_comp_pool = irq_pool_alloc(dev, pcif_vec + num_sf_ctrl, - sf_vec - num_sf_ctrl, "mlx5_sf_comp", + sf_vec_available, "mlx5_sf_comp", MLX5_EQ_SHARE_IRQ_MIN_COMP, MLX5_EQ_SHARE_IRQ_MAX_COMP); if (IS_ERR(table->sf_comp_pool)) { @@ -715,6 +726,7 @@ int mlx5_irq_table_get_num_comp(struct mlx5_irq_table *table) int mlx5_irq_table_create(struct mlx5_core_dev *dev) { int num_eqs = mlx5_max_eq_cap_get(dev); + bool dynamic_vec; int total_vec; int pcif_vec; int req_vec; @@ -724,21 +736,31 @@ int mlx5_irq_table_create(struct mlx5_core_dev *dev) if (mlx5_core_is_sf(dev)) return 0; + /* PCI PF vectors usage is limited by online cpus, device EQs and + * PCI MSI-X capability. + */ pcif_vec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + 1; pcif_vec = min_t(int, pcif_vec, num_eqs); + pcif_vec = min_t(int, pcif_vec, pci_msix_vec_count(dev->pdev)); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Maor Gottlieb , Tariq Toukan Subject: [PATCH net 3/7] net/mlx5: fs, lock FTE when checking if active Date: Thu, 7 Nov 2024 20:35:23 +0200 Message-ID: <20241107183527.676877-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107183527.676877-1-tariqt@nvidia.com> References: <20241107183527.676877-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|SA1PR12MB8947:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d81dc64-6e94-4966-2406-08dcff5b1ac0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: z1ff4nSmEXiznjqgVOPZd/LKGGHNI8XuIKxWShqVI9kyhZMN8HXzfPswZbGeM8Myezi1sFKQ4FX4ucSW3R3y7q1JIKxCsokljbqo8nT/jng/dOTugoVy+zSVvizXiDuZ4nvabD5WxHfhabrqp6MmfB3ELiTEgMlAtp5KUKLcwJPCKg5a70IiMZro1om8gq6s3R8zX/ZkTiJK+zhMYDO+6T2lpgg5+3XrD6VohkVzE1e5iCkg/rJvcQjGzAsDSUXXgn8SVb4vyANCADymoSFLgP69AJKCNbh0lfo9yRkvVUatYWONdUvv0j3A75LKW57IsIt+uMnhn77WB8pkj4O3oBISSGtrsus8tgfGPU9mEZnrED+AX5N622J2yHp/C4MSvLfZZmD1eBzLiMoy80Z+DI1jhXHkjMn6n5qizSGvTILcOxieVgRiq5ogEQwiI88AxudLVX/9jyEPw00aL8ioUKU1+wVdbRYRd0E2jIGtA825msFLEqgaG+4BHxJd9UEi3Nd4R7NXOsNhak1g4gHro5NGspyMF2359Oftn7RVzLT4sVlyt0hZgRi0aS0IDtsErtNcDbeyXPq09JQf80Un5n5vDhNaB88Oo+s4++EAejMwUARv+IjIWB0BZqrqwCBErsY6/WNHrnSZR2nTuPhtsjZsbIcDAagrYfYSEPTd9/ezQ1I54gjji3g18ZJR1C9CBYaxZUBiVgzOfoPP7ZOuH8C32/mBhYkZvRnXQSis06ytI07DJWu4lEIwOIzayNPU0CU8wRrIOt++pUJDFZQKRKSQZxe8vTiHa+skJBVtyAK9q0pVF6hKusTugZlEiSmTTP0RbZtCvLC/8E0QNL0ZGZmIuKhiK+Eoc+zzjvK4b/gmAQ+vto+xxlMQITBRfMMfg+5+b9zNNu5BbrgvV7AI98nIy+fAIIrqKD5CMCcLB/lfe0uahewftvI5erVcOoUqzeamSDI5o2YfH1yQxb5SnQhfH7r2n4+75ggM1zgKORjcm1JjNOlYyehMHAhimYV5wx3W+V+C9nJT/+NEMnZgHJ2RQyp6whoeM6VPWtPvqpUQioiPqjN5nocwmbnVIni7D6fod1UMY7YO+likzz7XFY7FTc5pJsil0bA878F2LUjRnof3oothxb6fx9SSGSjAkAsKuY44sZa0s1VzRgn7LgjVkcr6kEAM48Pc2oLaY+vdQijua9uZH9XM7tbvVP4Ootq+HZGxyj112+QJ4VixD71raVWPXgZD+XzHGr00wK9BrFSkZMWeyPOiNu9i7MuV9NmxODQYSl44keFYNVAOzZ8d1sZDl+ogoI5yDZiNu3Z7tnsZ4yzY2GTG2R+81AoYlFaqaLTq6BJSlLuE9A7vNwgOLyZ+YpU+7Mq6b0SdHrsoiuoLgJTkW2i4ZKLUoRviA+Yhwi0LcGe32TrAhn9Rhg== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 18:36:33.4736 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d81dc64-6e94-4966-2406-08dcff5b1ac0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8947 X-Patchwork-Delegate: kuba@kernel.org From: Mark Bloch The referenced commits introduced a two-step process for deleting FTEs: - Lock the FTE, delete it from hardware, set the hardware deletion function to NULL and unlock the FTE. - Lock the parent flow group, delete the software copy of the FTE, and remove it from the xarray. However, this approach encounters a race condition if a rule with the same match value is added simultaneously. In this scenario, fs_core may set the hardware deletion function to NULL prematurely, causing a panic during subsequent rule deletions. To prevent this, ensure the active flag of the FTE is checked under a lock, which will prevent the fs_core layer from attaching a new steering rule to an FTE that is in the process of deletion. [ 438.967589] MOSHE: 2496 mlx5_del_flow_rules del_hw_func [ 438.968205] ------------[ cut here ]------------ [ 438.968654] refcount_t: decrement hit 0; leaking memory. [ 438.969249] WARNING: CPU: 0 PID: 8957 at lib/refcount.c:31 refcount_warn_saturate+0xfb/0x110 [ 438.970054] Modules linked in: act_mirred cls_flower act_gact sch_ingress openvswitch nsh mlx5_vdpa vringh vhost_iotlb vdpa mlx5_ib mlx5_core xt_conntrack xt_MASQUERADE nf_conntrack_netlink nfnetlink xt_addrtype iptable_nat nf_nat br_netfilter rpcsec_gss_krb5 auth_rpcgss oid_registry overlay rpcrdma rdma_ucm ib_iser libiscsi scsi_transport_iscsi ib_umad rdma_cm ib_ipoib iw_cm ib_cm ib_uverbs ib_core zram zsmalloc fuse [last unloaded: cls_flower] [ 438.973288] CPU: 0 UID: 0 PID: 8957 Comm: tc Not tainted 6.12.0-rc1+ #8 [ 438.973888] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.13.0-0-gf21b5a4aeb02-prebuilt.qemu.org 04/01/2014 [ 438.974874] RIP: 0010:refcount_warn_saturate+0xfb/0x110 [ 438.975363] Code: 40 66 3b 82 c6 05 16 e9 4d 01 01 e8 1f 7c a0 ff 0f 0b c3 cc cc cc cc 48 c7 c7 10 66 3b 82 c6 05 fd e8 4d 01 01 e8 05 7c a0 ff <0f> 0b c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 90 [ 438.976947] RSP: 0018:ffff888124a53610 EFLAGS: 00010286 [ 438.977446] RAX: 0000000000000000 RBX: ffff888119d56de0 RCX: 0000000000000000 [ 438.978090] RDX: ffff88852c828700 RSI: ffff88852c81b3c0 RDI: ffff88852c81b3c0 [ 438.978721] RBP: ffff888120fa0e88 R08: 0000000000000000 R09: ffff888124a534b0 [ 438.979353] R10: 0000000000000001 R11: 0000000000000001 R12: ffff888119d56de0 [ 438.979979] R13: ffff888120fa0ec0 R14: ffff888120fa0ee8 R15: ffff888119d56de0 [ 438.980607] FS: 00007fe6dcc0f800(0000) GS:ffff88852c800000(0000) knlGS:0000000000000000 [ 438.983984] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 438.984544] CR2: 00000000004275e0 CR3: 0000000186982001 CR4: 0000000000372eb0 [ 438.985205] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 438.985842] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 438.986507] Call Trace: [ 438.986799] [ 438.987070] ? __warn+0x7d/0x110 [ 438.987426] ? refcount_warn_saturate+0xfb/0x110 [ 438.987877] ? report_bug+0x17d/0x190 [ 438.988261] ? prb_read_valid+0x17/0x20 [ 438.988659] ? handle_bug+0x53/0x90 [ 438.989054] ? exc_invalid_op+0x14/0x70 [ 438.989458] ? asm_exc_invalid_op+0x16/0x20 [ 438.989883] ? refcount_warn_saturate+0xfb/0x110 [ 438.990348] mlx5_del_flow_rules+0x2f7/0x340 [mlx5_core] [ 438.990932] __mlx5_eswitch_del_rule+0x49/0x170 [mlx5_core] [ 438.991519] ? mlx5_lag_is_sriov+0x3c/0x50 [mlx5_core] [ 438.992054] ? xas_load+0x9/0xb0 [ 438.992407] mlx5e_tc_rule_unoffload+0x45/0xe0 [mlx5_core] [ 438.993037] mlx5e_tc_del_fdb_flow+0x2a6/0x2e0 [mlx5_core] [ 438.993623] mlx5e_flow_put+0x29/0x60 [mlx5_core] [ 438.994161] mlx5e_delete_flower+0x261/0x390 [mlx5_core] [ 438.994728] tc_setup_cb_destroy+0xb9/0x190 [ 438.995150] fl_hw_destroy_filter+0x94/0xc0 [cls_flower] [ 438.995650] fl_change+0x11a4/0x13c0 [cls_flower] [ 438.996105] tc_new_tfilter+0x347/0xbc0 [ 438.996503] ? ___slab_alloc+0x70/0x8c0 [ 438.996929] rtnetlink_rcv_msg+0xf9/0x3e0 [ 438.997339] ? __netlink_sendskb+0x4c/0x70 [ 438.997751] ? netlink_unicast+0x286/0x2d0 [ 438.998171] ? __pfx_rtnetlink_rcv_msg+0x10/0x10 [ 438.998625] netlink_rcv_skb+0x54/0x100 [ 438.999020] netlink_unicast+0x203/0x2d0 [ 438.999421] netlink_sendmsg+0x1e4/0x420 [ 438.999820] __sock_sendmsg+0xa1/0xb0 [ 439.000203] ____sys_sendmsg+0x207/0x2a0 [ 439.000600] ? copy_msghdr_from_user+0x6d/0xa0 [ 439.001072] ___sys_sendmsg+0x80/0xc0 [ 439.001459] ? ___sys_recvmsg+0x8b/0xc0 [ 439.001848] ? generic_update_time+0x4d/0x60 [ 439.002282] __sys_sendmsg+0x51/0x90 [ 439.002658] do_syscall_64+0x50/0x110 [ 439.003040] entry_SYSCALL_64_after_hwframe+0x76/0x7e Fixes: 718ce4d601db ("net/mlx5: Consolidate update FTE for all removal changes") Fixes: cefc23554fc2 ("net/mlx5: Fix FTE cleanup") Signed-off-by: Mark Bloch Reviewed-by: Maor Gottlieb Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index 8505d5e241e1..6e4f8aaf8d2f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -2105,13 +2105,22 @@ lookup_fte_locked(struct mlx5_flow_group *g, fte_tmp = NULL; goto out; } + + nested_down_write_ref_node(&fte_tmp->node, FS_LOCK_CHILD); + if (!fte_tmp->node.active) { + up_write_ref_node(&fte_tmp->node, false); + + if (take_write) + up_write_ref_node(&g->node, false); + else + up_read_ref_node(&g->node); + tree_put_node(&fte_tmp->node, false); - fte_tmp = NULL; - goto out; + + return NULL; } - nested_down_write_ref_node(&fte_tmp->node, FS_LOCK_CHILD); out: if (take_write) up_write_ref_node(&g->node, false); From patchwork Thu Nov 7 18:35:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13866901 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2082.outbound.protection.outlook.com [40.107.100.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 187FB217329 for ; Thu, 7 Nov 2024 18:36:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Dragos Tatulea , Tariq Toukan Subject: [PATCH net 4/7] net/mlx5e: kTLS, Fix incorrect page refcounting Date: Thu, 7 Nov 2024 20:35:24 +0200 Message-ID: <20241107183527.676877-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107183527.676877-1-tariqt@nvidia.com> References: <20241107183527.676877-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE5:EE_|DM4PR12MB5794:EE_ X-MS-Office365-Filtering-Correlation-Id: 2779b737-efcf-4bf7-49ac-08dcff5b1e75 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: kcDGoQPl/GIKOVOP8ttgWwHXqTAvE6/IVg5rAUEBDr1/Uk3FMRxXUptUiQWJrW122gPJZ/3glIbpD88dNd5mp7D/qhJxP2SCqlkz8+yxDCusYFhCIycbG+RimlOY40YdCGBoEdZUa8NtQOdX+lHuH/ycmLavRyRaIY6CUd0uPuONrGkGfiBEX+RqvgylpG67IYYFMjxm6OSVSPKonJrML4+GQ7ftb4AjqkZPBRrJOyWgtB8hryGtcqFaBg5iyP9KUDmhbIjdqA77zZh6hW5cs7o1J+2VYaaO4cOiLwYZZBimAmzK+ghcjXClz5u9W4zZCXUNQg7daqQkM9Fm4pVfK0MFCqAHqE1vkEyV+6LLVJTE395ijAj7/iC7nZnW03czjZMPdYT1wNNWWmRKnHvrFCAHQYA89nrdbJakE/if3zk45l681+JX2BXPY6nEztK0+H8CUr7ey5GotHZs34U+l3d8SEvqN0HCDAbeRBntuWiz7SCAozFQENoL0PE53KZ1FqSTjJ1sp492m0g3VdAAguonpp24rF3VwIgFjtA6WvxHAHdtK9nvTsrv/gzTS34FOvIi2pPjUeT997QPe4TbhAuQkt3t/GSevn9PKVUYFILRAKfDnd0GPv15R4lAzqoiDqi3Ruzy+O7MZWgI/WW/ib18Eu9YMITlrVxTeJPrigNhMCoxdX+BrHKMTDIJ8K+hy16C1gpi6vCDPo92E6oukIGTmS/6TWS6GliizyLqwBdmTvdUmrZZazSVWkn5W5kaNpdLVjoevOv4CkScaIQtgG5rEw525W/z3EvVoH9C8Mb2+bq6rh2nFLz9kXZ3rNdbhhxyBZt5pL5pDM4bkda8Fq8aLclg7Hws10iQcbe0WvOwwn76zkD4vOmWlx8+j1agpnMla+cV5AP7f/vHDxv3kIIYm+eWsh8W2SM4k6ljIzPW8i797jbQ++JSDCe6J7+d4kliqH9okx4bTpN8iIQRWf2/qvou4fyp02intr9KZXmxSeXro6ukylS1VRveIAEsNM0pVuV4alUHHDC1MqOWRvadMPNCumy8j6vUwZDA//kfg82fi99n2WutXMiLOGfZpzenQJPja8Ze7qFgzv1pexyaxVDLEB9BILQBhTYVnrgdTGOvPHAvJeS1dvBi+nWXf8pmCr3fDPEakG6P1AV8kmgOG1zKiLdqvHGtdsn0D+aNlorUFA49LcdxL2DBgPFXgF0tRg0EMw6IH2i60K8n4mPDqVgRrIt/BS4RCQ9SuYc7gEkr6v4NQoIwlO+tgoJhgv6uJgxqS9tgpCMZ9+t8/s3dF9d6c+E2iS2CLhs+UkgOqpvde9J4j/QZf3KTij7mGyG3MJ3vl1a2SyYR3hLwn71HwXGkd01nzg+6P3hbKe7E35fErYZ1csVjenKPFX/dMQ+dwaEIqCqyH4bf95xBZQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 18:36:39.6471 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2779b737-efcf-4bf7-49ac-08dcff5b1e75 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5794 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea The kTLS tx handling code is using a mix of get_page() and page_ref_inc() APIs to increment the page reference. But on the release path (mlx5e_ktls_tx_handle_resync_dump_comp()), only put_page() is used. This is an issue when using pages from large folios: the get_page() references are stored on the folio page while the page_ref_inc() references are stored directly in the given page. On release the folio page will be dereferenced too many times. This was found while doing kTLS testing with sendfile() + ZC when the served file was read from NFS on a kernel with NFS large folios support (commit 49b29a573da8 ("nfs: add support for large folios")). Fixes: 84d1bb2b139e ("net/mlx5e: kTLS, Limit DUMP wqe size") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c index d61be26a4df1..3db31cc10719 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c @@ -660,7 +660,7 @@ tx_sync_info_get(struct mlx5e_ktls_offload_context_tx *priv_tx, while (remaining > 0) { skb_frag_t *frag = &record->frags[i]; - get_page(skb_frag_page(frag)); + page_ref_inc(skb_frag_page(frag)); remaining -= skb_frag_size(frag); info->frags[i++] = *frag; } @@ -763,7 +763,7 @@ void mlx5e_ktls_tx_handle_resync_dump_comp(struct mlx5e_txqsq *sq, stats = sq->stats; mlx5e_tx_dma_unmap(sq->pdev, dma); - put_page(wi->resync_dump_frag_page); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , William Tu , Tariq Toukan Subject: [PATCH net 5/7] net/mlx5e: clear xdp features on non-uplink representors Date: Thu, 7 Nov 2024 20:35:25 +0200 Message-ID: <20241107183527.676877-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107183527.676877-1-tariqt@nvidia.com> References: <20241107183527.676877-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE5:EE_|PH7PR12MB8827:EE_ X-MS-Office365-Filtering-Correlation-Id: c32a5c4e-2025-41c4-18b2-08dcff5b1f47 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: hJbsmFlYkSV4+JIllHkYGrTABye1FW+3XYYZb/7uBdIhOPSLBBDMiBk0qlYYJlO2ioRkIDFJK0uSEY24KBlaljI2aAxSd/tC1rlYWPjf5MZdTLwTsb8y3yrrQLpB1UoQBgujPdWoV57PYQ6y6QkLuZ1hQsURE5WVWWJrG0gZjTJGP2o5cVxlDmzraDNG+IirHl916qleFmizd7ssFEcFdKTl8tSBw77dOGCTrXwDYWtBbcusLFGVrSxn6KZkFSrXAUjIKK9y4KVBezFkI9ZOdqb3C1f2QmiTOeq2yl3TwcAzKnLoonrEX//vUXULue2qJcpv4vo2aiSyeX2BLTfOSSHs+zpkMsIQ0ZWIfTYPoRFq2OUoQDwElgMgbD3wMnCBOgDesVRPRj5qk6XniWd0cylYSMi6c8G+0JCzGVzxTZdrtQ4OpDx5eVjCSfMRynw7Or8iHuTsqUnXlSNdkES1Ak2wdMygGbr77X/4YjW+OwIwIyIzYoITySqoJwXS4YhUdJXxMalKBNQ2rQUXiQHcregCus034hlSVsHejo+fYJZ24tRKaZCiTB9BET8+5ezIOVtdp6OrLb0ZrqY7IStr9iq6Nk+hbG3PXJzHi7HKs+Fc3EwuEztcuPq1pABe95hkIAyvMHUVP0oaeaHMxLWquWXSAV5QhNfmvH5XNg6dAy7kdG5w0PnuZ5pDS/4uewAwPq7FT2mQpTQZpvp3X0aCkZpLikPF9BZ3kbhXv2dgT7x/qhsTezWHcnP8PU49o+/1TK7JKC+AUw+KzIlinuti+EniwxSGakjtzHKvToVg2+n8TVFIaTs8RTW1B2E6iCeSGIRkpb7Lvo0AAgD4SqFVZCtaqFRBEh0rqq+dDCkjO142guglSz6KbRVIxDcr/Dcrng4PH2c9yZYIQ0bevdmh5eYnpF1zRhR5DSOEmkBjERtkqcAo5RycFUiTLrk3uxhBcq4KY60zx9KIqKXQm24PXS6lwqHnx5CNSn8GnIUh2lAAUXPZqD3c1IkGU9PrgnOtrw1uPiM+ux5V/BwZO2dC5UrDH0O/7i37zBi6/k6mTeErTWQlMOSazpUJoyQ77lHMH8X0fnKon2C+wcdGDRIcmln8/bnuRJSbKAOk20vRTlgGkiEQ4/U/aPlqGpPgHcKdJe//6VD+wCPskF/TIHBRtcHjOSPNdcozwAHGVE+G3d1bt6J75OCwreHqDaJOQ22dwot3Oz4wSe0XmXCpzOcIf9yFDakHCTbgDcK+vzhi8rJcGMnefTDdUIaJoONvwFKbdA9lfyVJNUxdz8iV9I1IIGXuwG6thTMS9fmLdak/bi0ZQZ5njQbomxmZsHmQDuH/MLKjcTiFrfiH6fD8IxbbDo1LAL4QMl2kSioxcvstItFcdbK8sNmfrDh545LZuacXTi4IP2R+y+dfGHZ3/GTADA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 18:36:41.0377 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c32a5c4e-2025-41c4-18b2-08dcff5b1f47 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8827 X-Patchwork-Delegate: kuba@kernel.org From: William Tu Non-uplink representor port does not support XDP. The patch clears the xdp feature by checking the net_device_ops.ndo_bpf is set or not. Verify using the netlink tool: $ tools/net/ynl/cli.py --spec Documentation/netlink/specs/netdev.yaml --dump dev-get Representor netdev before the patch: {'ifindex': 8, 'xdp-features': {'basic', 'ndo-xmit', 'ndo-xmit-sg', 'redirect', 'rx-sg', 'xsk-zerocopy'}, 'xdp-rx-metadata-features': set(), 'xdp-zc-max-segs': 1, 'xsk-features': set()}, With the patch: {'ifindex': 8, 'xdp-features': set(), 'xdp-rx-metadata-features': set(), 'xsk-features': set()}, Fixes: 4d5ab0ad964d ("net/mlx5e: take into account device reconfiguration for xdp_features flag") Signed-off-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index e601324a690a..13a3fa8dc0cb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -4267,7 +4267,8 @@ void mlx5e_set_xdp_feature(struct net_device *netdev) struct mlx5e_params *params = &priv->channels.params; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Moshe Shemesh , Cosmin Ratiu , Yevgeny Kliteynik , Tariq Toukan Subject: [PATCH net 6/7] net/mlx5e: CT: Fix null-ptr-deref in add rule err flow Date: Thu, 7 Nov 2024 20:35:26 +0200 Message-ID: <20241107183527.676877-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107183527.676877-1-tariqt@nvidia.com> References: <20241107183527.676877-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AEB:EE_|DM4PR12MB6326:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ef1ba58-dd5f-4446-0cfa-08dcff5b20dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?cg6LPmH+pWTtnvvmyIVAA/8yFIz8kJ1?= =?utf-8?q?H2/2QC3BNU3ktV/0tn7PNgV0LJcm6bpr+tNnJYhNid6tzXIWy+BCnSOwUsxTGfR4D?= =?utf-8?q?JEr3/xN67oChlCp7wHQ/Mc5icOn72h634iFKccmZ45oUJmpPb2vA4HlVsrpZhx6G0?= =?utf-8?q?fGz/jmPE8UwS4PIqej1wJyGK7R2Xh8sl152lGIQAtbUUV0UuxQ3Rnl7G6PRiHkut0?= =?utf-8?q?a9ng2gF0QaDDe3KXTyW0VA02oT4n5N3VH7/ZCGEZOTbEYeYP6aHx9RP4WtFA9FFrd?= =?utf-8?q?aoYMiTsY0fhQ1FaSwVeGoGKkNrw7o05D8u/61Jz8KQy+RGIa8tDJf3C7QYK6I8uzG?= =?utf-8?q?vlycbM+QY0uJfCSphz9DAsPVhc7eE8yRpouo6tlsZXIBRCL3GfplHh3cNf5yIcQBX?= =?utf-8?q?o/4B24jqszOgaGQ9iR3tL3cgOCCCDjTq+Sw5K4IzHlQZ1I8Xwk5g+cZQD5ggTXBxm?= =?utf-8?q?ckPl+49boRSf26WAhg573+PN/10Woql5bgFbn/OwOeY2uaU5iExxhRW4XXz94bnIm?= =?utf-8?q?qnoa0imuK9kUCK/X4lU7u5aCdw0xLiM+bb1RDDD4ExJ1sgqh3vktDDid5lRi12a6R?= =?utf-8?q?jEl/Ta7A1aP+t4ZDog10rej3n8ZEn2ppZJLrjBkZkPC32icFLZFN49xF/P8T3j1nL?= =?utf-8?q?FE3TWsanVpxjCM9jmxsUIuc3Gw5wvY5X38tFr7pQ2dap6wjZgc+2lEh5k2b5GSsWS?= =?utf-8?q?UsBM+crIB/oIuMZZAWv5KKMpAM7gPLKf0lVEzN708nSenzd0LWQx0oXODsEoPSUlD?= =?utf-8?q?JT8bt4j2JWO+cByNWMZRMUcRA353gmlXdtPAzlUr3X6Ii0mjJ+AxmVOHePIp21xRn?= =?utf-8?q?col+QDBtLZkq56X4fbQPDVq8nQ2LuskB/mgLb073jXnZqpleD0zFESqB0IU+7l/Y9?= =?utf-8?q?yV6ldNc4auNsxQd0sJfUWJr5u6QVhDMQhYXb5wOsqTxgYpoGfcn93va1aA95pRPaJ?= =?utf-8?q?vUzySzLzCCO87/cRExA8A2YfnRhYDJFTyRmyTfE8lvRjl2xwNwfpZ8+DRXXc9TV8P?= =?utf-8?q?KtODD8EiQ2RkK5UdTATpvtiPOPKnKcR08RhJPq9grsNqnFY5R3bwejQcmfpjhg/xI?= =?utf-8?q?I/Nb5nBZiJgBJB7WUfAPyukftOQij5HTTUpNDsqdv0Qzbe+mvVmAOHARbcr0/RT3a?= =?utf-8?q?FecVSMU2hpyWRZ8z8RU8UWRj+aDQrH3TOX4Xudr0NCSciGwBbZ1NJtj9XBa6jNsiA?= =?utf-8?q?sdUu74g+NC8HQ+fXoivFbc7YxM97eAgMFvdBzjBGrN6QeU8jDmsNPqZfHexeuXuth?= =?utf-8?q?b6EMj+GilsSWq4FeMObQYblr7sxJAj+iDRCd4JjytIB3bZvfygozKWkyMggQTEX/c?= =?utf-8?q?YGixFQJ4iFSP0vMydXOvlziORfviu4u7bA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 18:36:43.6916 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ef1ba58-dd5f-4446-0cfa-08dcff5b20dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6326 X-Patchwork-Delegate: kuba@kernel.org From: Moshe Shemesh In error flow of mlx5_tc_ct_entry_add_rule(), in case ct_rule_add() callback returns error, zone_rule->attr is used uninitiated. Fix it to use attr which has the needed pointer value. Kernel log: BUG: kernel NULL pointer dereference, address: 0000000000000110 RIP: 0010:mlx5_tc_ct_entry_add_rule+0x2b1/0x2f0 [mlx5_core] … Call Trace: ? __die+0x20/0x70 ? page_fault_oops+0x150/0x3e0 ? exc_page_fault+0x74/0x140 ? asm_exc_page_fault+0x22/0x30 ? mlx5_tc_ct_entry_add_rule+0x2b1/0x2f0 [mlx5_core] ? mlx5_tc_ct_entry_add_rule+0x1d5/0x2f0 [mlx5_core] mlx5_tc_ct_block_flow_offload+0xc6a/0xf90 [mlx5_core] ? nf_flow_offload_tuple+0xd8/0x190 [nf_flow_table] nf_flow_offload_tuple+0xd8/0x190 [nf_flow_table] flow_offload_work_handler+0x142/0x320 [nf_flow_table] ? finish_task_switch.isra.0+0x15b/0x2b0 process_one_work+0x16c/0x320 worker_thread+0x28c/0x3a0 ? __pfx_worker_thread+0x10/0x10 kthread+0xb8/0xf0 ? __pfx_kthread+0x10/0x10 ret_from_fork+0x2d/0x50 ? __pfx_kthread+0x10/0x10 ret_from_fork_asm+0x1a/0x30 Fixes: 7fac5c2eced3 ("net/mlx5: CT: Avoid reusing modify header context for natted entries") Signed-off-by: Moshe Shemesh Reviewed-by: Cosmin Ratiu Reviewed-by: Yevgeny Kliteynik Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c index dcfccaaa8d91..92d5cfec3dc0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c @@ -866,7 +866,7 @@ mlx5_tc_ct_entry_add_rule(struct mlx5_tc_ct_priv *ct_priv, return 0; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net 7/7] net/mlx5e: Disable loopback self-test on multi-PF netdev Date: Thu, 7 Nov 2024 20:35:27 +0200 Message-ID: <20241107183527.676877-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107183527.676877-1-tariqt@nvidia.com> References: <20241107183527.676877-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D6:EE_|BL3PR12MB6593:EE_ X-MS-Office365-Filtering-Correlation-Id: ecaaa9df-e2e8-4fe1-2f26-08dcff5b258b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: 0lsYioVimdzP3OeI6pPJYp6oOpfGuR6cRMrEY7gB+Jsg8/TdVUxHWMdxRCg/Zi59c7fHa507Bzxr45Py82p/9ukqo6dB4NjHN0A6mqd2Bfk2HZMS0VHpJDKXoUBYZOxJDK2qqOCX5yk2hdmQTZ2otnWUDb72YW3pqJKYebUNykLzxKUSYsUpw6DqNvkvyStFymHy5dWu9G8tWhiFLd0jlepjISe+gk9daNgKCj3drp9a3gU65cUOqaVi9bz0LFASSL0hVc4B1Kk2asKtJn+LpRVgDAE7uCsWOUdZTO6doTwvQbMWn36JZ1DpSKpOMeTXGBqvg0yPoDbzElsygqb++Y38gajzk5qHvrbkKdHG0qAkn9N/KHcW8bysD18mPOdAe5RVYETw7ln4k0a6/7lxF9hoN0Nv9GvVMQUIT+qwDH6PBfiSCgJULB3B4S/gBw87ENeAt3/vjOD2eBAptYdMjGjAAey3YKQCNcbRwCCSfIU+9dQWH4SbngfhXCwDbm/QasPTZj8QCDQiub+TWg0n/ROhIlVMr4jz4e2FYaOZZX2C6iQYo5Df5tXxSnuX1f05le33GoDb5zHAWUKNj9lc/cimxUJpUNh89X6uVKc0sfop0qv1a6L4PZRqGkI7RyWX/XGBXGUMgRGcmfR3YQ7LXAhogzeZxVGGbORSP0uBxqtZWjg9Li5DdjQXlH67mZQUx9fa1AUX8MoPWdy4AfDuhkZCxzDjXnzuyHWJ4MlctylTQkz8rIMbKZXAJ64TtMxxdv8B1atp6sCxzwtbPFILTXRwsgUU3arUeGyFER2VFkIT7awCXFtRR63G4denD+7AB+T00S0FcDzVKOog/Tv8WhyScN6IgWfbPfeWhPPQabrouRqDXR6kehFYt1yH5RSaQJADlKdIwxzc9gFZ4Jx+CrXafiid+/HrXCR2GKcE2aEPUWXtOA7drcej6jgnkP7TL4RWj2D1IuUYLMC8ypE0T91RWcYgXk79PabZsH+qxy/WjKfmGrFY5y9/bWEi6axdMqJ3jpPXplcDi98yiwOkjPr41Lw/zPk8UoewX8CEO1t0xYUDAFBzuKVj54BUxyB+uuHHujmAbtcK/ElE3gTOuGt5b2KSYWtP37+IaUT9VISr6jObZAouSRvSZxxzCyZNIcx4h7AEhWUCZAvcUOQGSCOo4L7Q81RDMP9EWt1e7D+6JdWngKSkaMcl/UZojm/NWDsj3rsqNUaVX/fX2HtEuMbQG+UwWQXYRIWEzNlHekzmRCULJghXFnZxNC9nId5OoMlwc6KVxNW5zrslc+06etuuX+DgiRd5bLnTLToz+nd3O0SOPzxIpBz0B5AfW5GezUGlcpMo8blFHH6QJ/rqcuFb2h0mAcVK2Y449061u89b4x8JWo9ELqlnGA9Lre/N87s4Z6qpQJP/032utdYDGw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 18:36:51.5659 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ecaaa9df-e2e8-4fe1-2f26-08dcff5b258b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6593 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran In Multi-PF (Socket Direct) configurations, when a loopback packet is sent through one of the secondary devices, it will always be received on the primary device. This causes the loopback layer to fail in identifying the loopback packet as the devices are different. To avoid false test failures, disable the loopback self-test in Multi-PF configurations. Fixes: ed29705e4ed1 ("net/mlx5: Enable SD feature") Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c b/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c index 5bf8318cc48b..1d60465cc2ca 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c @@ -36,6 +36,7 @@ #include "en.h" #include "en/port.h" #include "eswitch.h" +#include "lib/mlx5.h" static int mlx5e_test_health_info(struct mlx5e_priv *priv) { @@ -247,6 +248,9 @@ static int mlx5e_cond_loopback(struct mlx5e_priv *priv) if (is_mdev_switchdev_mode(priv->mdev)) return -EOPNOTSUPP; + if (mlx5_get_sd(priv->mdev)) + return -EOPNOTSUPP; + return 0; }