From patchwork Fri Nov 8 07:06:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13867676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1914FD5E140 for ; Fri, 8 Nov 2024 07:19:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t9JGj-0006Ps-EZ; Fri, 08 Nov 2024 02:18:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9JGU-0006Kt-Az for qemu-devel@nongnu.org; Fri, 08 Nov 2024 02:18:42 -0500 Received: from mgamail.intel.com ([198.175.65.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9JGR-0007PD-Jg for qemu-devel@nongnu.org; Fri, 08 Nov 2024 02:18:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731050319; x=1762586319; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=btE2N/+WTXZCx3oanGi+tZdW8La69qQYP7KKi9es/lg=; b=lmPsPXyv7V7Z3G/Zb2yylWXWQfr9epPvwD0/um6soBdebtqSCUFDJ56Q JuOA8OtbxWiDlIzJggUCNsq+44+/SFehH69x9sWyTFa/+YWXZtPKVh7q4 F3MiDKs+9nvX5YIzpGjKnQeNNacXyuQJxKoxKYSBmKzorNsmCPbbIcrcf 3L5KrdKpPeKn/ppyjlFH9d4frkvfABhEoFGiyVArfRMJ4BNNIUhvadve9 C/yG3ALsAUpAooZ2LWl4Nuvoqyo1FoO30v0DAKiu/YbgclwCJoPe/43EU 0S+j/QSkpclD60EZzoBrrC6VVq89WjObKYbL4M31Qjrhjm9JzA6gTrlUh A==; X-CSE-ConnectionGUID: B+Xg+Eh0SPyFOV0OuyTHbQ== X-CSE-MsgGUID: +Qdc5RhBTUORYca/GfIIvQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="31082905" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="31082905" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 23:18:38 -0800 X-CSE-ConnectionGUID: NKPtfFqZSMegpk3pnAWufg== X-CSE-MsgGUID: jR3oOqh3RtG0iKPjhdCGsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,137,1728975600"; d="scan'208";a="86240933" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa008.jf.intel.com with ESMTP; 07 Nov 2024 23:18:33 -0800 From: Xiaoyao Li To: Paolo Bonzini Cc: Peter Maydell , Michael Rolnik , Brian Cain , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Palmer Dabbelt , Alistair Francis , Bin Meng , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-devel@nongnu.org, xiaoyao.li@intel.com Subject: [PATCH v1 1/4] cpu: Introduce qemu_early_init_vcpu() to initialize nr_cores and nr_threads inside it Date: Fri, 8 Nov 2024 02:06:06 -0500 Message-Id: <20241108070609.3653085-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108070609.3653085-1-xiaoyao.li@intel.com> References: <20241108070609.3653085-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.16; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.781, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently cpu->nr_cores and cpu->nr_threads are initialized in qemu_init_vcpu(), which is called a bit late in *cpu_realizefn() for each ARCHes. x86 arch would like to use nr_cores and nr_threads earlier in its realizefn(). Introduce qemu_early_init_vcpu() and move the initialization of nr_cores and nr_threads from qemu_init_vcpu() to it. Call qemu_early_init_vcpu() at the beginning of realizefn() for each ARCH. Signed-off-by: Xiaoyao Li --- This patch only is testes on x86 machine, please help test on other ARCHes. --- accel/tcg/user-exec-stub.c | 4 ++++ hw/core/cpu-common.c | 2 +- include/hw/core/cpu.h | 8 ++++++++ system/cpus.c | 6 +++++- target/alpha/cpu.c | 2 ++ target/arm/cpu.c | 2 ++ target/avr/cpu.c | 2 ++ target/hexagon/cpu.c | 2 ++ target/hppa/cpu.c | 2 ++ target/i386/cpu.c | 2 ++ target/loongarch/cpu.c | 2 ++ target/m68k/cpu.c | 2 ++ target/microblaze/cpu.c | 2 ++ target/mips/cpu.c | 2 ++ target/openrisc/cpu.c | 2 ++ target/ppc/cpu_init.c | 2 ++ target/riscv/cpu.c | 2 ++ target/rx/cpu.c | 2 ++ target/s390x/cpu.c | 2 ++ target/sh4/cpu.c | 2 ++ target/sparc/cpu.c | 2 ++ target/tricore/cpu.c | 2 ++ target/xtensa/cpu.c | 2 ++ 23 files changed, 56 insertions(+), 2 deletions(-) diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 4fbe2dbdc883..64baf917b55c 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -10,6 +10,10 @@ void cpu_remove_sync(CPUState *cpu) { } +void qemu_early_init_vcpu(CPUState *cpu) +{ +} + void qemu_init_vcpu(CPUState *cpu) { } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 09c79035949b..3b60e62228e4 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -242,7 +242,7 @@ static void cpu_common_initfn(Object *obj) cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; /* user-mode doesn't have configurable SMP topology */ - /* the default value is changed by qemu_init_vcpu() for system-mode */ + /* the default value is changed by qemu_early_init_vcpu() for system-mode */ cpu->nr_cores = 1; cpu->nr_threads = 1; cpu->cflags_next_tb = -1; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c3ca0babcb3f..99ecf18eec02 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1063,6 +1063,14 @@ void start_exclusive(void); */ void end_exclusive(void); +/** + * qemu_early_init_vcpu: + * @cpu: The vCPU to initialize. + * + * Early initialize a vCPU. + */ +void qemu_early_init_vcpu(CPUState *cpu); + /** * qemu_init_vcpu: * @cpu: The vCPU to initialize. diff --git a/system/cpus.c b/system/cpus.c index 1c818ff6828c..a1b46f68476a 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -662,12 +662,16 @@ const AccelOpsClass *cpus_get_accel(void) return cpus_accel; } -void qemu_init_vcpu(CPUState *cpu) +void qemu_early_init_vcpu(CPUState *cpu) { MachineState *ms = MACHINE(qdev_get_machine()); cpu->nr_cores = machine_topo_get_cores_per_socket(ms); cpu->nr_threads = ms->smp.threads; +} + +void qemu_init_vcpu(CPUState *cpu) +{ cpu->stopped = true; cpu->random_seed = qemu_guest_random_seed_thread_part1(); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 9db1dffc03ec..56309a647763 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -93,6 +93,8 @@ static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + #ifndef CONFIG_USER_ONLY /* Use pc-relative instructions in system-mode */ cs->tcg_cflags |= CF_PCREL; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5b751439bdc7..98dcc0855868 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1971,6 +1971,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) CPUARMState *env = &cpu->env; Error *local_err = NULL; + qemu_early_init_vcpu(cs); + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ tcg_cflags_set(cs, CF_PCREL); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3132842d5654..b8beaf9682c0 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -111,6 +111,8 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **errp) AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc4902..5931dce05bec 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -299,6 +299,8 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c38439c1800e..cf7b46e4ff42 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -169,6 +169,8 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3baa95481fbc..1179b7a3ce62 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7757,6 +7757,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) Error *local_err = NULL; unsigned requested_lbr_fmt; + qemu_early_init_vcpu(cs); + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ tcg_cflags_set(cs, CF_PCREL); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 57cc4f314bf7..9572cbd2a4f5 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -598,6 +598,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1d49f4cb2382..77acbadeb65f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -304,6 +304,8 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp) M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + register_m68k_insns(&cpu->env); cpu_exec_realizefn(cs, &local_err); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 135947ee8004..0850043ca1a2 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -226,6 +226,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) int i = 0; Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 9724e71a5e0f..8cd1b794e0af 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -460,6 +460,8 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + if (!clock_get(cpu->clock)) { #ifndef CONFIG_USER_ONLY if (!qtest_enabled()) { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6ec54ad7a6cf..071239dd3134 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -147,6 +147,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23881d09e9f3..5c2ab87319e7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6949,6 +6949,8 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b527..40cf24d2e759 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1166,6 +1166,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 36d2a6f18906..a24b3f28b455 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -117,6 +117,8 @@ static void rx_cpu_realize(DeviceState *dev, Error **errp) RXCPUClass *rcc = RX_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 4e41a3dff59b..20f083834309 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -247,6 +247,8 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp) S390CPUClass *scc = S390_CPU_GET_CLASS(dev); Error *err = NULL; + qemu_early_init_vcpu(cs); + /* the model has to be realized before qemu_init_vcpu() due to kvm */ s390_realize_cpu_model(cs, &err); if (err) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcfd5..74488a1c0ba4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -212,6 +212,8 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp) SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 54cb269e0af1..57cd7911263e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -788,6 +788,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) Error *local_err = NULL; CPUSPARCState *env = cpu_env(cs); + qemu_early_init_vcpu(cs); + #if defined(CONFIG_USER_ONLY) /* We are emulating the kernel, which will trap and emulate float128. */ env->def.features |= CPU_FEATURE_FLOAT128; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1a261715907d..d58271696631 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -88,6 +88,8 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) CPUTriCoreState *env = &cpu->env; Error *local_err = NULL; + qemu_early_init_vcpu(cs); + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a08c7a0b1f20..92120141fee2 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -163,6 +163,8 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); Error *local_err = NULL; + qemu_early_init_vcpu(cs); + #ifndef CONFIG_USER_ONLY xtensa_irq_init(&XTENSA_CPU(dev)->env); #endif From patchwork Fri Nov 8 07:06:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13867677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88365D5E144 for ; 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X-CSE-ConnectionGUID: nIwW9Xr+R+m92JU1r/Pagw== X-CSE-MsgGUID: pI4+0M+TRla6525hadsfFg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="31082920" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="31082920" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 23:18:42 -0800 X-CSE-ConnectionGUID: TlXPCfgiRLWE96MY6ximKw== X-CSE-MsgGUID: WCA84hHqRCSnCnicoDPeFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,137,1728975600"; d="scan'208";a="86240949" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa008.jf.intel.com with ESMTP; 07 Nov 2024 23:18:38 -0800 From: Xiaoyao Li To: Paolo Bonzini Cc: Peter Maydell , Michael Rolnik , Brian Cain , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Palmer Dabbelt , Alistair Francis , Bin Meng , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-devel@nongnu.org, xiaoyao.li@intel.com Subject: [PATCH v1 2/4] i386/cpu: Set up CPUID_HT in x86_cpu_expand_features() instead of cpu_x86_cpuid() Date: Fri, 8 Nov 2024 02:06:07 -0500 Message-Id: <20241108070609.3653085-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108070609.3653085-1-xiaoyao.li@intel.com> References: <20241108070609.3653085-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.16; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.781, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Track CPUID_HT in env->features[FEAT_1_EDX] instead of evaluating it each time in cpu_x86_cpuid(). env->features[] should be set up in cpu's realizefn() and cpu_x86_cpuid() should be the consumer of it. Beside, TDX support also depends on it because TDX is going to validate the feature configuration by comparing what TDX module reports with env->features[]. If not tracking CPUID_HT in env->features[], it gets warnings like below when number of vcpus > 1: warning: TDX enforces set the feature: CPUID.01H:EDX.ht [bit 28] Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1179b7a3ce62..e0c5a61ff615 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6544,7 +6544,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = env->features[FEAT_1_EDX]; if (threads_per_pkg > 1) { *ebx |= threads_per_pkg << 16; - *edx |= CPUID_HT; } if (!cpu->enable_pmu) { *ecx &= ~CPUID_EXT_PDCM; @@ -7490,6 +7489,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu) void x86_cpu_expand_features(X86CPU *cpu, Error **errp) { CPUX86State *env = &cpu->env; + CPUState *cs = CPU(cpu); FeatureWord w; int i; GList *l; @@ -7531,6 +7531,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) } } + if (cs->nr_cores * cs->nr_threads > 1) { + env->features[FEAT_1_EDX] |= CPUID_HT; + } + for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { FeatureDep *d = &feature_dependencies[i]; if (!(env->features[d->from.index] & d->from.mask)) { From patchwork Fri Nov 8 07:06:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13867678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4B47D5E144 for ; Fri, 8 Nov 2024 07:19:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t9JGs-0006Uj-Qj; Fri, 08 Nov 2024 02:19:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9JGb-0006Nr-9e for qemu-devel@nongnu.org; Fri, 08 Nov 2024 02:18:49 -0500 Received: from mgamail.intel.com ([198.175.65.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9JGZ-0007Po-L1 for qemu-devel@nongnu.org; Fri, 08 Nov 2024 02:18:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731050327; x=1762586327; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CIy5dPUvwqW57qY3sj4mBIedFmwRWWxMjES6nwTfxNM=; b=NGhFH1aIkl7+adv3T6Qq8XxCJbMUaxxoY2RYU+HTik+Yr2pWS5kIeY7T zgCYNBxVritW2ZuqTNuxSB41XCeWsw6HErJ5kciuFuc6DT+MaMg3+RoZT WeOzw7XUP2ez+HmFQia2MssMze0fmfSj/h7Aq4xXOdQ9uaJUyfkm30Vwa 0N1iyfH6KFjkIv/QrGtmQ7DxQwhRiddtfK7tDE4/pcq2XlCR/2pdT5nqB e4/W/E9mV8MqlD0dHmB1jyKlPof5q8LR9gM7BB/NIiluxryA9ke/DZywR HfNKAxpJthOY2eOwbVxHodfftvT4lmJO1BZCOxupMvYByMM+N2or7Bgc4 g==; X-CSE-ConnectionGUID: /nLoMfmPTCKB78ybi1O9UA== X-CSE-MsgGUID: uio5sAcDTLqgvCD/puXnCA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="31082935" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="31082935" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 23:18:46 -0800 X-CSE-ConnectionGUID: qzq3du5cTLyaZoAVCgcIIQ== X-CSE-MsgGUID: TK+F+UT4R9ikjroVBqr2og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,137,1728975600"; d="scan'208";a="86240968" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa008.jf.intel.com with ESMTP; 07 Nov 2024 23:18:43 -0800 From: Xiaoyao Li To: Paolo Bonzini Cc: Peter Maydell , Michael Rolnik , Brian Cain , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Palmer Dabbelt , Alistair Francis , Bin Meng , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-devel@nongnu.org, xiaoyao.li@intel.com Subject: [PATCH v1 3/4] i386/cpu: Set and track CPUID_EXT3_CMP_LEG in env->features[FEAT_8000_0001_ECX] Date: Fri, 8 Nov 2024 02:06:08 -0500 Message-Id: <20241108070609.3653085-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108070609.3653085-1-xiaoyao.li@intel.com> References: <20241108070609.3653085-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.16; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.781, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org ... instead of manually set it in cpu_x86_cpuid(). Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e0c5a61ff615..015e085fa66c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6959,17 +6959,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx = env->features[FEAT_8000_0001_ECX]; *edx = env->features[FEAT_8000_0001_EDX]; - /* The Linux kernel checks for the CMPLegacy bit and - * discards multiple thread information if it is set. - * So don't set it here for Intel to make Linux guests happy. - */ - if (threads_per_pkg > 1) { - if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || - env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || - env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { - *ecx |= 1 << 1; /* CmpLegacy bit */ - } - } if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && !(env->hflags & HF_LMA_MASK)) { *edx &= ~CPUID_EXT2_SYSCALL; @@ -7533,6 +7522,15 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) if (cs->nr_cores * cs->nr_threads > 1) { env->features[FEAT_1_EDX] |= CPUID_HT; + + /* + * The Linux kernel checks for the CMPLegacy bit and + * discards multiple thread information if it is set. + * So don't set it here for Intel to make Linux guests happy. + */ + if (!IS_INTEL_CPU(env)) { + env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; + } } for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { From patchwork Fri Nov 8 07:06:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13867679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0711ED5E140 for ; Fri, 8 Nov 2024 07:19:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t9JGu-0006X4-Qi; Fri, 08 Nov 2024 02:19:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9JGg-0006QA-QH for qemu-devel@nongnu.org; Fri, 08 Nov 2024 02:18:55 -0500 Received: from mgamail.intel.com ([198.175.65.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t9JGe-0007Po-5n for qemu-devel@nongnu.org; Fri, 08 Nov 2024 02:18:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731050332; x=1762586332; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UomARFnS0nQKCvmXO47RhasSQBfQMFc85ip6MKMZ2SM=; b=B7J1NqVznJevdURtj6nvPNlerKSPKLoAG5DyuoRcdlwF5ndS0H8WV9tj 0RYqrA453i/NbpxgwnURsvGNDacTOkhtSdmveCUTr19f1hn6gtmvxdo6l DS6bpJ9+iiZB5Fk9XtqqctNusRAKVetfOsUaHYaRFwwU+qP/GbDjECeA1 ROAeXyikF2/nt+fGkzb41omAMuf4bObos1X7RmrgGv2TtV52btbMuDOwh r3Mqo4f0SPx4aJPVeKmTeKd6p2IzqyL/57xFlzP8NbVZdG/UYITmQ3oH3 aBuaCvnMjAF6TgzRZzBmOMLUfQBBYcoWAIxqIEYpM5KZ48SaggA/uHwqQ Q==; X-CSE-ConnectionGUID: otc9tAmfQp+sxVhyo5mXHg== X-CSE-MsgGUID: qHLRXI7qR0Km9S2vxtHoEg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="31082949" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="31082949" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 23:18:51 -0800 X-CSE-ConnectionGUID: UG4tvoAGQMSOaJzwCJltbQ== X-CSE-MsgGUID: ZH7HAklYR6mY4wh8GR5bkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,137,1728975600"; d="scan'208";a="86240988" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa008.jf.intel.com with ESMTP; 07 Nov 2024 23:18:47 -0800 From: Xiaoyao Li To: Paolo Bonzini Cc: Peter Maydell , Michael Rolnik , Brian Cain , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Palmer Dabbelt , Alistair Francis , Bin Meng , Thomas Huth , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-devel@nongnu.org, xiaoyao.li@intel.com Subject: [PATCH v1 4/4] i386/cpu: Rectify the comment on order dependency on qemu_init_vcpu() Date: Fri, 8 Nov 2024 02:06:09 -0500 Message-Id: <20241108070609.3653085-5-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108070609.3653085-1-xiaoyao.li@intel.com> References: <20241108070609.3653085-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.16; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.781, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now cs->nr_threads is initialized in qemu_early_init_vcpu() which is called at the begining of realizef(). Drop the comment of the order dependcy on qemu_init_vcpu() and hoist code to put it together with other feature checking. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 015e085fa66c..98910fa49250 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7887,6 +7887,21 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) */ cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; + /* + * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU + * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX + * based on inputs (sockets,cores,threads), it is still better to give + * users a warning. + */ + if (IS_AMD_CPU(env) && + !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && + cs->nr_threads > 1) { + warn_report_once("This family of AMD CPU doesn't support " + "hyperthreading(%d). Please configure -smp " + "options properly or try enabling topoext " + "feature.", cs->nr_threads); + } + /* For 64bit systems think about the number of physical bits to present. * ideally this should be the same as the host; anything other than matching * the host can cause incorrect guest behaviour. @@ -7991,24 +8006,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) x86_cpu_gdb_init(cs); qemu_init_vcpu(cs); - /* - * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU - * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX - * based on inputs (sockets,cores,threads), it is still better to give - * users a warning. - * - * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise - * cs->nr_threads hasn't be populated yet and the checking is incorrect. - */ - if (IS_AMD_CPU(env) && - !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && - cs->nr_threads > 1) { - warn_report_once("This family of AMD CPU doesn't support " - "hyperthreading(%d). Please configure -smp " - "options properly or try enabling topoext " - "feature.", cs->nr_threads); - } - #ifndef CONFIG_USER_ONLY x86_cpu_apic_realize(cpu, &local_err); if (local_err != NULL) {