From patchwork Sat Nov 9 09:28:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13869335 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B1A2145B27 for ; Sat, 9 Nov 2024 09:29:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731144563; cv=none; b=mAr0Xoqili7VM8ospvw1hsbtbFs5boCfczSfiK44CPbrRWVNQYg3riapoS0O8guhO89BUBY9V3fDG+yd7UOZ+pLSte52z6D/cuPF9B5asSaet2BO2t7wLL8wQcfoEl90wu81hwzIGVsIsNyJlp60JVavszF+VSYMMV+CEjUNyCE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731144563; c=relaxed/simple; bh=VItcQZD2Asoua4RQn/ctc3HUAFeoMyvrerFIagM4G4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hDRSpvmbglCWb7cWBFQbXyIoXCUX03YR1h1bW/TZgKxbhxBWwr6CQur8CZWrnZzYWqp4iBjaX3ct6vTqiR9HcisXYTNNy1zljSrIV61LJh3enDovhvdDnQzn9mkJRxRdioUEjbr4NNxchXQlvZaJNXVheOJBVdfpvdntXiVOfw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s3gJ9CfL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s3gJ9CfL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 43447C4CECE; Sat, 9 Nov 2024 09:29:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731144562; bh=VItcQZD2Asoua4RQn/ctc3HUAFeoMyvrerFIagM4G4g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=s3gJ9CfL0f6apB4GPtjwLcAZfuMS9+z1xXiCo9efswRQdLuJNm4XD1idFfgXVP6zt tqWG+J+3NQTgPJgljj02miXxqgUeN33nLbO7n1cM+vcAFkxNLcswyOtT+WuF3Q0eOj Dz6keJtB6C8wxVsTsm70T7OSmRNz22pX0xF5q1QCdfPUw9uJFwZ8Kkl2S5iR7/xDh+ xaZbmjk6/IHJR35KzyxO7DN9es5JiycMvQVTm5FvdNVsaqruAVh1UyyA0XQ91BXTRL LNUQ7U3imOYOePqByUKjuKzRjCmmEC56CvHCjI0KmlHVz4mAH83vPyJ2XyD5A6PmVI 3c8Uf2vpEO60w== From: Lorenzo Bianconi Date: Sat, 09 Nov 2024 10:28:37 +0100 Subject: [PATCH v2 1/4] PCI: mediatek-gen3: Add missing reset_control_deassert() for mac_rst in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241109-pcie-en7581-fixes-v2-1-0ea3a4af994f@kernel.org> References: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> In-Reply-To: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Even if this is not a real issue since Airoha EN7581 SoC does not require the mac reset line, add missing reset_control_deassert() for mac reset line in mtk_pcie_en7581_power_up() callback. Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 66ce4b5d309bb6d64618c70ac5e0a529e0910511..0fac0b9fd785e463d26d29d695b923db41eef9cc 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -897,6 +897,9 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) */ mdelay(PCIE_EN7581_RESET_TIME_MS); + /* MAC power on and enable transaction layer clocks */ + reset_control_deassert(pcie->mac_reset); + pm_runtime_enable(dev); pm_runtime_get_sync(dev); @@ -931,6 +934,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) err_clk_prepare: pm_runtime_put_sync(dev); pm_runtime_disable(dev); + reset_control_assert(pcie->mac_reset); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); err_phy_deassert: phy_power_off(pcie->phy); From patchwork Sat Nov 9 09:28:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13869336 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6AC7145A16 for ; Sat, 9 Nov 2024 09:29:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731144565; cv=none; b=ltZmw2iSM1RC99T8Ib0yQxcPRS8eQnbgTNGuVZ1AL3fbepj1/m4yduBwFJB0DkfN5UTy0+RKsYAhgarUr4wWi8IRkz5QRY1myl95B986Owj2dmK3k/ziynfzzZu3nVVtg10yK5k72COKvxqQ8sGulWGnWbTZqdt80ptKtLEMGco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731144565; c=relaxed/simple; bh=b7sY8eeXTXCv7mml0kvVahhj89cw5WkIPMaWEq+tesY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VLynqyS6Zo2sGHlR07ld/q6C90VJz+YjnYUogGx67/tIjoFSR/JEmGg9xMdlXj0Agn1ylGlyZF6E4ssq5cc50b9soy5gqR0Atm2RRV1UvaK7RzaeErfflHWV7HATU2ggJ48w+zsLYcll30bQjS9ce+49ZBSkwWsh8kDFsXU1eSM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dZD88OtH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dZD88OtH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 21087C4CECE; Sat, 9 Nov 2024 09:29:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731144565; bh=b7sY8eeXTXCv7mml0kvVahhj89cw5WkIPMaWEq+tesY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dZD88OtH+gYFHPjg33MNygeYJkvaJE0LQW7CM3cno8MbuUB4pO7xWGQozMZ6gjScN x+wmlUSICc0B5d3f2K+fLQa/KfIVRxHwmjm1hnQ/fC7Ny6Vn8kuvo88gfJ/HCDd/gA MMi5IIqmMU7s4YinGdgZEbenrFODb2wn3troLGGGxajZn1MDelAOQAwoGH95KFKAZy KEiRkhJBXdomHLbtm4BFcIpllBqQJ0hiTkcBzB5S4BhU5pSGSGE1f5NQDWyU3tiESo vyGYDAd55C8oPHgcL12aHBCZKoL9ZiEa9z4SdRRmvXfiUUoYQFu9OMtwpIvsfrBTm1 nDRgL24JOAHiQ== From: Lorenzo Bianconi Date: Sat, 09 Nov 2024 10:28:38 +0100 Subject: [PATCH v2 2/4] PCI: mediatek-gen3: rely on clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241109-pcie-en7581-fixes-v2-2-0ea3a4af994f@kernel.org> References: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> In-Reply-To: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Squash clk_bulk_prepare() and clk_bulk_enable() in clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 0fac0b9fd785e463d26d29d695b923db41eef9cc..8c8c733a145634cdbfefd339f4a692f25a6e24de 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -903,12 +903,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); - if (err) { - dev_err(dev, "failed to prepare clock\n"); - goto err_clk_prepare; - } - val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | @@ -921,17 +915,15 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err = clk_bulk_enable(pcie->num_clks, pcie->clks); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); - goto err_clk_enable; + goto err_clk_init; } return 0; -err_clk_enable: - clk_bulk_unprepare(pcie->num_clks, pcie->clks); -err_clk_prepare: +err_clk_init: pm_runtime_put_sync(dev); pm_runtime_disable(dev); reset_control_assert(pcie->mac_reset); From patchwork Sat Nov 9 09:28:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13869337 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C646146D57 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gtKbOjIp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B7A64C4CECE; Sat, 9 Nov 2024 09:29:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731144568; bh=L+Tb8zBkZwxLcT8ZO2OWnc/bfPC5zN+Fbgmb8QaRcIE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gtKbOjIppaEaAgSR4fuMak7Xra9a9/IBd6y7Qja22dc44jViJEdaAufIo3ul4Uqiu shETEdwZOjYiFNr7sS+NSKkP6H/lqUXB4uX289b6g9T0Vyl9lpNq0XDVeJ7TQ9J1gW vVdRbExcJRi/nFEYtrWetPEtrwNc9tUgPkpH6P66wdcYsrnoLaDVpu55WOc4+7Ptw5 A2StZs69Ydsqu+v3xlexPuA3TfXQCvHtyo6Pg2jBi6LeNy+mBaAG979n5eq95QdHDw FlTEpNvB9WnkFjMUCCsPFY9V8odI4uwS7K1qs8RekriNAPJazxeQ2gqfPdJVsQE/n0 HxPfypb2s8aOg== From: Lorenzo Bianconi Date: Sat, 09 Nov 2024 10:28:39 +0100 Subject: [PATCH v2 3/4] PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241109-pcie-en7581-fixes-v2-3-0ea3a4af994f@kernel.org> References: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> In-Reply-To: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 In order to make the code more readable, move phy and mac reset lines assert/de-assert configuration in .power_up() callback (mtk_pcie_en7581_power_up()/mtk_pcie_power_up()). Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to complete PCIe reset on MediaTek controller. Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 8c8c733a145634cdbfefd339f4a692f25a6e24de..1ad93d2407810ba873d9a16da96208b3cc0c3011 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -120,6 +120,9 @@ #define MAX_NUM_PHY_RESETS 3 +/* Time in us needed to complete PCIe reset on MediaTek controller */ +#define PCIE_MTK_RESET_TIME_US 10 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -867,6 +870,14 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) int err; u32 val; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + /* * Wait for the time needed to complete the bulk assert in * mtk_pcie_setup for EN7581 SoC. @@ -941,6 +952,15 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) struct device *dev = pcie->dev; int err; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); + /* PHY power on and enable pipe clock */ err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); if (err) { @@ -1013,14 +1033,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) * counter since the bulk is shared. */ reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - /* - * The controller may have been left out of reset by the bootloader - * so make sure that we get a clean start by asserting resets here. - */ - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - - reset_control_assert(pcie->mac_reset); - usleep_range(10, 20); /* Don't touch the hardware registers before power up */ err = pcie->soc->power_up(pcie); From patchwork Sat Nov 9 09:28:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13869338 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FC53145A16 for ; Sat, 9 Nov 2024 09:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731144571; cv=none; b=YgkpfAuN4o27jBBrVONlRqM5EsUl9o9MDYHrcCm6kC/CXK3jD0zkTKYcu7OLMF90CHGI5P9T0twfABHhBesIh9rEVz+gu5++n9cLHFXXdS2PdtEoY+fNqhOHxvj9mRwv5XiJ6nASDZHZNnVlAtnCwt3UGOXnXNo1EKt6fBeD3aw= ARC-Message-Signature: i=1; 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b=offz9ekkgH0jrv3N1QGwBDKkc4x9pVQe86sBYqBv2hSxhC2r+0OlPizA+i5isYMQl UghLiaYW0E3ge9qfhleygJLv+tqI2VHtQ7Ro+++S4MaIiBt6/YtYLYuqZGJsIo5bls yk9WZUOb0FRuexfapY9hE2I2U/WaX7S2btTeuHWWMM3nRXA02EbknbKMES2tEk62g1 yyO9fiTSdGve+BJYi/jZmp+tdRJuFdodY+Ef/6qd8dVjfR4j7N5kAYPBtTGkRm2R8u MWaTeRxLBLZ0iQKntNGaBmuIejvlFtwnshUoITwld2xXe5f9eFROmRvr2buM3jQz82 0jLO9rLs1l6Ow== From: Lorenzo Bianconi Date: Sat, 09 Nov 2024 10:28:40 +0100 Subject: [PATCH v2 4/4] PCI: mediatek-gen3: Add comment about initialization order in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241109-pcie-en7581-fixes-v2-4-0ea3a4af994f@kernel.org> References: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> In-Reply-To: <20241109-pcie-en7581-fixes-v2-0-0ea3a4af994f@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike MediaTek PCIe controller, the Airoha EN7581 requires PHY initialization and power-on before PHY reset deassert. Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 1ad93d2407810ba873d9a16da96208b3cc0c3011..c9981013e59d18ccd3294acdcbd536dd95a0e436 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -884,6 +884,10 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) */ mdelay(PCIE_EN7581_RESET_TIME_MS); + /* + * Unlike the MediaTek controllers, the Airoha EN7581 requires PHY + * initialization and power-on before PHY reset deassert. + */ err = phy_init(pcie->phy); if (err) { dev_err(dev, "failed to initialize PHY\n");