From patchwork Mon Nov 11 03:37:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuan Liu via B4 Relay X-Patchwork-Id: 13870204 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 087A73224; Mon, 11 Nov 2024 03:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731296230; cv=none; b=j41NGmdlPMRgR94xglabUKDE7UGHycrZzVtdGK3K64Xx7SIEo27lTtoR7chEsM8e9UCnngZjRBGV2h+fddv8kEzUAtd01j+AOugw2vAQjnduGia7+Xxfe//JvRHbghbwj4ln6EcLToi555vLTQS/v3QZm8JuTYVo8jbAB9b1TbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731296230; c=relaxed/simple; bh=FLYPFnw2Yqnj3auU91LfHIFR9j23kCj3QGzsgZlM2TU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NFDToJOjmd0WKxhI1yzQlhDL/NMgghoy00NRJURb8AfhbXqUGH89haysQlAfy+UxMNImagnesRefmiGNi+1HBTJc5v+aMz3mjqerxWmvxAe3JmOYxJA4et8XoiKiRFJRD7ViZFNNVf4OorXfOFePDL0bN6USdboJxOZW1/mnqo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pgvqDa4p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pgvqDa4p" Received: by smtp.kernel.org (Postfix) with ESMTPS id C9305C4CECF; Mon, 11 Nov 2024 03:37:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731296229; bh=FLYPFnw2Yqnj3auU91LfHIFR9j23kCj3QGzsgZlM2TU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pgvqDa4pX+626RzLwZsL24T9zfPieZu92smUBkx72aDNnWAfWqiJH7sjEBkfHQ14a jv9zS0gyJ/a6vC0CEjTH918NYMABEmiZ8PV5Gv6UxJrJD8weKKQHfyG4claUg/S4l/ G/N65cg0/2d8y0O++T8ieMKgiPV3VYb9Vwqek5Q6ioXYpk3mpXrgKMwISnQHyTC9Pr d7dz9Yr+6eOjtmN8tFVk+I3SWnH0HguJcVXZ/8prA+0uJxEFFRhaVyWN86mi6v3m8v SRB5JrktapbOgAGdWFjAygR5MPvPsCX1nRpHwnCKmnnzx0HwEylx6R8ldcI0ifUFKe /EwCR3aW8XsVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9B29D12D63; Mon, 11 Nov 2024 03:37:09 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Mon, 11 Nov 2024 11:37:01 +0800 Subject: [PATCH v2 1/3] clk: Fix the CLK_IGNORE_UNUSED failure issue Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241111-fix_glitch_free-v2-1-0099fd9ad3e5@amlogic.com> References: <20241111-fix_glitch_free-v2-0-0099fd9ad3e5@amlogic.com> In-Reply-To: <20241111-fix_glitch_free-v2-0-0099fd9ad3e5@amlogic.com> To: Michael Turquette , Stephen Boyd , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731296227; l=3533; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=9b1cy9TNBZPPfcNjZa5uI79KkJxq5esCtVNt/pf2DF4=; b=B3YI7KWQBzzPirhueg0Y4FP+swR7rBAu+MWHP4YpU+sGHKo/kUjKDGkCpEzczH87qc/QhIka2 B60vBX1oqjgDzindHyBmrnyp1s2NwPm++D2kOiKV4dLgTCeZYz/CqIX X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu When the clk_disable_unused_subtree() function disables an unused clock, if CLK_OPS_PARENT_ENABLE is configured on the clock, clk_core_prepare_enable() and clk_core_disable_unprepare() are called directly, and these two functions do not determine CLK_IGNORE_UNUSED, This causes the clock to be disabled even if CLK_IGNORE_UNUSED is configured when clk_core_disable_unprepare() is called. Two new functions clk_disable_unprepare_unused() and clk_prepare_enable_unused() are added to resolve the preceding situation. The CLK_IGNORE_UNUSED judgment logic is added to these two functions. To prevent clock configuration CLK_IGNORE_UNUSED from possible failure. Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)") Signed-off-by: Chuan Liu --- drivers/clk/clk.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index d02451f951cf..6def76c30ce6 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -94,6 +94,7 @@ struct clk_core { struct hlist_node debug_node; #endif struct kref ref; + bool ignore_enabled; }; #define CREATE_TRACE_POINTS @@ -1479,6 +1480,68 @@ static void __init clk_unprepare_unused_subtree(struct clk_core *core) } } +static void __init clk_disable_unprepare_unused(struct clk_core *core) +{ + unsigned long flags; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return; + + if ((core->enable_count == 0) && core->ops->disable && + !core->ignore_enabled) { + flags = clk_enable_lock(); + core->ops->disable(core->hw); + clk_enable_unlock(flags); + } + + if ((core->prepare_count == 0) && core->ops->unprepare && + !core->ignore_enabled) + core->ops->unprepare(core->hw); + + core->ignore_enabled = false; + + clk_disable_unprepare_unused(core->parent); +} + +static int __init clk_prepare_enable_unused(struct clk_core *core) +{ + int ret = 0; + unsigned long flags; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + ret = clk_prepare_enable_unused(core->parent); + if (ret) + return ret; + + if ((core->flags & CLK_IGNORE_UNUSED) && clk_core_is_enabled(core)) + core->ignore_enabled = true; + + if ((core->prepare_count == 0) && core->ops->prepare) { + ret = core->ops->prepare(core->hw); + if (ret) + goto disable_unprepare; + } + + if ((core->enable_count == 0) && core->ops->enable) { + flags = clk_enable_lock(); + ret = core->ops->enable(core->hw); + clk_enable_unlock(flags); + if (ret) + goto disable_unprepare; + } + + return 0; +disable_unprepare: + clk_disable_unprepare_unused(core->parent); + return ret; +} + static void __init clk_disable_unused_subtree(struct clk_core *core) { struct clk_core *child; @@ -1490,7 +1553,7 @@ static void __init clk_disable_unused_subtree(struct clk_core *core) clk_disable_unused_subtree(child); if (core->flags & CLK_OPS_PARENT_ENABLE) - clk_core_prepare_enable(core->parent); + clk_prepare_enable_unused(core->parent); flags = clk_enable_lock(); @@ -1517,7 +1580,7 @@ static void __init clk_disable_unused_subtree(struct clk_core *core) unlock_out: clk_enable_unlock(flags); if (core->flags & CLK_OPS_PARENT_ENABLE) - clk_core_disable_unprepare(core->parent); + clk_disable_unprepare_unused(core->parent); } static bool clk_ignore_unused __initdata; From patchwork Mon Nov 11 03:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuan Liu via B4 Relay X-Patchwork-Id: 13870206 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CCB7145346; Mon, 11 Nov 2024 03:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 11 Nov 2024 03:37:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731296229; bh=O0/vpbhe7rf42WvVAzr8V4TxhY556ffdiUaI+owMnFY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HeB7BBCbv20JwbG6421LaFzYPya9Vj1XqFoGnOveXxPdy53o5rjZfr5ibWojEgOpt esZbTprJd2nYYp0oI9E15kq062ivRhl27CFBj466hAG/83ZspGlpwagXocQ7uUCebG uj7kcOgre5gXhK/Zi+BLsGvU2WJXwC2ErBzVlB7Ym8WMclBtwY3kNt6u5lSUl8avt0 tdDkZZgOF8EFyB3KDRwKwfUb/NcJdDL0mb1Sbq4q/jLnSI7GGqp4uiVZ+w8pADliGr nQNA0AVf4QWTUsbRvSe096rLl9q6m7dKyF9LqCoYyX46yx1lYx1UuNsLCDE9ipZKCU FtK9SR+dBdRvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB31FD12D68; Mon, 11 Nov 2024 03:37:09 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Mon, 11 Nov 2024 11:37:02 +0800 Subject: [PATCH v2 2/3] clk: meson: Fix failure of glitch-free mux switching Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241111-fix_glitch_free-v2-2-0099fd9ad3e5@amlogic.com> References: <20241111-fix_glitch_free-v2-0-0099fd9ad3e5@amlogic.com> In-Reply-To: <20241111-fix_glitch_free-v2-0-0099fd9ad3e5@amlogic.com> To: Michael Turquette , Stephen Boyd , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731296227; l=8711; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=atOOThnlnG3IFHNRk0s4v4QFpYbDw+X8nwyi0iZYZHw=; b=SJ1Q58UzUoM28/g8A6L/ubJfjIKtacTu0tk72GbNpWLNgK6hW40Oq2r5sb6/GSwCPAYn9n5IR 1xi5qyyqFFzDkH/huhC6vUketMMfDWvwWb7c2HVS5jgIb+1DFuMSl97 X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu glitch-free mux has two clock channels (channel 0 and channel 1) with the same configuration.Channel 0 of glitch-free mux is not only the clock source for the mux, but also the working clock for glitch free mux. Therefore, when glitch-free mux switches, it is necessary to ensure that channel 0 has a clock input, otherwise glitch free mux will not work and cannot switch to the target channel. So adding flag CLK_OPS_PARENT_ENABLE ensures that both channels 0 and 1 are enabled when mux switches. In fact, we just need to make sure that channel 0 is enabled. The purpose of CLK_OPS_PARENT_ENABLE may not be to solve our situation, but adding this flag does solve our current problem. Fixes: 84af914404db ("clk: meson: a1: add Amlogic A1 Peripherals clock controller driver") Fixes: 14ebb3154b8f ("clk: meson: axg: add Video Clocks") Fixes: f06ac3ed04e8 ("clk: meson: c3: add c3 clock peripherals controller driver") Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Fixes: fac9a55b66c9 ("clk: meson-gxbb: Add MALI clocks") Fixes: 74e1f2521f16 ("clk: meson: meson8b: add the GPU clock tree") Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller") Signed-off-by: Chuan Liu --- drivers/clk/meson/a1-peripherals.c | 4 ++-- drivers/clk/meson/axg.c | 4 ++-- drivers/clk/meson/c3-peripherals.c | 2 +- drivers/clk/meson/g12a.c | 6 +++--- drivers/clk/meson/gxbb.c | 6 +++--- drivers/clk/meson/meson8b.c | 21 ++++++++++++++++++--- drivers/clk/meson/s4-peripherals.c | 12 ++++++------ 7 files changed, 35 insertions(+), 20 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c index 7aa6abb2eb1f..4b9686916b17 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -489,7 +489,7 @@ static struct clk_regmap dspa_sel = { &dspa_b.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -635,7 +635,7 @@ static struct clk_regmap dspb_sel = { &dspb_b.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 1b08daf579b2..a1217dff40fa 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1144,7 +1144,7 @@ static struct clk_regmap axg_vpu = { &axg_vpu_1.hw }, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -1260,7 +1260,7 @@ static struct clk_regmap axg_vapb_sel = { &axg_vapb_1.hw }, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, }, }; diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peripherals.c index 7dcbf4ebee07..4566c2aeeb19 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -1431,7 +1431,7 @@ static struct clk_regmap hcodec = { .ops = &clk_regmap_mux_ops, .parent_data = hcodec_parent_data, .num_parents = ARRAY_SIZE(hcodec_parent_data), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d3539fe9f7af..4d3b064d09fc 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -2812,7 +2812,7 @@ static struct clk_regmap g12a_vpu = { &g12a_vpu_1.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -3105,7 +3105,7 @@ static struct clk_regmap g12a_vapb_sel = { &g12a_vapb_1.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -4039,7 +4039,7 @@ static struct clk_regmap g12a_mali = { .ops = &clk_regmap_mux_ops, .parent_hws = g12a_mali_parent_hws, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 262c318edbd5..dfa9ffc61b41 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -1132,7 +1132,7 @@ static struct clk_regmap gxbb_mali = { .ops = &clk_regmap_mux_ops, .parent_hws = gxbb_mali_parent_hws, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -1613,7 +1613,7 @@ static struct clk_regmap gxbb_vpu = { &gxbb_vpu_1.hw }, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -1748,7 +1748,7 @@ static struct clk_regmap gxbb_vapb_sel = { &gxbb_vapb_1.hw }, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, }, }; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index e4b474c5f86c..0af76b527e5b 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1997,7 +1997,22 @@ static struct clk_regmap meson8b_mali = { &meson8b_mali_1.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + /* + * glitch-free mux has two clock channels (channel 0 and + * channel 1) with the same configuration.Channel 0 of + * glitch-free mux is not only the clock source for the mux, + * but also the working clock for glitch free mux. Therefore, + * when glitch-free mux switches, it is necessary to ensure that + * channel 0 has a clock input, otherwise glitch free mux will + * not work and cannot switch to the target channel. So adding + * flag CLK_OPS_PARENT_ENABLE ensures that both channels 0 and 1 + * are enabled when mux switches. + * + * In fact, we just need to make sure that channel 0 is enabled. + * The purpose of CLK_OPS_PARENT_ENABLE may not be to solve our + * situation, but adding this flag does solve our current problem. + */ + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -2252,7 +2267,7 @@ static struct clk_regmap meson8b_vpu = { &meson8b_vpu_1.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -2364,7 +2379,7 @@ static struct clk_regmap meson8b_vdec_1 = { &meson8b_vdec_1_2.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c index c930cf0614a0..79e0240d58e6 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -1404,7 +1404,7 @@ static struct clk_regmap s4_mali_mux = { .ops = &clk_regmap_mux_ops, .parent_hws = s4_mali_parent_hws, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -1536,7 +1536,7 @@ static struct clk_regmap s4_vdec_mux = { .ops = &clk_regmap_mux_ops, .parent_hws = s4_vdec_mux_parent_hws, .num_parents = ARRAY_SIZE(s4_vdec_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -1656,7 +1656,7 @@ static struct clk_regmap s4_hevcf_mux = { .ops = &clk_regmap_mux_ops, .parent_hws = s4_hevcf_mux_parent_hws, .num_parents = ARRAY_SIZE(s4_hevcf_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -1774,7 +1774,7 @@ static struct clk_regmap s4_vpu = { &s4_vpu_1.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -1989,7 +1989,7 @@ static struct clk_regmap s4_vpu_clkc_mux = { .ops = &clk_regmap_mux_ops, .parent_hws = s4_vpu_mux_parent_hws, .num_parents = ARRAY_SIZE(s4_vpu_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; @@ -2115,7 +2115,7 @@ static struct clk_regmap s4_vapb = { &s4_vapb_1.hw }, .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, }; From patchwork Mon Nov 11 03:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuan Liu via B4 Relay X-Patchwork-Id: 13870207 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CC5D14037F; Mon, 11 Nov 2024 03:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731296230; cv=none; b=gtq/x3pvm1CQeQ0N9mleCa4KQxD/phngbBKscmL74MmXMV0ZXq0Q6IfZLkqBXeJiLEN7jfqo7HZIjSI0kAFIA0SSwLCFhuJyz25XbVuSWm/cdZtfDH4a6u79NHq/MmVqCe5gNhB1mS8jX4v5di0T63OU/3mcfQVs7H/knDNNB/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731296230; c=relaxed/simple; bh=nYbSMyAY5KMAdoS2ugyZMdKHOHfvsmdyGjahtE6WqS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e45kwPrKkMEEcsznp2zegwco4kuYVm0uf4iK4qXdFwIcjC9XdOKhHsMOXKGGTRqjipAIvWhWMVEmx2FqA5S1+26q8aq1CiPi/pFZmJsYud2LoMNkDqWVS17rzmvhh0dZXnUiWkfKBeH0YVb6i6gl8ZfnYJYDUaYBn+hUhSmROf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=All2Leeu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="All2Leeu" Received: by smtp.kernel.org (Postfix) with ESMTPS id EC7A4C4CED9; Mon, 11 Nov 2024 03:37:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731296230; bh=nYbSMyAY5KMAdoS2ugyZMdKHOHfvsmdyGjahtE6WqS0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=All2Leeub2vLtkgMokXyxiO17uyb510PsqDL8/nWLB0BSlJBmZWs4Cufvkn3lNESB lNye+Bg0HIxqK0dlbf9D0WXF5gf2b0Mczr0wmj9oirRfZ4UCqPzzSHlf9kdgeSWTif 1x5z9vRHxPVmDGUdnMsuo/HZIxoujL1ur7WBJS8B4wRpLqyBT4A5ZfqteKdvWYtDxC 6sua9wLn5TfI6Ud4R4tdIjzHyIVk2f6fHf3oI72NW6/dFnzG8XHVxi9Wqovz8bBtjx Lx50OLnUg2PxFce1Vz7Z7/zj+jd5pE7YlQBJhpUYYkX2YxIOclHB/z3Hot4bd9w7j9 uAPuvdp272ljw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE0A1D12D6A; Mon, 11 Nov 2024 03:37:09 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Mon, 11 Nov 2024 11:37:03 +0800 Subject: [PATCH v2 3/3] clk: meson: Fix glitch occurs when setting up glitch-free mux Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241111-fix_glitch_free-v2-3-0099fd9ad3e5@amlogic.com> References: <20241111-fix_glitch_free-v2-0-0099fd9ad3e5@amlogic.com> In-Reply-To: <20241111-fix_glitch_free-v2-0-0099fd9ad3e5@amlogic.com> To: Michael Turquette , Stephen Boyd , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731296227; l=9556; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=14bGE9sYOEx+b5MpaosDAU5c7E9221JER7/akkkpyQI=; b=87LGzbmMRXSyu8oy0ZGzgmHOdsqYg9UC7pAj0lFPfWns456G42M1cSzMH6cVTq9gMqpYri+rx /dcbvMA+08ACSttJ7amw9V9S8vQysAH2+fQWaMFVAEyERZpvfPVoHnp X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu glitch-free mux has two clock channels (channel 0 and channel 1) with the same configuration. When the frequency needs to be changed, the two channels ping-pong to ensure clock continuity and suppress glitch. The glitch-free mux configuration with CLK_SET_RATE_GATE enables the mux to perform ping-pong switching to suppress glitches. Fixes: 84af914404db ("clk: meson: a1: add Amlogic A1 Peripherals clock controller driver") Fixes: 14ebb3154b8f ("clk: meson: axg: add Video Clocks") Fixes: f06ac3ed04e8 ("clk: meson: c3: add c3 clock peripherals controller driver") Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Fixes: fac9a55b66c9 ("clk: meson-gxbb: Add MALI clocks") Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller") Signed-off-by: Chuan Liu --- drivers/clk/meson/a1-peripherals.c | 8 ++++---- drivers/clk/meson/axg.c | 12 ++++++++---- drivers/clk/meson/c3-peripherals.c | 4 ++-- drivers/clk/meson/g12a.c | 12 ++++++++---- drivers/clk/meson/gxbb.c | 12 ++++++++---- drivers/clk/meson/s4-peripherals.c | 20 ++++++++++---------- 6 files changed, 40 insertions(+), 28 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c index 4b9686916b17..7f515e002adb 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -423,7 +423,7 @@ static struct clk_regmap dspa_a = { &dspa_a_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -471,7 +471,7 @@ static struct clk_regmap dspa_b = { &dspa_b_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -569,7 +569,7 @@ static struct clk_regmap dspb_a = { &dspb_a_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -617,7 +617,7 @@ static struct clk_regmap dspb_b = { &dspb_b_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index a1217dff40fa..e2d3266f4b45 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1077,7 +1077,8 @@ static struct clk_regmap axg_vpu_0 = { * We want to avoid CCF to disable the VPU clock if * display has been set by Bootloader */ - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -1126,7 +1127,8 @@ static struct clk_regmap axg_vpu_1 = { * We want to avoid CCF to disable the VPU clock if * display has been set by Bootloader */ - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -1194,7 +1196,8 @@ static struct clk_regmap axg_vapb_0 = { &axg_vapb_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -1242,7 +1245,8 @@ static struct clk_regmap axg_vapb_1 = { &axg_vapb_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peripherals.c index 4566c2aeeb19..27343a73a521 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -1364,7 +1364,7 @@ static struct clk_regmap hcodec_0 = { &hcodec_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1411,7 +1411,7 @@ static struct clk_regmap hcodec_1 = { &hcodec_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 4d3b064d09fc..21a25001e904 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -2746,7 +2746,8 @@ static struct clk_regmap g12a_vpu_0 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -2790,7 +2791,8 @@ static struct clk_regmap g12a_vpu_1 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -3035,7 +3037,8 @@ static struct clk_regmap g12a_vapb_0 = { &g12a_vapb_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -3083,7 +3086,8 @@ static struct clk_regmap g12a_vapb_1 = { &g12a_vapb_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index dfa9ffc61b41..812b3e20c366 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -1543,7 +1543,8 @@ static struct clk_regmap gxbb_vpu_0 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -1591,7 +1592,8 @@ static struct clk_regmap gxbb_vpu_1 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -1674,7 +1676,8 @@ static struct clk_regmap gxbb_vapb_0 = { &gxbb_vapb_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; @@ -1726,7 +1729,8 @@ static struct clk_regmap gxbb_vapb_1 = { &gxbb_vapb_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | + CLK_SET_RATE_GATE, }, }; diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c index 79e0240d58e6..cf10be40141d 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -1466,7 +1466,7 @@ static struct clk_regmap s4_vdec_p0 = { &s4_vdec_p0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1516,7 +1516,7 @@ static struct clk_regmap s4_vdec_p1 = { &s4_vdec_p1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1586,7 +1586,7 @@ static struct clk_regmap s4_hevcf_p0 = { &s4_hevcf_p0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1636,7 +1636,7 @@ static struct clk_regmap s4_hevcf_p1 = { &s4_hevcf_p1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1712,7 +1712,7 @@ static struct clk_regmap s4_vpu_0 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1756,7 +1756,7 @@ static struct clk_regmap s4_vpu_1 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1921,7 +1921,7 @@ static struct clk_regmap s4_vpu_clkc_p0 = { &s4_vpu_clkc_p0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -1969,7 +1969,7 @@ static struct clk_regmap s4_vpu_clkc_p1 = { &s4_vpu_clkc_p1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -2049,7 +2049,7 @@ static struct clk_regmap s4_vapb_0 = { &s4_vapb_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; @@ -2097,7 +2097,7 @@ static struct clk_regmap s4_vapb_1 = { &s4_vapb_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, };