From patchwork Mon Nov 11 05:59:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13870250 Received: from mail-oi1-f173.google.com (mail-oi1-f173.google.com [209.85.167.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC7FF137747; Mon, 11 Nov 2024 05:59:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304790; cv=none; b=HgvDoLmw1tXkNvmDnxmEOr+fYWCu7yqVZ7XkFRDWtYwnIkTU5IG3jYQd2WM2zeYy5AL6OuCZMDPDxJ0UFhStyllyS+DeNMm9HHII7W8yWyi0B+hhizleZHYNLi0e4NWaOm5jW1trZJ1+p7AwSjjmbjBQFNzgZWiHK1mA2alu4FM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304790; c=relaxed/simple; bh=IQsklxW9iHWbBpzddygNMjibIkcbcEsUQQJBhcrEPgE=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Dk28hmYYTh2HMVuGhuL/MGvYMj/ypr1nTfPon3SFYUlcwZUFojdUQnqQuwglXN3LQ52D4xSqhUW1jx02O2iJkbVEIFwd82Jvq++/JvQJdvb46x/fDP5ATtIqRlJpaCs27lLs/Iooy52Nt5X5G4BmEyYYkQ93vznfS0L4G35dhNk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=doKwgEWB; arc=none smtp.client-ip=209.85.167.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="doKwgEWB" Received: by mail-oi1-f173.google.com with SMTP id 5614622812f47-3e601b6a33aso2403568b6e.0; Sun, 10 Nov 2024 21:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731304788; x=1731909588; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AcDsTsbAoHrjuJNrpeEiHIIXwt512iaJZ1liGpvMOf8=; b=doKwgEWBQqzyAyjmhn8gQPVwamdGNFvKFfquwWdPOt4aYlfNqvX7LnyEdjUb+yxRMg q+0PFQ8ZalTd7JpG3VQ5uKobVt0EChGncH0DdyL/tsRoflrt38vHuSpseV7ZeD1xXe4v aZEjmB25QDNu0luypULhjJdFvs4iJrMXcICh8V+pgxd2AIaWDUBjIaGT9tCQ2mq1WpaY QlTxcT/jfeWHPJqn0uSCwuRn89xEeGQN7ryg3wHMee4GyAgT8upvgVu+ElkPfkmyUV3Z ui7ksqF/AsxI3Yu5hwfIUYuFhw3OIB4jDVvuW3PVSXLJ4hBhStcZoF+JD8/GqzzlZsf9 U+2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731304788; x=1731909588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AcDsTsbAoHrjuJNrpeEiHIIXwt512iaJZ1liGpvMOf8=; b=HLi21EYEb+mKeyDV6BptXVRYS8EbiLxGPUXFzGFxx7RMBBp7xRlDrylv1TyPAcXFQT jBiqSJ2WFCz11p7dt46g+rIXub9AcaO0U3LJNQ0G5hoKJb3DrXgeqjh0MUi4yZg0q3Pd MEyPP/UiS1WLwkgO6V9Wfb3bBPbWJJhLf97O9eW8/zae0LDlYi8b7fhkBQyhoyv6CCXA OVc7/YHHd6kEZZfsae1DLq0evokOoQwuvf/w5Uct66tlwyV+n2rYQ9HsN87TPidPLdlE R6ajYKAFaXHqqItgULWXzwzWB3iFD1rNQKks0/QTvqPYUNuZJC48MJKzWFThi1zXJVEc eHbA== X-Forwarded-Encrypted: i=1; AJvYcCU02MOPBSkt1EqI4aI3dzOKRSJr0ZupRvHhLaZB/2dQz1rPd0QNHzgtA4tF86bKpPnrSsunEoNaIE6gsXfD@vger.kernel.org, AJvYcCWfVViEgShBcsfbvZMUgTwXvtIPrgOi/Qz//aUyGs9OLeN6mD7FQVet0M5ZMFc8+qi5tW23qH3pt1RW@vger.kernel.org, AJvYcCXOeASqKYQX0eRMEcxADokJUHY1VPmsKRz2GdYffrJNsAcKfp8P9v4rn7ljT9a3f2GwBmoDqWZXXWXn@vger.kernel.org X-Gm-Message-State: AOJu0Yw86TXXWj+5vu33PpD0pZ13OcNZt3j6Auu55br7Q5RwhzIxn7aq 2SYS7TBvaphMmAqwoV1dnGYE1Cqh4cvDv2AyE0cPNqqAZN9uU7j/ X-Google-Smtp-Source: AGHT+IGGuV49WNiTojEUmDK73Hy2JmrVXWdZzG5Wfg2sJpT+JoDVwiKHPnfkhzuQPC7X4Wfwh+9GrQ== X-Received: by 2002:a05:6808:3012:b0:3e6:2408:6117 with SMTP id 5614622812f47-3e7946687f7mr9876627b6e.13.1731304787650; Sun, 10 Nov 2024 21:59:47 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3e78cd706a5sm1971906b6e.54.2024.11.10.21.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 21:59:46 -0800 (PST) From: Chen Wang To: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host Date: Mon, 11 Nov 2024 13:59:37 +0800 Message-Id: <1edbed1276a459a144f0cb0815859a1eb40bfcbf.1731303328.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Add binding for Sophgo SG2042 PCIe host controller. Signed-off-by: Chen Wang --- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml new file mode 100644 index 000000000000..d4d2232f354f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) + +description: |+ + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. + It shares common features with the PCIe core and inherits common properties + defined in Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml. + +maintainers: + - Chen Wang + +properties: + compatible: + const: sophgo,sg2042-pcie-host + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: cfg + + sophgo,syscon-pcie-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the SYSCON entry + + sophgo,link-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cadence IP link ID. + + sophgo,internal-msi: + $ref: /schemas/types.yaml#/definitions/flag + description: Identifies whether the PCIE node uses internal MSI controller. + + vendor-id: + const: 0x1f1c + + device-id: + const: 0x2042 + + interrupts: + maxItems: 1 + + interrupt-names: + const: msi + +allOf: + - $ref: cdns-pcie-host.yaml# + +required: + - compatible + - reg + - reg-names + - sophgo,syscon-pcie-ctrl + - sophgo,link-id + - vendor-id + - device-id + - ranges + +additionalProperties: true + +examples: + - | + pcie@62000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x62000000 0x00800000>, + <0x48000000 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + bus-range = <0x80 0xbf>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <0>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; + sophgo,internal-msi; + interrupt-parent = <&intc>; + }; From patchwork Mon Nov 11 05:59:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13870251 Received: from mail-oi1-f174.google.com (mail-oi1-f174.google.com [209.85.167.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C1417F477; Mon, 11 Nov 2024 06:00:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304809; cv=none; b=hyaD3pnLU6INM9uxt8PP6VSI9rhT265T7NChgO4lHWI7b4ZEbdy3rgJdnMMAeAaVde2nedGInCzKMcmP/YxDiUYTfy1q/jG/lcAvmZ4/i3rUTg+VlJDqqJQW3HSHYcVvL2KhQWVeL+6rlxZufDIv0RzAOkHHmYIMcBJQAPb+abk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304809; c=relaxed/simple; bh=DdAdT+H4NWuTmq02p5pMjKVRqdMYBZLMH24DDbJ0dvE=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YL11uyFEtrdJmO8liFWVfGr++YZF8zBir4NU8MD4kxezU1vw4n3fIDIypqStf6I6Q8QFxTuU3CWkHWc9MoXrC1pI0XMvgZGTwlHJJ1iLAlZb6w0FF1z3JQu2Bi/7pVT3nbH/Tb+sUZazBmWvo2yQn2vPqzUzVP5iJ+VM/Ke2ARA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=U+qFU4pT; arc=none smtp.client-ip=209.85.167.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="U+qFU4pT" Received: by mail-oi1-f174.google.com with SMTP id 5614622812f47-3e5f6e44727so2652515b6e.0; Sun, 10 Nov 2024 22:00:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731304806; x=1731909606; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yTvANXTv/aWffsiW3Z8BnaLjvFYPVRyPf6OKa3zX8yI=; b=U+qFU4pTt6epQ9vrpSHypbuEG0s18uRmqoOHD+vDA7jBdtgZnQYGlFwWVU+fKf+xny Gs54ABlG45GTU7asqd+NEltSwZsVdBXCWe5f/xjRH5fMIbQl7Xv2TFWIPZ3HONL5HlwQ vWxDM+7ZaLcl49Z0yCn8TzInyQazsRYxBdKT1LC9d8+aCPV7UMhPQJJj5tH4eDOFmsYA hZafDGImar/zOznm1q9BiLYvJnBGeGUklrJJusT7et7bPi5a/94/VPBW7X6TB8T/xLio NimDuUZHQmz0ZhJ/TPeD8OdoLNBEY2x296pVddpx6yy6RiuFcgv0vASOqOZgzhwCE9k1 PMHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731304806; x=1731909606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yTvANXTv/aWffsiW3Z8BnaLjvFYPVRyPf6OKa3zX8yI=; b=jdLB8W4jEeD2CCxteuJOUHswH0RwkUi0sSiMF0dwnx06iLWZAvpwiOfP6++AxHpSFd 3568oioOjxz8nEkZFmrQH+oCPVHtL0KvcemS5z4+2v6Y28Am6ailixN0uMyU0AXyXnzv byTgwUzkxt2eDAP/fZKHkWH5b7eoC40XIV+HvM2GtOFl4FXvdd6rppllPBKQv1otCs9F MFf0qVIX7bm/I3ovhomkQwu62YQ5vv/1L2eAk3jrar87qEyoHUuzo9nqEKAgC8mg8mT9 T/Xw8alOLoB4iu0bPuwkBh0V3t0U+cWCeypeSUDM5TKmujwa+cb6LFUx+Qy4PorT6ME6 8GFg== X-Forwarded-Encrypted: i=1; AJvYcCW0Ve7u+/WV/qfD0d4RzyYcLMqYhGAiJHUaCPht2Forf9jOuVXaww19H2KUESTtSEzB+8NmFXdDNXQL54Wf@vger.kernel.org, AJvYcCWL+Il8CO3JZV5yBwfB9RwuMAH91LVZoAITZt3f9R5oeGoT7wMiuZV5hMeWP35kEJy9ikcRHvQgvhVI@vger.kernel.org, AJvYcCWZP5RZbuR9gyOruytQgfsgt1wjC/+PsKRGMUHgdodqYeObcFmBaU6PFySlEVUZaO3TNRnGml+lAYTP@vger.kernel.org X-Gm-Message-State: AOJu0YxpEsxD3457Bf59DVWnJOQzcaKqhCk8UP4o1zXl1LPxjU9v2ru5 Uxbb5lhzF9lKTljThOaNaLJ6F1niEBFOXH/rNfIDwEGsdeJA6YUq X-Google-Smtp-Source: AGHT+IE3v9OKk7/ZZ1EhbQsAltY55IOxcpt4L/XvmjK+OgLTOKKEVpwX2jTyucXcN5dpWcFx1TPARA== X-Received: by 2002:a05:6808:1794:b0:3e6:3878:13c4 with SMTP id 5614622812f47-3e79468354bmr9275319b6e.2.1731304805752; Sun, 10 Nov 2024 22:00:05 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3e78cc67520sm1981181b6e.9.2024.11.10.22.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 22:00:04 -0800 (PST) From: Chen Wang To: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 2/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver Date: Mon, 11 Nov 2024 13:59:56 +0800 Message-Id: <5051f2375ff6218e7d44ce0c298efd5f9ee56964.1731303328.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Add support for PCIe controller in SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in host mode only. Signed-off-by: Chen Wang --- drivers/pci/controller/cadence/Kconfig | 11 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pcie-sg2042.c | 611 +++++++++++++++++++ 3 files changed, 623 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 8a0044bb3989..45a16215ea94 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -67,4 +67,15 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + +config PCIE_SG2042 + bool "Sophgo SG2042 PCIe controller (host mode)" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on OF + select PCIE_CADENCE_HOST + help + Say Y here if you want to support the Sophgo SG2042 PCIe platform + controller in host mode. Sophgo SG2042 PCIe controller uses Cadence + PCIe core. + endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 9bac5fb2f13d..89aa316f54ac 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o +obj-$(CONFIG_PCIE_SG2042) += pcie-sg2042.o \ No newline at end of file diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c new file mode 100644 index 000000000000..809edb8e7259 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-sg2042.c @@ -0,0 +1,611 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" + +/* + * SG2042 PCIe controller supports two ways to report MSI: + * - Method A, the PICe controller implements an MSI interrupt controller inside, + * and connect to PLIC upward through one interrupt line. Provides + * memory-mapped msi address, and by programming the upper 32 bits of the + * address to zero, it can be compatible with old pcie devices that only + * support 32-bit msi address. + * - Method B, the PICe controller connects to PLIC upward through an + * independent MSI controller "sophgo,sg2042-msi" on the SOC. The MSI + * controller provides multiple(up to 32) interrupt sources to PLIC. + * Compared with the first method, the advantage is that the interrupt source + * is expanded, but because for SG2042, the msi address provided by the MSI + * controller is fixed and only supports 64-bit address(> 2^32), it is not + * compatible with old pcie devices that only support 32-bit msi address. + * Method A & B can be configured in DTS with property "sophgo,internal-msi", + * default is Method B. + */ + +#define MAX_MSI_IRQS 8 +#define MAX_MSI_IRQS_PER_CTRL 1 +#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) +#define MSI_DEF_NUM_VECTORS MAX_MSI_IRQS +#define BYTE_NUM_PER_MSI_VEC 4 + +#define REG_CLEAR 0x0804 +#define REG_STATUS 0x0810 +#define REG_LINK0_MSI_ADDR_SIZE 0x085C +#define REG_LINK1_MSI_ADDR_SIZE 0x080C +#define REG_LINK0_MSI_ADDR_LOW 0x0860 +#define REG_LINK0_MSI_ADDR_HIGH 0x0864 +#define REG_LINK1_MSI_ADDR_LOW 0x0868 +#define REG_LINK1_MSI_ADDR_HIGH 0x086C + +#define REG_CLEAR_LINK0_BIT 2 +#define REG_CLEAR_LINK1_BIT 3 +#define REG_STATUS_LINK0_BIT 2 +#define REG_STATUS_LINK1_BIT 3 + +#define REG_LINK0_MSI_ADDR_SIZE_MASK GENMASK(15, 0) +#define REG_LINK1_MSI_ADDR_SIZE_MASK GENMASK(31, 16) + +#define SG2042_CDNS_PLAT_CPU_TO_BUS_ADDR 0xCFFFFFFFFF + +struct sg2042_pcie { + struct cdns_pcie *cdns_pcie; + + struct regmap *syscon; + + u32 link_id; + u32 internal_msi; /* Flag if use internal MSI controller, default external */ + + struct irq_domain *msi_domain; + + int msi_irq; + + dma_addr_t msi_phys; + void *msi_virt; + + u32 num_applied_vecs; /* number of applied vectors, used to speed up ISR */ + + raw_spinlock_t lock; + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); +}; + +static void sg2042_pcie_msi_irq_mask_external(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void sg2042_pcie_msi_irq_unmask_external(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip sg2042_pcie_msi_chip_external = { + .name = "SG2042 PCIe MSI External", + .irq_ack = irq_chip_ack_parent, + .irq_mask = sg2042_pcie_msi_irq_mask_external, + .irq_unmask = sg2042_pcie_msi_irq_unmask_external, +}; + +static struct msi_domain_info sg2042_pcie_msi_domain_info_external = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .chip = &sg2042_pcie_msi_chip_external, +}; + +static struct irq_chip sg2042_pcie_msi_chip = { + .name = "SG2042 PCIe MSI", + .irq_ack = irq_chip_ack_parent, +}; + +static struct msi_domain_info sg2042_pcie_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .chip = &sg2042_pcie_msi_chip, +}; + +static void sg2042_pcie_msi_clear_status(struct sg2042_pcie *pcie) +{ + u32 status, clr_msi_in_bit; + + if (pcie->link_id == 1) + clr_msi_in_bit = BIT(REG_CLEAR_LINK1_BIT); + else + clr_msi_in_bit = BIT(REG_CLEAR_LINK0_BIT); + + regmap_read(pcie->syscon, REG_CLEAR, &status); + status |= clr_msi_in_bit; + regmap_write(pcie->syscon, REG_CLEAR, status); + + /* need write 0 to reset, hardware can not reset automatically */ + status &= ~clr_msi_in_bit; + regmap_write(pcie->syscon, REG_CLEAR, status); +} + +static int sg2042_pcie_msi_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask, + bool force) +{ + if (d->parent_data) + return irq_chip_set_affinity_parent(d, mask, force); + + return -EINVAL; +} + +static void sg2042_pcie_msi_irq_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + struct sg2042_pcie *pcie = irq_data_get_irq_chip_data(d); + struct device *dev = pcie->cdns_pcie->dev; + + msg->address_lo = lower_32_bits(pcie->msi_phys) + BYTE_NUM_PER_MSI_VEC * d->hwirq; + msg->address_hi = upper_32_bits(pcie->msi_phys); + msg->data = 1; + + pcie->num_applied_vecs = d->hwirq; + + dev_info(dev, "compose msi msg hwirq[%d] address_hi[%#x] address_lo[%#x]\n", + (int)d->hwirq, msg->address_hi, msg->address_lo); +} + +static void sg2042_pcie_msi_irq_ack(struct irq_data *d) +{ + struct sg2042_pcie *pcie = irq_data_get_irq_chip_data(d); + + sg2042_pcie_msi_clear_status(pcie); +} + +static struct irq_chip sg2042_pcie_msi_bottom_chip = { + .name = "SG2042 PCIe PLIC-MSI translator", + .irq_ack = sg2042_pcie_msi_irq_ack, + .irq_compose_msi_msg = sg2042_pcie_msi_irq_compose_msi_msg, +#ifdef CONFIG_SMP + .irq_set_affinity = sg2042_pcie_msi_irq_set_affinity, +#endif +}; + +static int sg2042_pcie_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + struct sg2042_pcie *pcie = domain->host_data; + unsigned long flags; + u32 i; + int bit; + + raw_spin_lock_irqsave(&pcie->lock, flags); + + bit = bitmap_find_free_region(pcie->msi_irq_in_use, MSI_DEF_NUM_VECTORS, + order_base_2(nr_irqs)); + + raw_spin_unlock_irqrestore(&pcie->lock, flags); + + if (bit < 0) + return -ENOSPC; + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_info(domain, virq + i, bit + i, + &sg2042_pcie_msi_bottom_chip, + pcie, handle_edge_irq, + NULL, NULL); + + return 0; +} + +static void sg2042_pcie_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct sg2042_pcie *pcie = irq_data_get_irq_chip_data(d); + unsigned long flags; + + raw_spin_lock_irqsave(&pcie->lock, flags); + + bitmap_release_region(pcie->msi_irq_in_use, d->hwirq, + order_base_2(nr_irqs)); + + raw_spin_unlock_irqrestore(&pcie->lock, flags); +} + +static const struct irq_domain_ops sg2042_pcie_msi_domain_ops = { + .alloc = sg2042_pcie_irq_domain_alloc, + .free = sg2042_pcie_irq_domain_free, +}; + +/* + * We use the usual two domain structure, the top one being a generic PCI/MSI + * domain, the bottom one being SG2042-specific and handling the actual HW + * interrupt allocation. + * At the same time, for internal MSI controller(Method A), bottom chip uses a + * chained handler to handle the controller's MSI IRQ edge triggered. + */ +static int sg2042_pcie_create_msi_domain(struct sg2042_pcie *pcie, + struct irq_domain *parent) +{ + struct device *dev = pcie->cdns_pcie->dev; + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); + + if (pcie->internal_msi) + pcie->msi_domain = pci_msi_create_irq_domain(fwnode, + &sg2042_pcie_msi_domain_info, + parent); + + else + pcie->msi_domain = pci_msi_create_irq_domain(fwnode, + &sg2042_pcie_msi_domain_info_external, + parent); + + if (!pcie->msi_domain) { + dev_err(dev, "Failed to create MSI domain\n"); + return -ENOMEM; + } + + return 0; +} + +static int sg2042_pcie_setup_msi_external(struct sg2042_pcie *pcie) +{ + struct device *dev = pcie->cdns_pcie->dev; + struct device_node *np = dev->of_node; + struct irq_domain *parent_domain; + struct device_node *parent_np; + + if (!of_find_property(np, "interrupt-parent", NULL)) { + dev_err(dev, "Can't find interrupt-parent!\n"); + return -EINVAL; + } + + parent_np = of_irq_find_parent(np); + if (!parent_np) { + dev_err(dev, "Can't find node of interrupt-parent!\n"); + return -ENXIO; + } + + parent_domain = irq_find_host(parent_np); + of_node_put(parent_np); + if (!parent_domain) { + dev_err(dev, "Can't find domain of interrupt-parent!\n"); + return -ENXIO; + } + + return sg2042_pcie_create_msi_domain(pcie, parent_domain); +} + +static int sg2042_pcie_init_msi_data(struct sg2042_pcie *pcie) +{ + struct device *dev = pcie->cdns_pcie->dev; + u32 value; + int ret; + + raw_spin_lock_init(&pcie->lock); + + /* + * Though the PCIe controller can address >32-bit address space, to + * facilitate endpoints that support only 32-bit MSI target address, + * the mask is set to 32-bit to make sure that MSI target address is + * always a 32-bit address + */ + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + if (ret < 0) + return ret; + + pcie->msi_virt = dma_alloc_coherent(dev, BYTE_NUM_PER_MSI_VEC * MAX_MSI_IRQS, + &pcie->msi_phys, GFP_KERNEL); + if (!pcie->msi_virt) + return -ENOMEM; + + /* Program the msi address and size */ + if (pcie->link_id == 1) { + regmap_write(pcie->syscon, REG_LINK1_MSI_ADDR_LOW, + lower_32_bits(pcie->msi_phys)); + regmap_write(pcie->syscon, REG_LINK1_MSI_ADDR_HIGH, + upper_32_bits(pcie->msi_phys)); + + regmap_read(pcie->syscon, REG_LINK1_MSI_ADDR_SIZE, &value); + value = (value & REG_LINK1_MSI_ADDR_SIZE_MASK) | MAX_MSI_IRQS; + regmap_write(pcie->syscon, REG_LINK1_MSI_ADDR_SIZE, value); + } else { + regmap_write(pcie->syscon, REG_LINK0_MSI_ADDR_LOW, + lower_32_bits(pcie->msi_phys)); + regmap_write(pcie->syscon, REG_LINK0_MSI_ADDR_HIGH, + upper_32_bits(pcie->msi_phys)); + + regmap_read(pcie->syscon, REG_LINK0_MSI_ADDR_SIZE, &value); + value = (value & REG_LINK0_MSI_ADDR_SIZE_MASK) | (MAX_MSI_IRQS << 16); + regmap_write(pcie->syscon, REG_LINK0_MSI_ADDR_SIZE, value); + } + + return 0; +} + +static irqreturn_t sg2042_pcie_msi_handle_irq(struct sg2042_pcie *pcie) +{ + u32 i, pos; + unsigned long val; + u32 status, num_vectors; + irqreturn_t ret = IRQ_NONE; + + num_vectors = pcie->num_applied_vecs; + for (i = 0; i <= num_vectors; i++) { + status = readl((void *)(pcie->msi_virt + i * BYTE_NUM_PER_MSI_VEC)); + if (!status) + continue; + + ret = IRQ_HANDLED; + val = status; + pos = 0; + while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, + pos)) != MAX_MSI_IRQS_PER_CTRL) { + generic_handle_domain_irq(pcie->msi_domain->parent, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); + pos++; + } + writel(0, ((void *)(pcie->msi_virt) + i * BYTE_NUM_PER_MSI_VEC)); + } + return ret; +} + +static void sg2042_pcie_msi_chained_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 status, st_msi_in_bit; + struct sg2042_pcie *pcie; + + chained_irq_enter(chip, desc); + + pcie = irq_desc_get_handler_data(desc); + if (pcie->link_id == 1) + st_msi_in_bit = REG_STATUS_LINK1_BIT; + else + st_msi_in_bit = REG_STATUS_LINK0_BIT; + + regmap_read(pcie->syscon, REG_STATUS, &status); + if ((status >> st_msi_in_bit) & 0x1) { + sg2042_pcie_msi_clear_status(pcie); + + sg2042_pcie_msi_handle_irq(pcie); + } + + chained_irq_exit(chip, desc); +} + +static int sg2042_pcie_setup_msi(struct sg2042_pcie *pcie, struct platform_device *pdev) +{ + struct device *dev = pcie->cdns_pcie->dev; + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); + struct irq_domain *parent_domain; + int ret = 0; + + parent_domain = irq_domain_create_linear(fwnode, MSI_DEF_NUM_VECTORS, + &sg2042_pcie_msi_domain_ops, pcie); + if (!parent_domain) { + dev_err(dev, "Failed to create IRQ domain\n"); + return -ENOMEM; + } + irq_domain_update_bus_token(parent_domain, DOMAIN_BUS_NEXUS); + + ret = sg2042_pcie_create_msi_domain(pcie, parent_domain); + if (ret) { + irq_domain_remove(parent_domain); + return ret; + } + + ret = sg2042_pcie_init_msi_data(pcie); + if (ret) { + dev_err(dev, "Failed to initialize msi data!\n"); + return ret; + } + + ret = platform_get_irq_byname(pdev, "msi"); + if (ret <= 0) { + dev_err(dev, "failed to get MSI irq\n"); + return ret; + } + pcie->msi_irq = ret; + + irq_set_chained_handler_and_data(pcie->msi_irq, + sg2042_pcie_msi_chained_isr, pcie); + + return 0; +} + +static void sg2042_pcie_free_msi(struct sg2042_pcie *pcie) +{ + struct device *dev = pcie->cdns_pcie->dev; + + if (pcie->msi_irq) + irq_set_chained_handler_and_data(pcie->msi_irq, NULL, NULL); + + if (pcie->msi_virt) + dma_free_coherent(dev, BYTE_NUM_PER_MSI_VEC * MAX_MSI_IRQS, + pcie->msi_virt, pcie->msi_phys); +} + +static u64 sg2042_cdns_pcie_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) +{ + return cpu_addr & SG2042_CDNS_PLAT_CPU_TO_BUS_ADDR; +} + +static const struct cdns_pcie_ops sg2042_cdns_pcie_ops = { + .cpu_addr_fixup = sg2042_cdns_pcie_cpu_addr_fixup, +}; + +/* + * SG2042 only support 4-byte aligned access, so for the rootbus (i.e. to read + * the PCIe controller itself, read32 is required. For non-rootbus (i.e. to read + * the PCIe peripheral registers, supports 1/2/4 byte aligned access, so + * directly use read should be fine. + * The same is true for write. + */ +static int sg2042_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + if (pci_is_root_bus(bus)) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int sg2042_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + if (pci_is_root_bus(bus)) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + +static struct pci_ops sg2042_pcie_host_ops = { + .map_bus = cdns_pci_map_bus, + .read = sg2042_pcie_config_read, + .write = sg2042_pcie_config_write, +}; + +static int sg2042_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct pci_host_bridge *bridge; + struct device_node *np_syscon; + struct cdns_pcie *cdns_pcie; + struct sg2042_pcie *pcie; + struct cdns_pcie_rc *rc; + struct regmap *syscon; + int ret; + + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) + return -ENODEV; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) { + dev_err(dev, "Failed to alloc host bridge!\n"); + return -ENOMEM; + } + bridge->ops = &sg2042_pcie_host_ops; + + rc = pci_host_bridge_priv(bridge); + cdns_pcie = &rc->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &sg2042_cdns_pcie_ops; + pcie->cdns_pcie = cdns_pcie; + + np_syscon = of_parse_phandle(np, "sophgo,syscon-pcie-ctrl", 0); + if (!np_syscon) { + dev_err(dev, "Failed to get syscon node\n"); + return -ENOMEM; + } + syscon = syscon_node_to_regmap(np_syscon); + if (IS_ERR(syscon)) { + dev_err(dev, "Failed to get regmap for syscon\n"); + return -ENOMEM; + } + pcie->syscon = syscon; + + if (of_property_read_u32(np, "sophgo,link-id", &pcie->link_id)) { + dev_err(dev, "Unable to parse link ID\n"); + return -EINVAL; + } + + pcie->internal_msi = 0; + if (of_property_read_bool(np, "sophgo,internal-msi")) + pcie->internal_msi = 1; + + platform_set_drvdata(pdev, pcie); + + pm_runtime_enable(dev); + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + if (pcie->internal_msi) { + ret = sg2042_pcie_setup_msi(pcie, pdev); + if (ret < 0) + goto err_setup_msi; + } else { + ret = sg2042_pcie_setup_msi_external(pcie); + if (ret < 0) + goto err_setup_msi; + } + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy!\n"); + goto err_setup_msi; + } + + ret = cdns_pcie_host_setup(rc); + if (ret < 0) { + dev_err(dev, "Failed to setup host!\n"); + goto err_host_setup; + } + + return 0; + +err_host_setup: + cdns_pcie_disable_phy(cdns_pcie); + +err_setup_msi: + sg2042_pcie_free_msi(pcie); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return ret; +} + +static void sg2042_pcie_shutdown(struct platform_device *pdev) +{ + struct sg2042_pcie *pcie = platform_get_drvdata(pdev); + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; + struct device *dev = &pdev->dev; + + sg2042_pcie_free_msi(pcie); + + cdns_pcie_disable_phy(cdns_pcie); + + pm_runtime_put(dev); + pm_runtime_disable(dev); +} + +static const struct of_device_id sg2042_pcie_of_match[] = { + { .compatible = "sophgo,sg2042-pcie-host" }, + {}, +}; + +static struct platform_driver sg2042_pcie_driver = { + .driver = { + .name = "sg2042-pcie", + .of_match_table = sg2042_pcie_of_match, + .pm = &cdns_pcie_pm_ops, + }, + .probe = sg2042_pcie_probe, + .shutdown = sg2042_pcie_shutdown, +}; +builtin_platform_driver(sg2042_pcie_driver); From patchwork Mon Nov 11 06:00:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13870252 Received: from mail-ot1-f44.google.com (mail-ot1-f44.google.com [209.85.210.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAD7A482DD; Mon, 11 Nov 2024 06:00:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304826; cv=none; b=lhTniPsgqYBw41khTzjqIXYRhwgdWgDwwkzl8nB20jld4ewYXKlNJ6fwuER76TOT1vNT0b8D/IzgfZ+RvFcy4sOZWH6KBfM+BWvab05MHya+KSV+WAxwZdFGOqp4tqOmEFzuNIzopabRh6/O8fFQR+ViWNOJlqpF/iZadt2nsDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304826; c=relaxed/simple; bh=x35E8KjaM3+OTgr9O3Ohn16lmeATUcDBGMW6GJqFciM=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mn9YRHwNxdcU8Be0Zz0kraP2q5kjmeI2Vunw2V8s8n+y/QvpCLXIMOCHvbSqywK63XfWahb9IRYYOrWhVgME+CFqTu6fbXoeAZI6Xdzt2Mnaa/itMsLiF7lk2MVssfU4zwJ4Te5Zwj57iTwEex6f2YdO18j6LlgusOzCRNb9aPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=W37Msxwu; arc=none smtp.client-ip=209.85.210.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="W37Msxwu" Received: by mail-ot1-f44.google.com with SMTP id 46e09a7af769-718066adb47so2471055a34.0; Sun, 10 Nov 2024 22:00:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731304824; x=1731909624; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HB3qPjMrBpNHrB9kYUUmbwc232oS7W4EAFSAt7K/O60=; b=W37MsxwuDeJ34Pc5PvLaLpNE+EKjXJLAj6qi2tFV+8LVZdf8mH5CeQPSDJIheDwv6J Mj4f2QCfUjibbbx7fKyrehgKslba7H51XDDnMxv6g+w8fBqh/6zDtqY7Yy5uG5TSe7g5 rAg8nVPtdOf6ZViz1iIXnZ5RvkbM5VWP3gkpcXVMHPZpl8+Lo+2eL7pP5amnwBzrGdH1 vhKJcz+eHISlF5L9QlPELxYiNc/xDL+/iiNKGROOV9Eii5CAmJPiVqsqelzmbqSOn3fC evagc7QY4O++xBzk8QdX1NyiliAucWoPnmGoVtgP1NtEtI3Ue3QOakUqF0i9cyJ/okiK Ngbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731304824; x=1731909624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HB3qPjMrBpNHrB9kYUUmbwc232oS7W4EAFSAt7K/O60=; b=SLfH4YkoLi1GDd2POsvS4PQU7mXMRtjBRN62lc0/C5fcYGCpUtCx/pq2hkEZBeDmsc Ryn9g1EdkvYxWTw71JTlg/hbgYlrR8WTJ77JpZ6rdVOq3twSk15PgmYtzwa0GMCxcD7J 08GX6mwAftTqB4mCdyF1G0RcJnJuYUcWg0xji78S7pQDaldjMsZvz2rbbQJRIjsKdl0A Kf6yOXjcgg3gTQHwFxIYhejkyGRx7Qq7/OKbUgObCnaU4gh4EuOOb6qp/BmjOAzOF+N+ kmdjUPFMe3DRecBHZNHs/BH9fy1VckfrrZNBLlFL7IW0Vp9lSil5Ofmp3xeiyZFHW09a Egpw== X-Forwarded-Encrypted: i=1; AJvYcCUsiAJtMU/dnjtohokA/796TNsuFMfj+wuG6Lrp+55eE2efGi8/ftuiGcX46uvgrDzMPnEVXzNMUmfYsbJ8@vger.kernel.org, AJvYcCWDYwf0vY0Qzq28QIGKRTYVyQyLj4Bs6BNdRO0+95MNwa64jkMBhutnigEIeTYxSVZ94kqjxhTbG9ij@vger.kernel.org, AJvYcCX4M2DVgraQ7FAi3dct3vJuaUN/Jc4/Q/0TVCd7NNFwde6/IOWICHDU0wOjchWPfaiUZxvJQQ9tE7Fl@vger.kernel.org X-Gm-Message-State: AOJu0Yzc6RTOF2keYnT6TY4Ha3q7Otsqh/mh1zegMfaZBJNx6WbHZmQm XnwMBRpLPuLtn/bfpAchmm9KLYB2J+F6mnxZxS8+xkznLL9BqySI X-Google-Smtp-Source: AGHT+IHlyAOfWAKE5ev2UjvU1fNznXmdq+01HKo2SJuPfm+QU62k9qG+BkGkD8K2V8IYTqwnw4le0w== X-Received: by 2002:a05:6830:631a:b0:718:bdd:d1d8 with SMTP id 46e09a7af769-71a1c1fc074mr9175544a34.8.1731304823786; Sun, 10 Nov 2024 22:00:23 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71a10920002sm2116864a34.65.2024.11.10.22.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 22:00:22 -0800 (PST) From: Chen Wang To: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible Date: Mon, 11 Nov 2024 14:00:15 +0800 Message-Id: <4f030066767c2a3b3acabe24e3dfbb8d87b42bfe.1731303328.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Document SOPHGO SG2042 compatible for PCIe control registers. These registers are shared by pcie controller nodes. Signed-off-by: Chen Wang Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index cc9b17ad69f2..55f919690001 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -106,6 +106,7 @@ select: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain @@ -203,6 +204,7 @@ properties: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain From patchwork Mon Nov 11 06:00:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13870253 Received: from mail-oi1-f178.google.com (mail-oi1-f178.google.com [209.85.167.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AF146EB7C; Mon, 11 Nov 2024 06:00:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304846; cv=none; b=Yo1p/ySPlEYBG3vOkFiHIokbUNFnIeCV9oRj532/qW94z9364jazerGSW4JQwbOQrCjcVe34iN/zqyvb5GhiNAdkX17RuhpRiKtU4eW9lhIgpMEbys+T5Gls2s0YB5NbHEiBxIhTubB5WCXWDH1cnm1taEXD+fUQQfiDuJAffsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304846; c=relaxed/simple; bh=8/c8h4T6tYg8XhBBU8i8Sf3Fr6JsxUqaQ5ZDI/ympjU=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aDFb6d0X8Uj2VAedj9YoYgrs4162hsePraHkef/aUzdlQXDNcvUaROT4ykS7Adz+IxGapnRuVjLdndS3oozifPVuZ+o6Clakk91Tj2gCxGZKfURuRWK/Ay40IgsRAinrz7LQu4aXw6LjSy7hwMR75NvAvM23UfR7995qEsR4jDQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=l/vZyCx2; arc=none smtp.client-ip=209.85.167.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l/vZyCx2" Received: by mail-oi1-f178.google.com with SMTP id 5614622812f47-3e5f86e59f1so2282237b6e.1; Sun, 10 Nov 2024 22:00:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731304844; x=1731909644; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0rmRpGSKuaRk3Cztraml8ttOGifpWQdN9oAXrvgVN5A=; b=l/vZyCx2yxK7jKUU3Fu0CnSo7B7DRqIiD3nDk1u8YRD0evGOG/RPpDnsdlBj9wKnAI 6jyd699t9rSsaircqttYLQejinWEYH+nTbFUO1lEwqBSdJvMQrOKq0ASKXrhrHMi5slH ETo+wgO8QUTrl3yEgm+ijYLr0UT+1s3MhzSiyOfUyygJsAM3CVoht3BzsR3zG+pOE/vj VO3YHp+n0zrIau8HlWF3jFYjUMn6esPnm3LnOYP5jEBVipAepbMZ76ubUnvM7iNFd8+C lZd9eFmbacly1+cq329q4mzGKfMws3g7JRnz9TOycAKNY6pGHhJn1XCvsxP9+AL/hcs0 aY1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731304844; x=1731909644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0rmRpGSKuaRk3Cztraml8ttOGifpWQdN9oAXrvgVN5A=; b=eP9SDrBhlBHkJkY+h2RRkBB2NzV9I/14wZNxjm3P8qcd22zWHYMxlfdLWsTyef7I0Z OA1NfF6xAjoNRRL4JG7SVS83fkppIJtHOSzLSjpxvc6oR17/unrufJ09dx1ESS1m7jUD JCo9osZfMBqlNQbD62Naq6Ptnl2pvukpu4jqESWOr11X/GHPJmTGYve/b2OqiAquJfD9 Vm62Bp5f8WBWW/JqNrv/mPe2b2fLCxjTejV3P5M989sJklPoOZzpE4v5n89r8X8V8JAr v9R8GcfKemVMZJqTxurOAQQR1TFxToXGtUQ7ltyzZ4BWfKeQ9Wb+vELYCNq5/ekUwwmp 3N4w== X-Forwarded-Encrypted: i=1; AJvYcCUuid133GWPhP5jTWyBIyvI86D/HFL1CcErrx1mxAUKWHYJK6zKPiFDXSHjDV19BB6nKdRWtBuXX8hL@vger.kernel.org, AJvYcCXeDUFcM4B4jtwfxEks1QbAifq4CAGZbrLNWlQv23zZetzfHkGFgxrJPerAw2zYW114p4C2fNKAvj6rMwvn@vger.kernel.org, AJvYcCXuxnHfqpNjL2SlbzEfjE2dlUs9ySyP3UnjvQ2+CvA4t1lanOU6BsfzbDh4larjzgbh2OLp5KM2Gj8W@vger.kernel.org X-Gm-Message-State: AOJu0YyY+38NHJEqIAlYZ6SSn5Ld/NJtWmaACmQx+8XfSzgtrJ1+mBRG P9ZrlfJxqjrTnp9QYsZnX2jDQC14jRJy0xJeSAw2uFr4e/JSLCjd X-Google-Smtp-Source: AGHT+IEkrA8U43EbLL8PtUg0l0K7tH8rQnspDeNnyVtzBYeMx8cJznQw5STblElKQlJzO9mLz8DLLw== X-Received: by 2002:a05:6808:1825:b0:3e6:63bb:ed4e with SMTP id 5614622812f47-3e7946c80b4mr8480393b6e.27.1731304844207; Sun, 10 Nov 2024 22:00:44 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3e78cd4ce88sm1976673b6e.44.2024.11.10.22.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 22:00:43 -0800 (PST) From: Chen Wang To: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 4/5] riscv: sophgo: dts: add pcie controllers for SG2042 Date: Mon, 11 Nov 2024 14:00:34 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index e62ac51ac55a..dca51fa9381b 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -195,6 +195,88 @@ clkgen: clock-controller@7030012000 { #clock-cells = <1>; }; + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0x3f>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <0>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie0_ctrl>; + interrupt-parent = <&msi>; + status = "disabled"; + }; + + cdns_pcie0_ctrl: syscon@7061800000 { + compatible = "sophgo,sg2042-pcie-ctrl", "syscon"; + reg = <0x70 0x61800000 0x0 0x800000>; + }; + + pcie_rc1: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x80 0xbf>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <0>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; + sophgo,internal-msi; + interrupt-parent = <&intc>; + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + status = "disabled"; + }; + + pcie_rc2: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0xc0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <1>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; + interrupt-parent = <&msi>; + status = "disabled"; + }; + + cdns_pcie1_ctrl: syscon@7063800000 { + compatible = "sophgo,sg2042-pcie-ctrl", "syscon"; + reg = <0x70 0x63800000 0x0 0x800000>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; From patchwork Mon Nov 11 06:00:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 13870254 Received: from mail-ot1-f49.google.com (mail-ot1-f49.google.com [209.85.210.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 366CBF9D9; Mon, 11 Nov 2024 06:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304864; cv=none; b=LbwGwSqEt5ReFEasr2H5ksQki/1MZ0SKdokyDlitKebB52fKuIMb2A14TIlwLMTDCmtYp9HPPnh/OspisnjoAE5k1QaTW7zhB0sDUKJJhAigqYwMxvA6E/361uwI/dT/ujr7NdSGuYSVm+BweqNBw0qAMQJCp7HPscvfAQMhBHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731304864; c=relaxed/simple; bh=NV+9hUlYUAg8ndimwT6PttWD1B2CP4DjjpTGNK+b/fU=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lw9FXUAhvxwii2FGl+BCK6obg2NmxT8SM1rffXtwQVTaddNiISDVecg43m0+8MMV/REm1yf7s0kzasob7PiJF8FSGqt0WT0NXo/Ofaaa57KAdXfb+c4CqPcTCX7YldmlmRB8xrBq71v4xVGsm9n9Gk0oAuRbpyuBuTWTJteyTFo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ibDVik6b; arc=none smtp.client-ip=209.85.210.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ibDVik6b" Received: by mail-ot1-f49.google.com with SMTP id 46e09a7af769-718119fc061so2101598a34.2; Sun, 10 Nov 2024 22:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731304862; x=1731909662; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ln/YvogurAeDd4PXMTsxwRi+ScCPO8pDH1rSa6dd7is=; b=ibDVik6bLlwNymCSnPQP5AjZm05yGoJ3AXkMwVw7B8MP8YpxE6YIPfcM1ACnGNsnnq u4LH0M4xoOhfnFmhAVfd9W9xV2utIzAjzGqR823N3wUCdEtXze+y99TB6hiF5Nj8VGyD efsaIXTCcW1DaJ6MbS5r4wzIZV0kgoHcnPkqV1HjTGHKr1vqVDH9GfaPguYm8jCPu3Dz xWjMLtgxcvZ5FjmKZLLOqAv7IylpQNqV8uCjAWvjL/2uP0jSM3AfbiWM4g7jSQOm12OA dbZI9lDNi9Hrf9quNGoxhwlMjNOK2TkJaYROwS2YAQjd+ijSrnJ26ECPkaBw31Nkrnbn Rbrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731304862; x=1731909662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ln/YvogurAeDd4PXMTsxwRi+ScCPO8pDH1rSa6dd7is=; b=Qn0rNGRt+fVLrgyeXjrTHjvAZQPFGXg+r2eY+Iyv6FgnRZTpZZnohLztPR15mVST4t Bat//H56C1D36Dc0FPC31rlghw5aMhlgby75EaIvhNm07nDPpHEqZKIeqPSGzOUUOron 2qKJ5VmhWh7sVuvBRDQh82TqTU10YgSlQeAPIAsrukWKz2BGGwixW7vjKMAC1qLRD/89 3eYO+IIACjNBUoN1bAnlioyyelzWOnfaG9eF0XcYGaxGVjerbJF5MvZ94k9XwK87DzZ8 O9dothwBxN30x6L1dOmqGRRVuMiFMj9tR2TTw1XDkBhB3ZHqthC49fAgSutMMs7OBUr5 0qeQ== X-Forwarded-Encrypted: i=1; AJvYcCUnma/u3oLJl7dMcS1L8CpKW5hxBDLz/WrMaujoVRZKjW6tU3o67Cc7y9wdMtRnXA0MPLNF1Oafvd+v@vger.kernel.org, AJvYcCVOs+PRyIMeX3j1VfK53Skla3aExbarVkBlKLjRD6PHPA0pRgJhecDNuwSvVt3xj7FFlKv/BByUl3cEN8cS@vger.kernel.org, AJvYcCXcL4LG0tfKsVieslbPx/PG3cPbNQ4s2yunOmlZZiVv075o/WzE6goPGwSHWQGMu5mmI/oM0TAGwseN@vger.kernel.org X-Gm-Message-State: AOJu0YwIzle5cAECDNngEhFRhdDe3qE8tUCfQ2L5GStIm/2A7NHyMGHQ bhIxAayMArWawunmGGBwzFgyXRmECO+DZTOOU3uYFJCbbPmusRK6 X-Google-Smtp-Source: AGHT+IFBlx2VElOixlZusR/Vn6fS6PXbSuh9gX6z0Dkf7b72H47WFUGg6sJXSpzTddWCr+wvW2+BFA== X-Received: by 2002:a05:6830:4cd:b0:71a:21c9:cd5c with SMTP id 46e09a7af769-71a21c9ce57mr6154495a34.22.1731304862305; Sun, 10 Nov 2024 22:01:02 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71a107ebea1sm2125973a34.14.2024.11.10.22.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 22:01:01 -0800 (PST) From: Chen Wang To: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 5/5] riscv: sophgo: dts: enable pcie for PioneerBox Date: Mon, 11 Nov 2024 14:00:53 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chen Wang Enable pcie controllers for PioneerBox, which uses SG2042 SoC. Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index a3f9d6f22566..746b9c3d254c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -45,6 +45,18 @@ mcu: syscon@17 { }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &sd { bus-width = <4>; no-sdio;