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[176.184.43.163]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432aa5b5e56sm231254545e9.2.2024.11.11.14.44.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 11 Nov 2024 14:45:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/2] target/mips: Introduce decode tree bindings for nanoMIPS ISA Date: Mon, 11 Nov 2024 23:44:51 +0100 Message-ID: <20241111224452.61276-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241111224452.61276-1-philmd@linaro.org> References: <20241111224452.61276-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Introduce the nanoMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/nanomips16.decode | 8 ++++++++ target/mips/tcg/nanomips32.decode | 8 ++++++++ target/mips/tcg/nanomips_translate.c | 14 ++++++++++++++ target/mips/tcg/nanomips_translate.c.inc | 7 +++++++ target/mips/tcg/meson.build | 3 +++ 6 files changed, 42 insertions(+) create mode 100644 target/mips/tcg/nanomips16.decode create mode 100644 target/mips/tcg/nanomips32.decode create mode 100644 target/mips/tcg/nanomips_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index a65ab4a747..f93bceb82a 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -222,6 +222,8 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ +bool decode_isa_nanomips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_nanomips32(DisasContext *ctx, uint32_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode new file mode 100644 index 0000000000..81fdc68e98 --- /dev/null +++ b/target/mips/tcg/nanomips16.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode new file mode 100644 index 0000000000..9cecf1e13d --- /dev/null +++ b/target/mips/tcg/nanomips32.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c new file mode 100644 index 0000000000..c148c13ed9 --- /dev/null +++ b/target/mips/tcg/nanomips_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - nanoMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-nanomips16.c.inc" +#include "decode-nanomips32.c.inc" diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 1e274143bb..e401b92bfd 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4482,6 +4482,13 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) return 2; } + if (decode_isa_nanomips16(ctx, ctx->opcode)) { + return 2; + } + if (decode_isa_nanomips32(ctx, ctx->opcode)) { + return 4; + } + op = extract32(ctx->opcode, 10, 6); switch (op) { case NM_P16_MV: diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 7b18e6c4c8..c05f3c0649 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,5 +1,7 @@ gen = [ decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), + decodetree.process('nanomips16.decode', extra_args: ['--decode=decode_isa_nanomips16', '--insnwidth=16']), + decodetree.process('nanomips32.decode', extra_args: ['--decode=decode_isa_nanomips32']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), @@ -18,6 +20,7 @@ mips_ss.add(files( 'lmmi_helper.c', 'msa_helper.c', 'msa_translate.c', + 'nanomips_translate.c', 'op_helper.c', 'rel6_translate.c', 'translate.c', From patchwork Mon Nov 11 22:44:52 2024 Content-Type: text/plain; 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[176.184.43.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381edc1104asm14091743f8f.88.2024.11.11.14.45.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 11 Nov 2024 14:45:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/2] target/mips: Convert nanoMIPS LSA opcode to decodetree Date: Mon, 11 Nov 2024 23:44:52 +0100 Message-ID: <20241111224452.61276-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241111224452.61276-1-philmd@linaro.org> References: <20241111224452.61276-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper, taking care to substract 1 to the shift field. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/nanomips32.decode | 8 ++++++++ target/mips/tcg/nanomips_translate.c | 12 ++++++++++++ target/mips/tcg/nanomips_translate.c.inc | 9 --------- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode index 9cecf1e13d..11bf5cd6c4 100644 --- a/target/mips/tcg/nanomips32.decode +++ b/target/mips/tcg/nanomips32.decode @@ -6,3 +6,11 @@ # # Reference: nanoMIPS32 Instruction Set Technical Reference Manual # (Document Number: MD01247) + +&r rs rt rd sa + +%lsa_u2 9:2 !function=minus_1 + +@lsa ...... rt:5 rs:5 rd:5 .. --- ... ... &r sa=%lsa_u2 + +LSA 001000 ..... ..... ..... .. ... 001 111 @lsa diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c index c148c13ed9..9a6db4a828 100644 --- a/target/mips/tcg/nanomips_translate.c +++ b/target/mips/tcg/nanomips_translate.c @@ -9,6 +9,18 @@ #include "qemu/osdep.h" #include "translate.h" +static inline int minus_1(DisasContext *ctx, int x) +{ + return x - 1; +} + /* Include the auto-generated decoders. */ #include "decode-nanomips16.c.inc" #include "decode-nanomips32.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_r *a) +{ + gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); + + return true; +} diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index e401b92bfd..0e012ab3d0 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -399,7 +399,6 @@ enum { /* POOL32A7 instruction pool */ enum { NM_P_LSX = 0x00, - NM_LSA = 0x01, NM_EXTW = 0x03, NM_POOL32AXF = 0x07, }; @@ -3625,14 +3624,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_P_LSX: gen_p_lsx(ctx, rd, rs, rt); break; - case NM_LSA: - /* - * In nanoMIPS, the shift field directly encodes the shift - * amount, meaning that the supported shift values are in - * the range 0 to 3 (instead of 1 to 4 in MIPSR6). - */ - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1); - break; case NM_EXTW: gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); break;