From patchwork Tue Nov 12 08:45:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Kandpal X-Patchwork-Id: 13871918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3849DD41D70 for ; Tue, 12 Nov 2024 08:45:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD3CE10E275; Tue, 12 Nov 2024 08:45:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="m8oisyX1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 992F610E02B; Tue, 12 Nov 2024 08:45:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731401153; x=1762937153; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ZcgpnOa40SIuetdynEKEerOPih2ow/d+dMCvF24+4HA=; b=m8oisyX1xYZWxZ/orPCJclq+20e98Cd/gIaR0EpLfdjSJH6o6BvUOVOz 44m4+/luROlRaQfuOgD1s5wi4pT88pl5h+wGAb3fG6jZkoGjcZfYWNpT9 i+3kLeCQb7XsiiXPnRWYgrl8eVyPhADSmdfU4SLXE0ZH3BuE78+4DzQrJ 1rgeG+eOMCDQbctWpL0CFisVSi6HFb7AGL2qOkQv6JKBX1FOV3mklQUlo 5jKIhg8cJF0W+Aofhj2IYHslGqFLuZCVhLPSKO3xn5YOJrrUnzv+vMSXm 0czHwlELef08jDrxYEkts9YLiXzJlNGiriGdHp/3OtxzKSKjXoiGwOjER A==; X-CSE-ConnectionGUID: o0yowKCvQoOgSIE/4BOR+Q== X-CSE-MsgGUID: NYfSSGvMQHCCsuYO6r8Edw== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="31449603" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="31449603" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:45:53 -0800 X-CSE-ConnectionGUID: GL6Ma1GIQiGilu/k3AFw7w== X-CSE-MsgGUID: QiF0dTe8Svi2yOhfxniUCA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="124851940" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2024 00:45:52 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, Suraj Kandpal , Mitul Golani Subject: [PATCH 1/6] drm/i915/watermark: Initialize latency variable to appropriate value Date: Tue, 12 Nov 2024 14:15:37 +0530 Message-Id: <20241112084542.1337314-1-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Initialize max_latency variable to LNL_PKG_C_LATENCY_MASK which helps to eliminate the else block and make the whole code a lot cleaner. Signed-off-by: Suraj Kandpal Reviewed-by: Mitul Golani --- drivers/gpu/drm/i915/display/skl_watermark.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index d3bbf335c749..a97e90ac643f 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2850,7 +2850,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state, static void skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) { - u32 max_latency = 0; + u32 max_latency = LNL_PKG_C_LATENCY_MASK; u32 clear = 0, val = 0; u32 added_wake_time = 0; @@ -2863,9 +2863,6 @@ skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) max_latency = LNL_PKG_C_LATENCY_MASK; added_wake_time = DSB_EXE_TIME + i915->display.sagv.block_time_us; - } else { - max_latency = LNL_PKG_C_LATENCY_MASK; - added_wake_time = 0; } clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; From patchwork Tue Nov 12 08:45:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Kandpal X-Patchwork-Id: 13871919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E0F9D41D71 for ; Tue, 12 Nov 2024 08:45:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B2C9310E58A; Tue, 12 Nov 2024 08:45:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NbzFaDGr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2BB8E10E02B; Tue, 12 Nov 2024 08:45:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731401155; x=1762937155; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JVc84VmJ7xPplE7bL4ZBDwb47Ft45bdE2pYA9hoi/OY=; b=NbzFaDGrr7Y+7FcrBibCbadeBJEisYN9pck9wGjkJZfO4b0F1v6IIohh g/mksNkBVvE6r6XrRhzrdfID1B5lHMGMYYxoGjHQgfFXEjzwPN15tKhVl wktElRGoXVeVjhbPQFC2z0ulmADKi1FwEJBwWlttvgvvBEPw7t6uOJtTG mdta5j56qZMCOaRpbBIKIUqY3PZVTGKp09F87w/JpnblJzKf2LjZFR/dK u7KLUrOC+kDMk5x3o3lNev6NXpgP996WBHulORSfRBOXhwq80VZgJmwbn hjL5dAedAGFdO4cl3t6iBh45aaHcF61yqOWkdAWJnOvOC2WbxH7cgGps1 g==; X-CSE-ConnectionGUID: i6FUvGOdTJGcaykDEA8qpg== X-CSE-MsgGUID: TpwscC0/TdKk6aYv+KwDqw== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="31449605" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="31449605" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:45:55 -0800 X-CSE-ConnectionGUID: UabMEW+0Q26Dze9rwOpVqg== X-CSE-MsgGUID: bWIW36uJRFC68p6Aw5MZLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="124851949" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2024 00:45:54 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 2/6] drm/i915/watermark: Rename enable_dpkgc variable Date: Tue, 12 Nov 2024 14:15:38 +0530 Message-Id: <20241112084542.1337314-2-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112084542.1337314-1-suraj.kandpal@intel.com> References: <20241112084542.1337314-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename the enable_dpkgc variable to make it more clear what it represents which is that if we are in fixed refresh rate or not. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/skl_watermark.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index a97e90ac643f..3fa463159b0b 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2848,7 +2848,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state, * Program PKG_C_LATENCY Added Wake Time = 0 */ static void -skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) +skl_program_dpkgc_latency(struct drm_i915_private *i915, bool fixed_refresh_rate) { u32 max_latency = LNL_PKG_C_LATENCY_MASK; u32 clear = 0, val = 0; @@ -2857,7 +2857,7 @@ skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) if (DISPLAY_VER(i915) < 20) return; - if (enable_dpkgc) { + if (fixed_refresh_rate) { max_latency = skl_watermark_max_latency(i915, 1); if (max_latency == 0) max_latency = LNL_PKG_C_LATENCY_MASK; @@ -2878,7 +2878,7 @@ skl_compute_wm(struct intel_atomic_state *state) struct intel_crtc *crtc; struct intel_crtc_state __maybe_unused *new_crtc_state; int ret, i; - bool enable_dpkgc = false; + bool fixed_refresh_rate = false; for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { ret = skl_build_pipe_wm(state, crtc); @@ -2907,10 +2907,10 @@ skl_compute_wm(struct intel_atomic_state *state) if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || !new_crtc_state->vrr.enable) - enable_dpkgc = true; + fixed_refresh_rate = true; } - skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc); + skl_program_dpkgc_latency(to_i915(state->base.dev), fixed_refresh_rate); skl_print_wm_changes(state); From patchwork Tue Nov 12 08:45:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Kandpal X-Patchwork-Id: 13871920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 893D0D41D70 for ; Tue, 12 Nov 2024 08:45:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D66810E594; Tue, 12 Nov 2024 08:45:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bv8NumvR"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C0E210E591; Tue, 12 Nov 2024 08:45:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731401157; x=1762937157; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hIXeuFhpIeUNqGZ33Yr0m+mB8qPT1Fu9RLp9d7PsxLE=; b=bv8NumvRSBmYsDwJhsB/jYpQZycZ5omKkZGmOFVKJphGV1xAZ1wfCBeU oUoqmKnCFBtXiDV9cms1/a+mmc7JAJWA05q4BlpcgVLG9gErSkkQpvuZV 9pTpoeVK/hxKIMUzE6yKzi1wAXbZkLPh44qkccHPA55tcuMp5WeaDRJER 476kkuCJKk6stDA4Is7YAtfkVjRR/2eczKUIxfA2rWyUQYv1sJncvnVN3 PJzDAGJNAiwlfWKbeMmOCOBQEC+CsxrJ93TvIyW50oO/5AO8kPm7VYXyz CFBGO5AGYqqEj1S7f4+yTbuzWZ+/9cg2NIJKEWBegSYQqA/tq8KpIS757 g==; X-CSE-ConnectionGUID: 80k7nsxARuqbLC7QEXEXAQ== X-CSE-MsgGUID: wVFEXHrkRJikgkis8Nv8Jg== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="31449606" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="31449606" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:45:57 -0800 X-CSE-ConnectionGUID: sJGqbBBCTQyY97Tbc0b5fw== X-CSE-MsgGUID: NRGPGCBPQcmOVqIBnlj8qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="124851956" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2024 00:45:56 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 3/6] drm/i915/watermark: Refactor dpkgc value prepration Date: Tue, 12 Nov 2024 14:15:39 +0530 Message-Id: <20241112084542.1337314-3-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112084542.1337314-1-suraj.kandpal@intel.com> References: <20241112084542.1337314-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Refactor the value getting prepped to be written into the PKG_C_LATENCY register by ORing the REG_FIELD_PREP values instead of having val getiing operated on twice. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 3fa463159b0b..4c92ada1c851 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2866,8 +2866,8 @@ skl_program_dpkgc_latency(struct drm_i915_private *i915, bool fixed_refresh_rate } clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; - val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency); - val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); + val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) | + REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val); } From patchwork Tue Nov 12 08:45:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Kandpal X-Patchwork-Id: 13871921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C66BD41D6F for ; Tue, 12 Nov 2024 08:46:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B412D10E596; Tue, 12 Nov 2024 08:46:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LreR4mpo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEF8810E594; Tue, 12 Nov 2024 08:45:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731401159; x=1762937159; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RKdgL7FQqZzSmT/WH6uGjTX66NQNGfu32DlfAWLQiVw=; b=LreR4mpoABHyKoOQxADFU6calUoE2G+fs5/1a+7Q6C+CpyO1q0az5d/b fsldj0vKa1skaf7iAIOafB3vj0Gn8T7Nk+MeP1op4YvxyYHMtvPpFtHLL d+AHb7/zf0Cjx4C7oiJ5Z7JlT0rouF+G93c4siJpz5L5R9/ot6Rns/UwH +mioUOxfAB4hg67hEgUHnnTUzEAlCpns2su+hNIxxZGQBkbZ/MMO2lfHk l5QaYwUgXHzcJB38nqQH37qywEYpKsYd2BbOOD+4TbelQOaXSl5rblRMG kB9uWWGS3l8kQjE6v+A9qq2ijg2P/zkUYSkJjEEif7INe+P7pBNFUMTjZ Q==; X-CSE-ConnectionGUID: AXp2rp3aTliPP75B/AhJhw== X-CSE-MsgGUID: +v76MtAKRR+fFyWxPro8vA== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="31449608" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="31449608" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:45:59 -0800 X-CSE-ConnectionGUID: Mw+z/0FuTwCMATVZfbV9eg== X-CSE-MsgGUID: hnU3i3eoS32b3xtj+J/c1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="124851962" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2024 00:45:57 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 4/6] drm/i915/watermark: Use intel_display for dpkgc code Date: Tue, 12 Nov 2024 14:15:40 +0530 Message-Id: <20241112084542.1337314-4-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112084542.1337314-1-suraj.kandpal@intel.com> References: <20241112084542.1337314-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use intel_display for DPKGC code wherever we can. While we are at it also use intel_de_rmw instead of intel_uncore_rmw as we really don't need the internal uncore_rmw_function. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/skl_watermark.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 4c92ada1c851..714bfcd83015 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2850,11 +2850,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state, static void skl_program_dpkgc_latency(struct drm_i915_private *i915, bool fixed_refresh_rate) { + struct intel_display *display = to_intel_display(&i915->drm); u32 max_latency = LNL_PKG_C_LATENCY_MASK; u32 clear = 0, val = 0; u32 added_wake_time = 0; - if (DISPLAY_VER(i915) < 20) + if (DISPLAY_VER(display) < 20) return; if (fixed_refresh_rate) { @@ -2862,14 +2863,14 @@ skl_program_dpkgc_latency(struct drm_i915_private *i915, bool fixed_refresh_rate if (max_latency == 0) max_latency = LNL_PKG_C_LATENCY_MASK; added_wake_time = DSB_EXE_TIME + - i915->display.sagv.block_time_us; + display->sagv.block_time_us; } clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) | REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); - intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val); + intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); } static int From patchwork Tue Nov 12 08:45:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Kandpal X-Patchwork-Id: 13871922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BC29D41D70 for ; Tue, 12 Nov 2024 08:46:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9305710E597; Tue, 12 Nov 2024 08:46:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iETME2HK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03D2210E596; Tue, 12 Nov 2024 08:46:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731401161; x=1762937161; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z+uFBVlDw5UeLgXMGTXAHiIK4ZXJg2E+kP2/joBcQ2g=; b=iETME2HKblperKhr+PaCYeNUPzNbiLVKdOAz/tWylS+0/rS8JAPON3iE P7c4JB0tAFzOhZi6ZrOx6EE0dN0/fZgiSmOZC3x3iNLgld6kC7ajYIDbj +CE2BXvo70x9IVD8wHHpeTFWrtVJD7wzKE1eSfSkvUt3oJFzLrNSCkt0Q SShwI0tVmc6CqwpPVirdXksSiNgdI49NeUgtyu+N/+nZnOuc5rBup83u4 rk7WIqiE7hNUTOfOU3UApBMtSHval/vIR+RHypes/adw5RrxyaQF1gQ0l tzlhGlXtP1iNOuWp3Lq265uz76x9Mg5q0Ybyv0YfOc3AZbzdv9rtndYtn A==; X-CSE-ConnectionGUID: Ax2Miep0R4uMhWdJqGYCNA== X-CSE-MsgGUID: YwCEw+2FRAiZOKHfy5R6uQ== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="31449609" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="31449609" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:46:01 -0800 X-CSE-ConnectionGUID: OLrOa1JkRv2q6Aae1Ir7Nw== X-CSE-MsgGUID: MT7EZMgWTamHVv7n906Qig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="124851971" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2024 00:45:59 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 5/6] drm/i915/watermark: Break and move DPKGC latency programming function Date: Tue, 12 Nov 2024 14:15:41 +0530 Message-Id: <20241112084542.1337314-5-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112084542.1337314-1-suraj.kandpal@intel.com> References: <20241112084542.1337314-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We break our dpkgc functions into two parts computation and writing to its respective register. This is for mainly due to the reason stated below - We do not want to compute and write to the register in the compute config phase itself. - We want to make sure we have all the required values specially linetime which is computed after intel_wm_compute, this will also help implement some WA's which require linetime. We also move it from its initial place because of the first point state above. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display.c | 7 ++ .../gpu/drm/i915/display/intel_display_core.h | 3 + drivers/gpu/drm/i915/display/intel_wm.c | 71 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_wm.h | 4 ++ drivers/gpu/drm/i915/display/skl_watermark.c | 50 ------------- 5 files changed, 85 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 46f6643d8d0f..484681f4e023 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4600,6 +4600,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, } + ret = intel_wm_compute_dpkgc_latency(state, dev_priv); + if (ret) + return ret; + ret = intel_psr2_sel_fetch_update(state, crtc); if (ret) return ret; @@ -7124,6 +7128,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, if (intel_crtc_vrr_enabling(state, crtc)) intel_vrr_enable(new_crtc_state); + + if (DISPLAY_VER(dev_priv) >= 20) + intel_wm_write_dpkgc_latency(to_intel_display(crtc)); } static void intel_enable_crtc(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 45b7c6900adc..8cfd8ab725ce 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -278,6 +278,9 @@ struct intel_wm { struct mutex wm_mutex; bool ipc_enabled; + + u32 dpkgc_latency; + u32 dpkgc_added_waketime; }; struct intel_display { diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c index d7dc49aecd27..ffc7dde86629 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.c +++ b/drivers/gpu/drm/i915/display/intel_wm.c @@ -7,9 +7,18 @@ #include "i915_drv.h" #include "i9xx_wm.h" +#include "intel_de.h" #include "intel_display_types.h" #include "intel_wm.h" #include "skl_watermark.h" +#include "skl_watermark_regs.h" + +/* + * It is expected that DSB can do posted writes to every register in + * the pipe and planes within 100us. For flip queue use case, the + * recommended DSB execution time is 100us + one SAGV block time. + */ +#define DSB_EXE_TIME 100 /** * intel_update_watermarks - update FIFO watermark values based on current modes @@ -131,6 +140,68 @@ bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, return plane_state->uapi.visible; } +/* + * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline: + * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from + * watermark level1 and up and above. If watermark level 1 is + * invalid program it with all 1's. + * Program PKG_C_LATENCY Added Wake Time = DSB execution time + * If Variable Refresh Rate where Vmin != Vmax != Flipline: + * Program DEEP PKG_C_LATENCY Pkg C with all 1's. + * Program PKG_C_LATENCY Added Wake Time = 0 + */ +int +intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, + struct drm_i915_private *i915) +{ + struct intel_display *display = to_intel_display(state); + struct intel_crtc *crtc; + struct intel_crtc_state *new_crtc_state; + u32 max_latency = LNL_PKG_C_LATENCY_MASK; + u32 added_waketime = 0; + int i; + bool fixed_refresh_rate = false; + + if (DISPLAY_VER(display) < 20) + return 0; + + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && + new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || + !new_crtc_state->vrr.enable) + fixed_refresh_rate = true; + } + + if (fixed_refresh_rate) { + max_latency = skl_watermark_max_latency(i915, 1); + if (max_latency == 0) + max_latency = LNL_PKG_C_LATENCY_MASK; + added_waketime = DSB_EXE_TIME + + display->sagv.block_time_us; + } + + display->wm.dpkgc_latency = max_latency; + display->wm.dpkgc_added_waketime = added_waketime; + + return 0; +} + +int +intel_wm_write_dpkgc_latency(struct intel_display *display) +{ + u32 clear = 0, val = 0; + + if (DISPLAY_VER(display) < 20) + return 0; + + clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; + val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, display->wm.dpkgc_latency) | + REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, display->wm.dpkgc_added_waketime); + + intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); + return 0; +} + void intel_print_wm_latency(struct drm_i915_private *dev_priv, const char *name, const u16 wm[]) { diff --git a/drivers/gpu/drm/i915/display/intel_wm.h b/drivers/gpu/drm/i915/display/intel_wm.h index e97cdca89a5c..1d3c2653168f 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.h +++ b/drivers/gpu/drm/i915/display/intel_wm.h @@ -9,6 +9,7 @@ #include struct drm_i915_private; +struct intel_display; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; @@ -31,5 +32,8 @@ void intel_print_wm_latency(struct drm_i915_private *i915, const char *name, const u16 wm[]); void intel_wm_init(struct drm_i915_private *i915); void intel_wm_debugfs_register(struct drm_i915_private *i915); +int intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, + struct drm_i915_private *i915); +int intel_wm_write_dpkgc_latency(struct intel_display *display); #endif /* __INTEL_WM_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 714bfcd83015..70f1d4f66f2d 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -28,12 +28,6 @@ #include "skl_watermark.h" #include "skl_watermark_regs.h" -/*It is expected that DSB can do posted writes to every register in - * the pipe and planes within 100us. For flip queue use case, the - * recommended DSB execution time is 100us + one SAGV block time. - */ -#define DSB_EXE_TIME 100 - static void skl_sagv_disable(struct drm_i915_private *i915); /* Stores plane specific WM parameters */ @@ -2837,49 +2831,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state, return 0; } -/* - * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline: - * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from - * watermark level1 and up and above. If watermark level 1 is - * invalid program it with all 1's. - * Program PKG_C_LATENCY Added Wake Time = DSB execution time - * If Variable Refresh Rate where Vmin != Vmax != Flipline: - * Program DEEP PKG_C_LATENCY Pkg C with all 1's. - * Program PKG_C_LATENCY Added Wake Time = 0 - */ -static void -skl_program_dpkgc_latency(struct drm_i915_private *i915, bool fixed_refresh_rate) -{ - struct intel_display *display = to_intel_display(&i915->drm); - u32 max_latency = LNL_PKG_C_LATENCY_MASK; - u32 clear = 0, val = 0; - u32 added_wake_time = 0; - - if (DISPLAY_VER(display) < 20) - return; - - if (fixed_refresh_rate) { - max_latency = skl_watermark_max_latency(i915, 1); - if (max_latency == 0) - max_latency = LNL_PKG_C_LATENCY_MASK; - added_wake_time = DSB_EXE_TIME + - display->sagv.block_time_us; - } - - clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; - val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) | - REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); - - intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); -} - static int skl_compute_wm(struct intel_atomic_state *state) { struct intel_crtc *crtc; struct intel_crtc_state __maybe_unused *new_crtc_state; int ret, i; - bool fixed_refresh_rate = false; for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { ret = skl_build_pipe_wm(state, crtc); @@ -2904,15 +2861,8 @@ skl_compute_wm(struct intel_atomic_state *state) ret = skl_wm_add_affected_planes(state, crtc); if (ret) return ret; - - if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && - new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || - !new_crtc_state->vrr.enable) - fixed_refresh_rate = true; } - skl_program_dpkgc_latency(to_i915(state->base.dev), fixed_refresh_rate); - skl_print_wm_changes(state); return 0; From patchwork Tue Nov 12 08:45:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Kandpal X-Patchwork-Id: 13871923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DA82D41D71 for ; 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X-CSE-ConnectionGUID: KcMQvnU0RNGnLPuOoweYfA== X-CSE-MsgGUID: xztN9n7/TGSgjb4Q3e1VjQ== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="31449613" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="31449613" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:46:03 -0800 X-CSE-ConnectionGUID: lviqJmRNS6+AzD7RsqLOzQ== X-CSE-MsgGUID: ut7B4YtaQgS9oIBcbqDKXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="124851984" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2024 00:46:01 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 6/6] drm/i915/watermark: Modify latency programmed into PKG_C_LATENCY Date: Tue, 12 Nov 2024 14:15:42 +0530 Message-Id: <20241112084542.1337314-6-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112084542.1337314-1-suraj.kandpal@intel.com> References: <20241112084542.1337314-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Increase the latency programmed into PKG_C_LATENCY latency to be a multiple of line time which is written into WM_LINETIME. --v2 -Fix commit subject line [Sai Teja] -Use individual DISPLAY_VER checks instead of range [Sai Teja] -Initialize max_linetime [Sai Teja] --v3 -take into account the scenario when adjusted_latency is 0 [Vinod] --v4 -rename adjusted_latency to latency [Mitul] -fix the condition in which dpkgc is disabled [Vinod] WA: 22020299601 Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_wm.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c index ffc7dde86629..47c82aa2adf9 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.c +++ b/drivers/gpu/drm/i915/display/intel_wm.c @@ -157,8 +157,9 @@ intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc; struct intel_crtc_state *new_crtc_state; - u32 max_latency = LNL_PKG_C_LATENCY_MASK; + u32 latency = LNL_PKG_C_LATENCY_MASK; u32 added_waketime = 0; + u32 max_linetime = 0; int i; bool fixed_refresh_rate = false; @@ -170,17 +171,27 @@ intel_wm_compute_dpkgc_latency(struct intel_atomic_state *state, new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || !new_crtc_state->vrr.enable) fixed_refresh_rate = true; + + max_linetime = max(new_crtc_state->linetime, max_linetime); } if (fixed_refresh_rate) { - max_latency = skl_watermark_max_latency(i915, 1); - if (max_latency == 0) - max_latency = LNL_PKG_C_LATENCY_MASK; + latency = skl_watermark_max_latency(i915, 1); + + /* Wa_22020299601 */ + if (latency) { + if (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) + latency = max_linetime * + DIV_ROUND_UP(latency, max_linetime); + } else { + latency = LNL_PKG_C_LATENCY_MASK; + } + added_waketime = DSB_EXE_TIME + display->sagv.block_time_us; } - display->wm.dpkgc_latency = max_latency; + display->wm.dpkgc_latency = latency; display->wm.dpkgc_added_waketime = added_waketime; return 0;