From patchwork Tue Nov 12 08:50:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mitul Golani X-Patchwork-Id: 13871925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2ADF1D41D71 for ; Tue, 12 Nov 2024 08:48:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C9EF10E595; Tue, 12 Nov 2024 08:48:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nAYrFoPm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 219D410E599; Tue, 12 Nov 2024 08:48:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731401322; x=1762937322; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=tJw5jf1UwoQWtl7pacdbkG0EI6YvziiwFxYbm8gv/DY=; b=nAYrFoPmV/FWeW7VHfyXduwZWI0Mr6D3M3nvAeukOZ7AkIqKG3G9zgGc uXzjWsULHGiCsVh5sT5rypjhxozMqORSdnolVqQ2657SypfVUttb5PmoX zaOQaLnoOGBHk2FtGayJsqqQz5wGda44RCcb1J2+ZYELouuM0vacyNeYD SSZZ204BZJBkzh+o09tYUcG93ncqvorw86Q33y+bf9j+sFhGODLVUcYbE mFJxNWVk1zG7lepG8sO5dBnaEu9M/I1NuhhjHjVPxL+SI2SBqX15ZFFvI BRwJpYTws5/JDUY0BhGPsoz3V3PxziJoxsoPllgxaPS7X6x8gMl+sy2gw A==; X-CSE-ConnectionGUID: sZFsYTpxTmemv35JiBW+/w== X-CSE-MsgGUID: EaKLiM+jSDanXrspsRI8RA== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="18835736" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="18835736" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:48:42 -0800 X-CSE-ConnectionGUID: JXaSEMBGQnSb8p65rLFoyg== X-CSE-MsgGUID: az6ionaLRTmFOnZG/h3snQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="87759860" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by fmviesa009.fm.intel.com with ESMTP; 12 Nov 2024 00:48:41 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [RFC v1 1/4] drm/i915/scaler: Calculate scaler prefill latency Date: Tue, 12 Nov 2024 14:20:36 +0530 Message-ID: <20241112085039.1258860-2-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> References: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Calculate scaler prefill latency which accounts for time for each scaler in pipeline. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/skl_scaler.c | 39 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/skl_scaler.h | 1 + 2 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 7dbc99b02eaa..eec4a5f783fa 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -6,6 +6,7 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_crtc.h" #include "intel_fb.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -839,3 +840,41 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) else scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); } + +int skl_calc_scaler_prefill_latency(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); + struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + int scaler_prefill_latency[2]; + int num_scaler_in_use, count, hscale, vscale, tot_scaler_prefill_usec; + int hscan_time = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.htotal * 1000, + crtc_state->hw.adjusted_mode.crtc_clock); + + for (count = 0; count < crtc->num_scalers; count++) + if (scaler_state->scalers[count].in_use) + num_scaler_in_use++; + + if (!num_scaler_in_use) + return 0; + + if (num_scaler_in_use == 2) { + hscale = drm_rect_calc_hscale(&plane_state->uapi.src, + &plane_state->uapi.dst, + 0, INT_MAX); + vscale = drm_rect_calc_vscale(&plane_state->uapi.src, + &plane_state->uapi.dst, + 0, INT_MAX); + scaler_prefill_latency[1] = 4 * hscan_time * hscale * vscale; + } + + /* + * FIXME : When only 1 scaler used, 1st scaler can be downscale/upscale + */ + scaler_prefill_latency[0] = 4 * hscan_time; + tot_scaler_prefill_usec = scaler_prefill_latency[0] + scaler_prefill_latency[1]; + + return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, + tot_scaler_prefill_usec); +} diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 63f93ca03c89..cd4d961d3b02 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -34,4 +34,5 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); +int skl_calc_scaler_prefill_latency(struct intel_crtc_state *crtc_state); #endif From patchwork Tue Nov 12 08:50:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mitul Golani X-Patchwork-Id: 13871926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85C5AD41D6E for ; Tue, 12 Nov 2024 08:48:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B52410E5A4; Tue, 12 Nov 2024 08:48:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="f/PWGGO0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3D04B10E592; Tue, 12 Nov 2024 08:48:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731401323; x=1762937323; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=5znXMSDU/en1mbS0SCp/J18ANy883+iR6+gXfPD1lR0=; b=f/PWGGO0xg1vligN+ZIxRwI6DlFbH9Jyh2MLywxdQLqGIj4ZvPXzaMG6 4R3TsjfV6DS4ksHtqvX64G2MbQfgSRNOFRXvx7XEX8AY99/aslFUqbFQb ogpArtqIbFJGSjRxAQXQCneQi52jhCvUjRBdeLh8xPw9Z/2CyYjY0udAd 0/BKJzRbXTBp+3F+ok86b1Z7DAeHGSlgJfIuwMNNxSr5brrb4N7tdr3ns a39g2mep/qLDS3iTP9Hf3SZE1qdOt6zrXHr9me0V6+eN1H5EqZvm+NwKI rYFpnlf7dDLeMT6VG7mcxPwg6TFeQiPu0e/mJ4FzVAFoofD5d7IBOSGd9 A==; X-CSE-ConnectionGUID: bpL1X3H7RvWRXEuVJB22ow== X-CSE-MsgGUID: yUgJMvp8SLmFYagb+ZVdew== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="18835741" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="18835741" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:48:43 -0800 X-CSE-ConnectionGUID: SkSUZ6pyT9qnVTiH55VN8A== X-CSE-MsgGUID: bv4g+VxzRBihnNcnq5ceow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="87759869" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by fmviesa009.fm.intel.com with ESMTP; 12 Nov 2024 00:48:42 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [RFC v1 2/4] drm/i915/watermark: Add WM0 prefill latency Date: Tue, 12 Nov 2024 14:20:37 +0530 Message-ID: <20241112085039.1258860-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> References: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Calculate WM0 prefill latency which accounts for maximum time to fill data buffer up to watermark 0. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/skl_watermark.c | 21 ++++++++++++++++++++ drivers/gpu/drm/i915/display/skl_watermark.h | 1 + 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index d3bbf335c749..8afa24943333 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2260,6 +2260,27 @@ static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state) return wm0_lines; } +int skl_calc_wm0_prefill_latency(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + int cdclk_prefill_latency, wm0_prefill_latency; + int linetime = + DIV_ROUND_UP(crtc_state->hw.adjusted_mode.htotal * 1000, + crtc_state->hw.adjusted_mode.crtc_clock); + /* + * TODO: DIV_ROUND_UP will also round off to 1, so need to + * check upon if this can be eliminated here + */ + cdclk_prefill_latency = + MIN(1, DIV_ROUND_UP(crtc_state->pixel_rate, + 2 * display->cdclk.hw.cdclk)); + wm0_prefill_latency = + 20 + (linetime * skl_max_wm0_lines(crtc_state) * cdclk_prefill_latency); + + return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, + wm0_prefill_latency); +} + static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state, int wm0_lines) { diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index e73baec94873..9495a142fbe5 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -23,6 +23,7 @@ struct skl_wm_level; u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); +int skl_calc_wm0_prefill_latency(struct intel_crtc_state *crtc_state); void intel_sagv_pre_plane_update(struct intel_atomic_state *state); void intel_sagv_post_plane_update(struct intel_atomic_state *state); bool intel_can_enable_sagv(struct drm_i915_private *i915, From patchwork Tue Nov 12 08:50:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mitul Golani X-Patchwork-Id: 13871929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9C9FD41D6E for ; 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X-CSE-ConnectionGUID: KIQTeTCySB2bAZciYhmGNg== X-CSE-MsgGUID: G8Yxfr/uRC+UfbmLQbCyrw== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="18835745" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="18835745" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:48:44 -0800 X-CSE-ConnectionGUID: dwRhnj0VTvyNi2e8Gsu2Uw== X-CSE-MsgGUID: dGjrgfgZSSG2Xm8ZIRGLUw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="87759878" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by fmviesa009.fm.intel.com with ESMTP; 12 Nov 2024 00:48:43 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [RFC v1 3/4] drm/i915/psr: Add latency for PSR Date: Tue, 12 Nov 2024 14:20:38 +0530 Message-ID: <20241112085039.1258860-4-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> References: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Calculate latency for PSR2 wake lines. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_psr.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 16888935b33a..b7dfdd94509c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3972,3 +3972,26 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_psr_status", 0444, root, connector, &i915_psr_status_fops); } + +int intel_psr2_calc_prefill(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + int wake_lines; + struct intel_encoder *encoder; + + intel_psr_lock(crtc_state); + for_each_intel_encoder_mask_with_psr(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + lockdep_assert_held(&intel_dp->psr.lock); + + if (!intel_psr2_config_valid(intel_dp, crtc_state)) + return false; + + wake_lines = psr2_block_count_lines(intel_dp); + } + intel_psr_unlock(crtc_state); + + return wake_lines; +} diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 956be263c09e..65f936d83aad 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -24,6 +24,7 @@ struct intel_plane_state; #define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \ (intel_dp)->psr.source_panel_replay_support) +int intel_psr2_calc_prefill(struct intel_crtc_state *crtc_state); bool intel_encoder_can_psr(struct intel_encoder *encoder); bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); From patchwork Tue Nov 12 08:50:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mitul Golani X-Patchwork-Id: 13871927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82AC0D41D6F for ; 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X-CSE-ConnectionGUID: M6SLX63pQy2UzuIEX1zRGQ== X-CSE-MsgGUID: ZLeNt+QjS9CQpI00x6/A5g== X-IronPort-AV: E=McAfee;i="6700,10204,11253"; a="18835750" X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="18835750" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2024 00:48:45 -0800 X-CSE-ConnectionGUID: PuwpjjXoTR68M8mjJ+ACSA== X-CSE-MsgGUID: ZRXiUcuiStmSkURnCHAXcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,147,1728975600"; d="scan'208";a="87759886" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by fmviesa009.fm.intel.com with ESMTP; 12 Nov 2024 00:48:44 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [RFC v1 4/4] display/vrr: Update guardband based on enabled latency Date: Tue, 12 Nov 2024 14:20:39 +0530 Message-ID: <20241112085039.1258860-5-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> References: <20241112085039.1258860-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Instead of computing guardband to max vblank, account for the differenct feature latency. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 19a5d0076bb8..de5113ab018b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -10,7 +10,12 @@ #include "intel_display_types.h" #include "intel_vrr.h" #include "intel_vrr_regs.h" +#include "skl_watermark_regs.h" +#include "intel_crtc.h" #include "intel_dp.h" +#include "intel_psr.h" +#include "skl_watermark.h" +#include "skl_scaler.h" #define FIXED_POINT_PRECISION 100 #define CMRR_PRECISION_TOLERANCE 10 @@ -255,8 +260,17 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state) return; if (DISPLAY_VER(display) >= 13) { - crtc_state->vrr.guardband = - crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; + int sagv_block_time_in_scanline = + intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, + display->sagv.block_time_us); + /* + * TODO: DSC , PKGC and SDP latency to be computed + */ + crtc_state->vrr.guardband = MAX(crtc_state->framestart_delay + + skl_calc_scaler_prefill_latency(crtc_state) + + skl_calc_wm0_prefill_latency(crtc_state) + + sagv_block_time_in_scanline, + intel_psr2_calc_prefill(crtc_state)); } else { crtc_state->vrr.pipeline_full = min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -