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CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM7PR04MB7046.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(376014)(7416014)(52116014)(1800799024)(38350700014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9sBdl5aKLfYUEgMEqgFdrWLhrI7OtgDRzztii0QR4O87MozXaRskmJUJDpriZhdymJYRlIon0QP059fWAoegjroW7JFGnK1q36kV/wyiC1akSgu5K1GNBXxWmt8VI19WKNecyUlvxnYLfaZhxQyvtmgzeERjK8i2vMkn5/C+1aTj7bDISlEGrHQPw//ysag7RdtsZ/NsHZfmkPbVbyVJhhhahMbDYo5GXNPk869iLGLyo9P9+1qwlgpF9oOLUdhMPTo3FYQpPdSCmfbj7NS8oL0SEDtCes0nOpHXFek2gP7rOQkblLVb49cKUvmx7copir4yqE+bcCLSpVECB7PppD/T/gzOns8RSnchHS3UtBGoL6P26/rpp6P/M4EJoqaXXv4QdAisBGq0Xsm2a1tAuY2SesOe0Y2bllsqDdBk04VTtZmQDmC/OdpiTLpwRcSKLlUVPfQq1mHm+1IvrMaOKcD98oftkPr5kYOuCKohKuKNu9LeY1rMBM8eGnOJMIVUgxBA9wvQGo6w48s8dqxtmqz5HN2E5Qt+Vfpqiw1n6s9V19AN3WIo5VIR/E3Cy2pQqFMCsKABHq2ZmZ4zHj4pUANBHQqysbkwLsArDYANiQDxUO0PWOHBdjt7wxOPN3OBmDvOVV9GjMxqS9+Kol/J04mF4cPf1DZSVXIzJ9J4X4WkCFzOUWOk0vHB6c49nNj6J/6eefgmucIscr4pDCTnWMIIpaUbzVIv8F5XnCgpPhrRRVEo30VtoVgQDIQ1T45MNqIhyhHaFKIrueDwji0clO4oE8FGvPDSZUojLllu3ICNgx61MuYTkoWrDguCn+fky3y7gsY/12PCzp64sDqlQmjV7LvSxqV6S5MAfWSoCvwYptItLT4LEI+6D05Ob2VG19BRTELGkjAOqTBJtn4tKZGdA8YuMR7h4GWEbdmEZ28YK8ZvXhz3Hytjx3DePX9AkmNjbCCXkYLgOwj8/2MQnkE49ALuXfENTCe3alqzSfOeR/gBy/9kr4Dwv5rPaM46/wuvjoZxnCLcpdwx+pXuSCCZsXuiXRfWUw6dQ5AXuRL3eVNbN1wH/LhK9xDYjgTqTWkCQd60pDJKYUbjAmqSxeYYXe1oGfVEj/JN1BZrIGxz8rcpcMSPD95V7+zZXcuDpynCb1j4PN+aBNPyJymfJFs3+AqCMzJTDM0UPJeASRwNukpyFisL2fzd+8DDTG073U69jyFpelAUYpZ2XcUb8iuH0iicQxb7jry2ODNkRXrj0OWb2h3tAQkLbXM+S2fl7b38KJOiXghGpuHTU6QRRc1AD/AA2QhsduFvSk+Cf9CHe5Pvx/jNbdxNcVoVPVaYH69RpnipWCAG8Qr51uv1Uds9XihcgqTy1ONKCVLyc9ef2NwrBnixcpfi5Pb0FU+4b+/vLRyrwbze+/OSbT0GsWDWdIH5o4wPVfHUecqZ/5DGCfBSb8boQl3P8fLiSV5UD7WnlHyy7bYVw3Woa7dHU43q3gK9G9SQItFLNF9bqFnwdH4gOBbdbpLlkTezaaNHjDbIcdGbfHISAqxjU3na4OgCpSW1+ma+VPxFBzjYF3lbJdP6aq5EWR9pjHtvLMSy X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f477ad38-a8ef-4793-3225-08dd03019807 X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2024 10:05:53.9985 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rlZGL78HDRb7ON8TOJhrCsBq3hfUOLNqNgijZus3TniQj+O+IJCJxdlNTb686nj9MZ0Ya+z9wCNPVfiR5WwHVA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8256 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The LVDS panel "multi-inno,mi1010ait-1cp" used on this platform has a typical pixel clock rate of 70MHz. Set "media_disp2_pix" clock rate to that rate, instead of the original 68.9MHz. The LVDS serial clock is controlled by "media_ldb" clock. It should run at 490MHz(7-fold the pixel clock rate due to single LVDS link). Set "video_pll1" clock rate and "media_ldb" to 490MHz to achieve that. This should be able to suppress this LDB driver warning: [ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (70000000 Hz) does not match requested LVDS clock: 490000000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Signed-off-by: Liu Ying --- v6: * No change. v5: * No change. v4: * No change. v3: * New patch. .../dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts index 30962922b361..2c75da5f064f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -52,7 +52,7 @@ &lcdif2 { &lvds_bridge { /* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ - assigned-clock-rates = <482300000>; + assigned-clock-rates = <490000000>; status = "okay"; ports { @@ -70,10 +70,10 @@ &media_blk_ctrl { */ assigned-clock-rates = <500000000>, <200000000>, <0>, /* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */ - <68900000>, + <70000000>, <500000000>, - /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */ - <964600000>; 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The two display controllers connect with Samsung MIPI DSI controller and LVDS Display Bridge(LDB) respectively. Since the two display controllers are driven by separate DRM driver instances and the two pixel clocks may be derived from the same video_pll1_out clock(sys_pll3_out clock could be already used to derive audio_axi clock), there is no way to negotiate a dynamically changeable video_pll1_out clock rate to satisfy both of the two display controllers. In this case, the only solution to drive them with the single video_pll1_out clock is to assign a sensible/unchangeable clock rate for video_pll1_out clock. Thus, there is no need to set the CLK_SET_RATE_PARENT flag for media_disp{1,2}_pix clocks, drop it then. Fixes: ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate") Signed-off-by: Liu Ying --- v6: * New patch. drivers/clk/imx/clk-imx8mp.c | 4 ++-- drivers/clk/imx/clk.h | 4 ---- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..e561ff7b135f 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -547,7 +547,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000); hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100); hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); - hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300, CLK_SET_RATE_PARENT); + hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300); hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); @@ -609,7 +609,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80); hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00); hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); - hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_PARENT); + hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00); hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00); hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..adb7ad649a0d 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -442,10 +442,6 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, _imx8m_clk_hw_composite(name, parent_names, reg, \ IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) -#define imx8m_clk_hw_composite_bus_flags(name, parent_names, reg, flags) \ - _imx8m_clk_hw_composite(name, parent_names, reg, \ - IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags) - #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ _imx8m_clk_hw_composite(name, parent_names, reg, \ IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) From patchwork Tue Nov 12 10:05:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13872011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACD47D32D83 for ; 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b=MYPZtOrozI/PYl83raowS994RANvJwTsu8ot6dExDGQbEK1bXPXGrrOpB4L7EY/vqu0bA+ITConx0pMTsXgPiW41Nm78uj7A9ZBOBkPXUsCs1jMvOzcCiw0AzDgDwiwf+1JLPt9A3NbL05+0SXPpEYG1fgvnGrGwRpKRJ3h/NCkvxMRldlueEwevX58v8PK0FTkn9PIej12NAXY16hxbeOKdwA1WjZv05AKYe66OYgBBqwHkvEnmYS9aW/sp9WiunAEw8JLOrYY/c/PpX7pCeLyLVgLY+pMX227ITQgJoM1TTjJfe9lHZQ608tkPxxLHQ50Wtmvup6uy9pspVAMNbg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by PAXPR04MB8256.eurprd04.prod.outlook.com (2603:10a6:102:1c6::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.28; Tue, 12 Nov 2024 10:06:12 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%5]) with mapi id 15.20.8137.027; Tue, 12 Nov 2024 10:06:12 +0000 From: Liu Ying To: imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, quic_bjorande@quicinc.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, marex@denx.de Subject: [PATCH v6 3/7] drm/bridge: fsl-ldb: Get the next non-panel bridge Date: Tue, 12 Nov 2024 18:05:43 +0800 Message-Id: <20241112100547.2908497-4-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112100547.2908497-1-victor.liu@nxp.com> References: <20241112100547.2908497-1-victor.liu@nxp.com> X-ClientProxiedBy: SG2PR02CA0025.apcprd02.prod.outlook.com (2603:1096:3:18::13) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|PAXPR04MB8256:EE_ X-MS-Office365-Filtering-Correlation-Id: dc766a2b-227a-4861-154f-08dd0301a338 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Use devm_drm_of_get_bridge() to replace the combination function calls of of_drm_find_panel() and devm_drm_panel_bridge_add() to get either a panel bridge or a non-panel bridge, instead of getting a panel bridge only. Signed-off-by: Liu Ying Reviewed-by: Dmitry Baryshkov --- v6: * No change. v5: * No change. v4: * No change. v3: * Collect Dmitry' R-b tag. v2: * No change. drivers/gpu/drm/bridge/fsl-ldb.c | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index 0e4bac7dd04f..b559f3e0bef6 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -15,7 +15,6 @@ #include #include #include -#include #define LDB_CTRL_CH0_ENABLE BIT(0) #define LDB_CTRL_CH0_DI_SELECT BIT(1) @@ -86,7 +85,7 @@ static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { struct fsl_ldb { struct device *dev; struct drm_bridge bridge; - struct drm_bridge *panel_bridge; + struct drm_bridge *next_bridge; struct clk *clk; struct regmap *regmap; const struct fsl_ldb_devdata *devdata; @@ -117,7 +116,7 @@ static int fsl_ldb_attach(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge, + return drm_bridge_attach(bridge->encoder, fsl_ldb->next_bridge, bridge, flags); } @@ -292,9 +291,7 @@ static const struct drm_bridge_funcs funcs = { static int fsl_ldb_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *panel_node; struct device_node *remote1, *remote2; - struct drm_panel *panel; struct fsl_ldb *fsl_ldb; int dual_link; @@ -318,33 +315,27 @@ static int fsl_ldb_probe(struct platform_device *pdev) if (IS_ERR(fsl_ldb->regmap)) return PTR_ERR(fsl_ldb->regmap); - /* Locate the remote ports and the panel node */ + /* Locate the remote ports. */ remote1 = of_graph_get_remote_node(dev->of_node, 1, 0); remote2 = of_graph_get_remote_node(dev->of_node, 2, 0); fsl_ldb->ch0_enabled = (remote1 != NULL); fsl_ldb->ch1_enabled = (remote2 != NULL); - panel_node = of_node_get(remote1 ? remote1 : remote2); of_node_put(remote1); of_node_put(remote2); - if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) { - of_node_put(panel_node); - return dev_err_probe(dev, -ENXIO, "No panel node found"); - } + if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) + return dev_err_probe(dev, -ENXIO, "No next bridge node found"); dev_dbg(dev, "Using %s\n", fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" : fsl_ldb->ch0_enabled ? "channel 0" : "channel 1"); - panel = of_drm_find_panel(panel_node); - of_node_put(panel_node); - if (IS_ERR(panel)) - return PTR_ERR(panel); - - fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel); - if (IS_ERR(fsl_ldb->panel_bridge)) - return PTR_ERR(fsl_ldb->panel_bridge); - + fsl_ldb->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, + fsl_ldb->ch0_enabled ? 1 : 2, + 0); + if (IS_ERR(fsl_ldb->next_bridge)) + return dev_err_probe(dev, PTR_ERR(fsl_ldb->next_bridge), + "failed to get next bridge\n"); if (fsl_ldb_is_dual(fsl_ldb)) { struct device_node *port1, *port2; From patchwork Tue Nov 12 10:05:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13872012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 692AAD32D83 for ; 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Use clk_round_rate() to validate the "ldb" clock rate for each mode in drm_bridge_funcs::mode_valid() to filter unsupported modes out. Signed-off-by: Liu Ying --- Note that this patch depends on a patch in shawnguo/imx/fixes: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241017031146.157996-1-marex@denx.de/ v6: * Drop pixel clock rate validation. v5: * No change. v4: * No change. v3: * No change. v2: * Add more comments in fsl-ldb.c and commit message about pixel clock rate validation. (Maxime) drivers/gpu/drm/bridge/fsl-ldb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index b559f3e0bef6..d9436ff9ccc3 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -270,10 +270,16 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, const struct drm_display_mode *mode) { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); + unsigned long link_freq; if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) return MODE_CLOCK_HIGH; + /* Validate "ldb" clock rate. */ + link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); + if (link_freq != clk_round_rate(fsl_ldb->clk, link_freq)) + return MODE_NOCLOCK; + return MODE_OK; } From patchwork Tue Nov 12 10:05:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13872013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1E66D32D83 for ; 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This may filter modes out whose pixel clock rates cannot be supported by the pixel clock tree. For example, when the pixel clock is derived from the i.MX8MP video_pll1_out clock and video_pll1_out clock rate is 1.0395GHz, mode 720x576p@50Hz with 27MHz pixel clock rate will be filtered out in LDB split mode because the PLL clock rate does satisfy the "ldb" clock rate(27MHz * 3.5 = 94.5MHz) with 11 division ratio while it cannot satisfy the "pix" clock rate with 38.5 division ratio(only integer division ratio is supported). Signed-off-by: Liu Ying --- v6: * New patch. drivers/gpu/drm/bridge/fsl-ldb.c | 38 +++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index d9436ff9ccc3..035a3ffb4b3b 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -86,7 +87,8 @@ struct fsl_ldb { struct device *dev; struct drm_bridge bridge; struct drm_bridge *next_bridge; - struct clk *clk; + struct clk *clk_ldb; + struct clk *clk_pixel; struct regmap *regmap; const struct fsl_ldb_devdata *devdata; bool ch0_enabled; @@ -176,15 +178,15 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, mode = &crtc_state->adjusted_mode; requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); - clk_set_rate(fsl_ldb->clk, requested_link_freq); + clk_set_rate(fsl_ldb->clk_ldb, requested_link_freq); - configured_link_freq = clk_get_rate(fsl_ldb->clk); + configured_link_freq = clk_get_rate(fsl_ldb->clk_ldb); if (configured_link_freq != requested_link_freq) dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz\n", configured_link_freq, requested_link_freq); - clk_prepare_enable(fsl_ldb->clk); + clk_prepare_enable(fsl_ldb->clk_ldb); /* Program LDB_CTRL */ reg = (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_ENABLE : 0) | @@ -237,7 +239,7 @@ static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); - clk_disable_unprepare(fsl_ldb->clk); + clk_disable_unprepare(fsl_ldb->clk_ldb); } #define MAX_INPUT_SEL_FORMATS 1 @@ -269,15 +271,21 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { + unsigned long link_freq, pclk_rate, rounded_pclk_rate; struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - unsigned long link_freq; if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) return MODE_CLOCK_HIGH; /* Validate "ldb" clock rate. */ link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); - if (link_freq != clk_round_rate(fsl_ldb->clk, link_freq)) + if (link_freq != clk_round_rate(fsl_ldb->clk_ldb, link_freq)) + return MODE_NOCLOCK; + + /* Validate pixel clock rate. */ + pclk_rate = mode->clock * HZ_PER_KHZ; + rounded_pclk_rate = clk_round_rate(fsl_ldb->clk_pixel, pclk_rate); + if (rounded_pclk_rate != pclk_rate) return MODE_NOCLOCK; return MODE_OK; @@ -297,7 +305,7 @@ static const struct drm_bridge_funcs funcs = { static int fsl_ldb_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *remote1, *remote2; + struct device_node *remote0, *remote1, *remote2; struct fsl_ldb *fsl_ldb; int dual_link; @@ -313,9 +321,16 @@ static int fsl_ldb_probe(struct platform_device *pdev) fsl_ldb->bridge.funcs = &funcs; fsl_ldb->bridge.of_node = dev->of_node; - fsl_ldb->clk = devm_clk_get(dev, "ldb"); - if (IS_ERR(fsl_ldb->clk)) - return PTR_ERR(fsl_ldb->clk); + fsl_ldb->clk_ldb = devm_clk_get(dev, "ldb"); + if (IS_ERR(fsl_ldb->clk_ldb)) + return PTR_ERR(fsl_ldb->clk_ldb); + + /* Get pixel clock from display controller's OF node. */ + remote0 = of_graph_get_remote_node(dev->of_node, 0, 0); + fsl_ldb->clk_pixel = of_clk_get_by_name(remote0, "pix"); + of_node_put(remote0); + if (IS_ERR(fsl_ldb->clk_pixel)) + return PTR_ERR(fsl_ldb->clk_pixel); fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent); if (IS_ERR(fsl_ldb->regmap)) @@ -375,6 +390,7 @@ static void fsl_ldb_remove(struct platform_device *pdev) struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev); drm_bridge_remove(&fsl_ldb->bridge); + clk_put(fsl_ldb->clk_pixel); } static const struct of_device_id fsl_ldb_match[] = { From patchwork Tue Nov 12 10:05:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13872014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DE68D32D83 for ; Tue, 12 Nov 2024 10:06:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD50810E5AC; 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Card IMX-LVDS-HDMI supports single LVDS link(IT6263 link1). Card IMX-DLVDS-HDMI supports dual LVDS links(IT6263 link1 and link2). Only one card can be enabled with one i.MX8MP EVK. Add dedicated overlays to support the below four connections: 1) imx8mp-evk-lvds0-imx-lvds-hdmi.dtso: i.MX8MP EVK LVDS0 connector <=> LVDS adapter card J6(IT6263 link1) 2) imx8mp-evk-lvds1-imx-lvds-hdmi.dtso: i.MX8MP EVK LVDS1 connector <=> LVDS adapter card J6(IT6263 link1) 3) imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso: i.MX8MP EVK LVDS0 connector <=> DLVDS adapter card channel0(IT6263 link1) i.MX8MP EVK LVDS1 connector <=> DLVDS adapter card channel1(IT6263 link2) 4) imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso: i.MX8MP EVK LVDS1 connector <=> DLVDS adapter card channel0(IT6263 link1) i.MX8MP EVK LVDS0 connector <=> DLVDS adapter card channel1(IT6263 link2) Part links: https://www.nxp.com/part/IMX-LVDS-HDMI https://www.nxp.com/part/IMX-DLVDS-HDMI Signed-off-by: Liu Ying --- v6: * No change. v5: * No change. v4: * Rebase this patch upon next-20241025 to resolve conflicts when apply. v3: * Use data-mapping DT property instead of ite,lvds-link-num-data-lanes. (Dmitry, Biju) v2: * Add ite,lvds-link-num-data-lanes properties. arch/arm64/boot/dts/freescale/Makefile | 8 ++++ .../imx8mp-evk-imx-lvds-hdmi-common.dtsi | 29 ++++++++++++ ...8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso | 44 +++++++++++++++++++ ...imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi | 43 ++++++++++++++++++ .../imx8mp-evk-lvds0-imx-lvds-hdmi.dtso | 28 ++++++++++++ ...8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso | 44 +++++++++++++++++++ ...imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi | 43 ++++++++++++++++++ .../imx8mp-evk-lvds1-imx-lvds-hdmi.dtso | 28 ++++++++++++ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +++ 9 files changed, 273 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 42e6482a31cb..e2e828b352e7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -211,8 +211,16 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb +imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtbo +imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-hdmi.dtbo +imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo +imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi new file mode 100644 index 000000000000..44b30e9b3fde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; +/plugin/; + +&{/} { + lvds-hdmi-connector { + compatible = "hdmi-connector"; + label = "J2"; + type = "a"; + + port { + lvds2hdmi_connector_in: endpoint { + remote-endpoint = <&it6263_out>; + }; + }; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso new file mode 100644 index 000000000000..4008d2fd36d6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + it6263_lvds_link1: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + it6263_lvds_link2: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&it6263_lvds_link1>; + }; + }; + + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&it6263_lvds_link2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi new file mode 100644 index 000000000000..6eae7477abf8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi" + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + it6263: hdmi@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + data-mapping = "jeida-24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_en>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + ivdd-supply = <®_buck5>; + ovdd-supply = <®_vext_3v3>; + txavcc18-supply = <®_buck5>; + txavcc33-supply = <®_vext_3v3>; + pvcc1-supply = <®_buck5>; + pvcc2-supply = <®_buck5>; + avcc-supply = <®_vext_3v3>; + anvdd-supply = <®_buck5>; + apvdd-supply = <®_buck5>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + it6263_out: endpoint { + remote-endpoint = <&lvds2hdmi_connector_in>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso new file mode 100644 index 000000000000..9e11f261ad13 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg = <0>; + + it6263_lvds_link1: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&it6263_lvds_link1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso new file mode 100644 index 000000000000..af2e73e36a1b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg = <0>; + dual-lvds-even-pixels; + + it6263_lvds_link1: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-odd-pixels; + + it6263_lvds_link2: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&it6263_lvds_link2>; + }; + }; + + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&it6263_lvds_link1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi new file mode 100644 index 000000000000..8cc9d361c2a4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi" + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + it6263: hdmi@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + data-mapping = "jeida-24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_en>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + ivdd-supply = <®_buck5>; + ovdd-supply = <®_vext_3v3>; + txavcc18-supply = <®_buck5>; + txavcc33-supply = <®_vext_3v3>; + pvcc1-supply = <®_buck5>; + pvcc2-supply = <®_buck5>; + avcc-supply = <®_vext_3v3>; + anvdd-supply = <®_buck5>; + apvdd-supply = <®_buck5>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + it6263_out: endpoint { + remote-endpoint = <&lvds2hdmi_connector_in>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso new file mode 100644 index 000000000000..527a893a71b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg = <0>; + + it6263_lvds_link1: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&it6263_lvds_link1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index d26930f1a9e9..68e12a752edd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -938,6 +938,12 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 >; }; + pinctrl_lvds_en: lvdsengrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ From patchwork Tue Nov 12 10:05:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13872015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE1A7D32D82 for ; Tue, 12 Nov 2024 10:06:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E86E10E5AF; Tue, 12 Nov 2024 10:06:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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The adapter cards can connect to i.MX8MP EVK base board to support video output through HDMI connectors. Build the ITE IT6263 driver as a module. Signed-off-by: Liu Ying Reviewed-by: Biju Das --- v6: * No change. v5: * No change. v4: * No change. v3: * No change. v2: * No change. arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d13218d0c30f..9b20b75f82e2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -901,6 +901,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_FSL_LDB=m +CONFIG_DRM_ITE_IT6263=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m