From patchwork Tue Nov 12 17:20:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13872641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85313D42BB6 for ; Tue, 12 Nov 2024 17:21:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAuZF-0003GP-QZ; Tue, 12 Nov 2024 12:20:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAuZB-0003FU-E9 for qemu-devel@nongnu.org; Tue, 12 Nov 2024 12:20:37 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tAuZ7-0003hb-Kv for qemu-devel@nongnu.org; Tue, 12 Nov 2024 12:20:35 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4319399a411so56459555e9.2 for ; Tue, 12 Nov 2024 09:20:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731432031; x=1732036831; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YFVkGXPUlThiD5pzlhxgmCFBmWmFouX3sMfYVHk+NQc=; b=TWrdGYjVHt+0MouA8p2tEn+S7Byl6Ey6KJELQYfGM4aoE1whUvyGEA2o0233hTX6w8 NVdc8Kok+WlkTk11UQ/GUi6tkQwgEMRS3gRF83b+jr5oXmMTmM1T+QsBNdWehkL6v+5a Db576SzlQ/wcvJoGpELurR4HM/sa3ciXe80JfxqfoOVQglA1DGmlEUNOOsW6vX1GWxU3 wBlLRAYsIqvKz0FRnoDoy/Dr4gKbbfdzBdSZgcZuFIImOVD6Q99stA+ayoTkMhjbsrZe SlxFObE4p2FfRDiwGl7PZBsiJRg++xmD6a5Xz4uOybuoP3KKAaNS6qSqNA8Kd1563qVc M/pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731432031; x=1732036831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YFVkGXPUlThiD5pzlhxgmCFBmWmFouX3sMfYVHk+NQc=; b=XzVwzGE5aSazpavlbeRwE8jrvDEA05z8LeccoR0/OEC+OJvi48/Ejba2SNW21xi9xV eQq9maftwsGpjH/tcupDrVbdZDHe7aChuxC3S+8j/R5zVVL79EfHvZTggRDAyYmz2UVv Y0hIPsPKGedQHYl7LqpScjNkRHOaDtd4qa/aP8Yn1HUV3HoKvE1n5Dz6/7XHxH/VzfnF BellJW9enuTyAJkeL1GicHQz1JfsgMyQ8B2bzHpaqm2c9umDt+iYPOTnXMMyWjzBlHuY 1sTVR5Xe3S1xH0ygpLTjwbhR5+raVlAdKNvPjpVMCqt6cYNdZOwieeKFYERnEoN9IblA 6Vog== X-Gm-Message-State: AOJu0Ywjrn9OwSpgN1sMEyWaxhxwsFXfpQmvWVwQDBZN4Qrk2Plpp5RK KACmyTxMz41rRHUeNtbTabP7ZPYvqzjfQpgKssjv4DfJA69wlYut1qSHHzpEIV9ftxGiRT8gpXt Z X-Google-Smtp-Source: AGHT+IGS510vuWmuTuxYsaoiRAsWd3JOclltR5V0xdf/hjUkVF0OLTNEtRRnDQCQRAyD2KKEhuYgGg== X-Received: by 2002:a5d:64c9:0:b0:37d:890c:63e4 with SMTP id ffacd0b85a97d-381f188c859mr14729106f8f.55.1731432030947; Tue, 12 Nov 2024 09:20:30 -0800 (PST) Received: from localhost.localdomain (cnf78-h01-176-184-27-250.dsl.sta.abo.bbox.fr. [176.184.27.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432aa6bee9asm259559555e9.19.2024.11.12.09.20.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 09:20:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/6] target/mips: Introduce decode tree bindings for microMIPS ISA Date: Tue, 12 Nov 2024 18:20:17 +0100 Message-ID: <20241112172022.88348-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112172022.88348-1-philmd@linaro.org> References: <20241112172022.88348-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Introduce the microMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/micromips16.decode | 9 +++++++++ target/mips/tcg/micromips32.decode | 9 +++++++++ target/mips/tcg/micromips_translate.c | 14 ++++++++++++++ target/mips/tcg/micromips_translate.c.inc | 6 ++++++ target/mips/tcg/meson.build | 3 +++ 6 files changed, 43 insertions(+) create mode 100644 target/mips/tcg/micromips16.decode create mode 100644 target/mips/tcg/micromips32.decode create mode 100644 target/mips/tcg/micromips_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index a65ab4a747..816453f2be 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -222,6 +222,8 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ +bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode new file mode 100644 index 0000000000..207e9c69f9 --- /dev/null +++ b/target/mips/tcg/micromips16.decode @@ -0,0 +1,9 @@ +# microMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume II-B +# microMIPS32 Instruction Set +# (Document Number: MD00582) diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode new file mode 100644 index 0000000000..c115ed2eab --- /dev/null +++ b/target/mips/tcg/micromips32.decode @@ -0,0 +1,9 @@ +# microMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume II-B +# microMIPS32 Instruction Set +# (Document Number: MD00582) diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c new file mode 100644 index 0000000000..49e90e7eca --- /dev/null +++ b/target/mips/tcg/micromips_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - microMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-micromips16.c.inc" +#include "decode-micromips32.c.inc" diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index c479bec108..f504e15fa7 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -3000,6 +3000,9 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) gen_reserved_instruction(ctx); return 2; } + if (decode_isa_micromips32(ctx, ctx->opcode)) { + return 4; + } break; case 1: /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */ @@ -3011,6 +3014,9 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) gen_reserved_instruction(ctx); return 2; } + if (decode_isa_micromips16(ctx, ctx->opcode)) { + return 2; + } break; } } diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 7b18e6c4c8..5db5681eb1 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,4 +1,6 @@ gen = [ + decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']), + decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), @@ -16,6 +18,7 @@ mips_ss.add(files( 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', + 'micromips_translate.c', 'msa_helper.c', 'msa_translate.c', 'op_helper.c', From patchwork Tue Nov 12 17:20:18 2024 Content-Type: text/plain; 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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432b05c0d33sm220339195e9.27.2024.11.12.09.20.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 09:20:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 2/6] target/mips: Introduce decode tree bindings for nanoMIPS ISA Date: Tue, 12 Nov 2024 18:20:18 +0100 Message-ID: <20241112172022.88348-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112172022.88348-1-philmd@linaro.org> References: <20241112172022.88348-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Introduce the nanoMIPS decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Rikalo Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/nanomips16.decode | 8 ++++++++ target/mips/tcg/nanomips32.decode | 8 ++++++++ target/mips/tcg/nanomips_translate.c | 14 ++++++++++++++ target/mips/tcg/nanomips_translate.c.inc | 7 +++++++ target/mips/tcg/meson.build | 3 +++ 6 files changed, 42 insertions(+) create mode 100644 target/mips/tcg/nanomips16.decode create mode 100644 target/mips/tcg/nanomips32.decode create mode 100644 target/mips/tcg/nanomips_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 816453f2be..a91c003f96 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -224,6 +224,8 @@ bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); +bool decode_isa_nanomips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_nanomips32(DisasContext *ctx, uint32_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode new file mode 100644 index 0000000000..81fdc68e98 --- /dev/null +++ b/target/mips/tcg/nanomips16.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode new file mode 100644 index 0000000000..9cecf1e13d --- /dev/null +++ b/target/mips/tcg/nanomips32.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c new file mode 100644 index 0000000000..c148c13ed9 --- /dev/null +++ b/target/mips/tcg/nanomips_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - nanoMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-nanomips16.c.inc" +#include "decode-nanomips32.c.inc" diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 1e274143bb..e401b92bfd 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4482,6 +4482,13 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) return 2; } + if (decode_isa_nanomips16(ctx, ctx->opcode)) { + return 2; + } + if (decode_isa_nanomips32(ctx, ctx->opcode)) { + return 4; + } + op = extract32(ctx->opcode, 10, 6); switch (op) { case NM_P16_MV: diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 5db5681eb1..f815174ed1 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -2,6 +2,8 @@ gen = [ decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']), decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), + decodetree.process('nanomips16.decode', extra_args: ['--decode=decode_isa_nanomips16', '--insnwidth=16']), + decodetree.process('nanomips32.decode', extra_args: ['--decode=decode_isa_nanomips32']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), @@ -21,6 +23,7 @@ mips_ss.add(files( 'micromips_translate.c', 'msa_helper.c', 'msa_translate.c', + 'nanomips_translate.c', 'op_helper.c', 'rel6_translate.c', 'translate.c', From patchwork Tue Nov 12 17:20:19 2024 Content-Type: text/plain; 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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed970f85sm16234038f8f.6.2024.11.12.09.20.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 09:20:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Richard Henderson Subject: [PATCH v2 3/6] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument Date: Tue, 12 Nov 2024 18:20:19 +0100 Message-ID: <20241112172022.88348-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112172022.88348-1-philmd@linaro.org> References: <20241112172022.88348-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Having the callee add 1 to shift amount is misleading (see the NM_LSA case in decode_nanomips_32_48_opc() where we have to manually substract 1). Rather have the callers pass a modified $sa. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/msa_translate.c | 4 ++-- target/mips/tcg/rel6_translate.c | 4 ++-- target/mips/tcg/translate_addr_const.c | 4 ++-- target/mips/tcg/micromips_translate.c.inc | 2 +- target/mips/tcg/nanomips_translate.c.inc | 7 +------ 5 files changed, 8 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 75cf80a20e..82b149922f 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); static bool trans_LSA(DisasContext *ctx, arg_r *a) { - return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); } static bool trans_DLSA(DisasContext *ctx, arg_r *a) @@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) if (TARGET_LONG_BITS != 64) { return false; } - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); } diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index 59f237ba3b..363bc86491 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -23,7 +23,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) static bool trans_LSA(DisasContext *ctx, arg_r *a) { - return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); } static bool trans_DLSA(DisasContext *ctx, arg_r *a) @@ -31,5 +31,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) if (TARGET_LONG_BITS != 64) { return false; } - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); } diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c index 6f4b39f715..1d140e918d 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -26,7 +26,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) t1 = tcg_temp_new(); gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); - tcg_gen_shli_tl(t0, t0, sa + 1); + tcg_gen_shli_tl(t0, t0, sa); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); return true; @@ -47,7 +47,7 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa) t1 = tcg_temp_new(); gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); - tcg_gen_shli_tl(t0, t0, sa + 1); + tcg_gen_shli_tl(t0, t0, sa); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); return true; } diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index f504e15fa7..e8ec5a0ff2 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -1795,7 +1795,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) return; case LSA: check_insn(ctx, ISA_MIPS_R6); - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2)); + gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1); break; case ALIGN: check_insn(ctx, ISA_MIPS_R6); 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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed987d33sm16160546f8f.43.2024.11.12.09.20.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 09:20:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aurelien Jarno Subject: [PATCH v2 4/6] target/mips: Decode LSA shift amount using decodetree function Date: Tue, 12 Nov 2024 18:20:20 +0100 Message-ID: <20241112172022.88348-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112172022.88348-1-philmd@linaro.org> References: <20241112172022.88348-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 3 ++- target/mips/tcg/rel6.decode | 4 +++- target/mips/tcg/msa_translate.c | 4 ++-- target/mips/tcg/rel6_translate.c | 9 +++++++-- 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 4410e2a02e..798e8c401a 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -21,6 +21,7 @@ &msa_elm_df df wd ws n &msa_elm wd ws +%lsa_sa 6:2 !function=plus_1 %elm_df 16:6 !function=elm_df %elm_n 16:6 !function=elm_n %bit_df 16:7 !function=bit_df @@ -29,7 +30,7 @@ %3r_df_h 21:1 !function=plus_1 %3r_df_w 21:1 !function=plus_2 -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +@lsa ...... rs:5 rt:5 rd:5 ... .. ...... &r sa=%lsa_sa @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:s16 &msa_bz diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode index d6989cf56e..a9031171b5 100644 --- a/target/mips/tcg/rel6.decode +++ b/target/mips/tcg/rel6.decode @@ -16,7 +16,9 @@ &r rs rt rd sa -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +%lsa_sa 6:2 !function=plus_1 + +@lsa ...... rs:5 rt:5 rd:5 ... .. ...... &r sa=%lsa_sa LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 82b149922f..75cf80a20e 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); static bool trans_LSA(DisasContext *ctx, arg_r *a) { - return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } static bool trans_DLSA(DisasContext *ctx, arg_r *a) @@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) if (TARGET_LONG_BITS != 64) { return false; } - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index 363bc86491..2522ecae2b 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -11,6 +11,11 @@ #include "qemu/osdep.h" #include "translate.h" +static inline int plus_1(DisasContext *ctx, int x) +{ + return x + 1; +} + /* Include the auto-generated decoders. */ #include "decode-rel6.c.inc" @@ -23,7 +28,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) static bool trans_LSA(DisasContext *ctx, arg_r *a) { - return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } static bool trans_DLSA(DisasContext *ctx, arg_r *a) @@ -31,5 +36,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) if (TARGET_LONG_BITS != 64) { return false; } - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } From patchwork Tue Nov 12 17:20:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13872644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8054FD42BB5 for ; Tue, 12 Nov 2024 17:21:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAuZl-0003UZ-D6; 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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432aa70a234sm256216705e9.34.2024.11.12.09.20.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 09:20:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aurelien Jarno Subject: [PATCH v2 5/6] target/mips: Convert microMIPS LSA opcode to decodetree Date: Tue, 12 Nov 2024 18:20:21 +0100 Message-ID: <20241112172022.88348-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112172022.88348-1-philmd@linaro.org> References: <20241112172022.88348-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Simply call the generic gen_lsa(), using the plus_1() helper to add 1 to the shift amount. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/micromips32.decode | 8 ++++++++ target/mips/tcg/micromips_translate.c | 10 ++++++++++ target/mips/tcg/micromips_translate.c.inc | 5 ----- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode index c115ed2eab..958883ce84 100644 --- a/target/mips/tcg/micromips32.decode +++ b/target/mips/tcg/micromips32.decode @@ -7,3 +7,11 @@ # Reference: MIPS Architecture for Programmers, Volume II-B # microMIPS32 Instruction Set # (Document Number: MD00582) + +&r rs rt rd sa + +%lsa_sa 9:2 !function=plus_1 + +@lsa ...... rt:5 rs:5 rd:5 .. ... ...... &r sa=%lsa_sa + +LSA 000000 ..... ..... ..... .. 000 001111 @lsa diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c index 49e90e7eca..f0b5dbf655 100644 --- a/target/mips/tcg/micromips_translate.c +++ b/target/mips/tcg/micromips_translate.c @@ -9,6 +9,16 @@ #include "qemu/osdep.h" #include "translate.h" +static inline int plus_1(DisasContext *ctx, int x) +{ + return x + 1; +} + /* Include the auto-generated decoders. */ #include "decode-micromips16.c.inc" #include "decode-micromips32.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_r *a) +{ + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); +} diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index e8ec5a0ff2..4b4550872f 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -191,7 +191,6 @@ enum { /* The following can be distinguished by their lower 6 bits. */ BREAK32 = 0x07, INS = 0x0c, - LSA = 0x0f, ALIGN = 0x1f, EXT = 0x2c, POOL32AXF = 0x3c, @@ -1793,10 +1792,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case INS: gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; - case LSA: - check_insn(ctx, ISA_MIPS_R6); - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1); - break; case ALIGN: check_insn(ctx, ISA_MIPS_R6); gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); 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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381eda04ad0sm15834386f8f.100.2024.11.12.09.20.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 09:20:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/6] target/mips: Convert nanoMIPS LSA opcode to decodetree Date: Tue, 12 Nov 2024 18:20:22 +0100 Message-ID: <20241112172022.88348-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241112172022.88348-1-philmd@linaro.org> References: <20241112172022.88348-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Simply call the generic gen_lsa() helper. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/nanomips32.decode | 6 ++++++ target/mips/tcg/nanomips_translate.c | 7 +++++++ target/mips/tcg/nanomips_translate.c.inc | 4 ---- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode index 9cecf1e13d..96d2299bfb 100644 --- a/target/mips/tcg/nanomips32.decode +++ b/target/mips/tcg/nanomips32.decode @@ -6,3 +6,9 @@ # # Reference: nanoMIPS32 Instruction Set Technical Reference Manual # (Document Number: MD01247) + +&r rs rt rd sa + +@lsa ...... rt:5 rs:5 rd:5 sa:2 --- ... ... &r + +LSA 001000 ..... ..... ..... .. ... 001 111 @lsa diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c index c148c13ed9..43a934d857 100644 --- a/target/mips/tcg/nanomips_translate.c +++ b/target/mips/tcg/nanomips_translate.c @@ -12,3 +12,10 @@ /* Include the auto-generated decoders. */ #include "decode-nanomips16.c.inc" #include "decode-nanomips32.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_r *a) +{ + gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); + + return true; +} diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index e118013edc..0e012ab3d0 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -399,7 +399,6 @@ enum { /* POOL32A7 instruction pool */ enum { NM_P_LSX = 0x00, - NM_LSA = 0x01, NM_EXTW = 0x03, NM_POOL32AXF = 0x07, }; @@ -3625,9 +3624,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_P_LSX: gen_p_lsx(ctx, rd, rs, rt); break; - case NM_LSA: - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2)); - break; case NM_EXTW: gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); break;