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([193.104.68.137]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cf03c8130dsm6137004a12.88.2024.11.12.08.42.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 08:42:27 -0800 (PST) From: Aleksandar Rakic X-Google-Original-From: Aleksandar Rakic To: qemu-devel@nongnu.org Cc: aleksandar.rakic@htecgroup.com, djordje.todorovic@htecgroup.com, cfu@mips.com, arikalo@gmail.com, peter.maydell@linaro.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, kwolf@redhat.com, hreitz@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, pierrick.bouvier@linaro.org, berrange@redhat.com, Yongbok Kim , Aleksandar Markovic Subject: [PATCH v3 1/4] Add support for emulation of CRC32 instructions Date: Tue, 12 Nov 2024 17:41:27 +0100 Message-Id: <20241112164130.2396737-3-aleksandar.rakic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> References: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=rakicaleksandar1999@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 12 Nov 2024 12:37:38 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions. Reuse zlib crc32() and Linux crc32c(). Cherry-picked 4cc974938aee1588f852590509004e340c072940 from https://github.com/MIPS/gnutools-qemu Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Aleksandar Rakic Reviewed-by: Aleksandar Rikalo --- target/mips/helper.h | 2 ++ target/mips/meson.build | 1 + target/mips/tcg/op_helper.c | 26 ++++++++++++++++++++++++++ target/mips/tcg/rel6.decode | 5 +++++ target/mips/tcg/rel6_translate.c | 14 ++++++++++++++ target/mips/tcg/translate.c | 25 +++++++++++++++++++++++++ target/mips/tcg/translate.h | 3 +++ 7 files changed, 76 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 0f8462febb..752748d5e6 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -21,6 +21,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif +DEF_HELPER_3(crc32, tl, tl, tl, i32) +DEF_HELPER_3(crc32c, tl, tl, tl, i32) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) /* microMIPS functions */ diff --git a/target/mips/meson.build b/target/mips/meson.build index a26d1e1f79..d2d686fc0c 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -7,6 +7,7 @@ mips_ss.add(files( 'gdbstub.c', 'msa.c', )) +mips_ss.add(zlib) if have_system subdir('sysemu') diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 65403f1a87..22600697f0 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -25,6 +25,8 @@ #include "exec/exec-all.h" #include "exec/memop.h" #include "fpu_helper.h" +#include "qemu/crc32c.h" +#include static inline target_ulong bitswap(target_ulong v) { @@ -143,6 +145,30 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } +/* these crc32 functions are based on target/arm/helper-a64.c */ +target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + target_ulong mask = ((sz * 8) == 64) ? + (target_ulong) -1ULL : + ((1ULL << (sz * 8)) - 1); + + m &= mask; + stq_le_p(buf, m); + return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); +} + +target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + target_ulong mask = ((sz * 8) == 64) ? + (target_ulong) -1ULL : + ((1ULL << (sz * 8)) - 1); + m &= mask; + stq_le_p(buf, m); + return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff); +} + void helper_fork(target_ulong arg1, target_ulong arg2) { /* diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode index d6989cf56e..5074338aa5 100644 --- a/target/mips/tcg/rel6.decode +++ b/target/mips/tcg/rel6.decode @@ -16,11 +16,16 @@ &r rs rt rd sa +&special3_crc rs rt c sz + @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +@crc32 ...... rs:5 rt:5 ..... c:3 sz:2 ...... &special3_crc LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa +CRC32 011111 ..... ..... 00000 ... .. 001111 @crc32 + REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index 59f237ba3b..423b323ba7 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -33,3 +33,17 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) } return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } + +static bool trans_CRC32(DisasContext *ctx, arg_special3_crc *a) +{ + if (unlikely(!ctx->crcp) || + unlikely((a->sz == 3) && + (!(ctx->hflags & MIPS_HFLAG_64))) || + unlikely((a->c >= 2))) { + gen_reserved_instruction(ctx); + return true; + } + gen_crc32(ctx, a->rt, a->rs, a->rt, + a->sz, a->c); + return true; +} diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index de7045874d..c97d1d37bd 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -13448,6 +13448,30 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) } } +void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, + int crc32c) +{ + TCGv t0; + TCGv t1; + TCGv_i32 tsz = tcg_constant_i32(1 << sz); + if (rd == 0) { + /* Treat as NOP. */ + return; + } + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + + if (crc32c) { + gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz); + } else { + gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz); + } + +} + static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; @@ -15094,6 +15118,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; + ctx->crcp = (env->CP0_Config5 >> CP0C5_CRCP) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx = MIPS_HFLAG_UM; diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 1bf153d183..cb27ae78ae 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -51,6 +51,7 @@ typedef struct DisasContext { bool abs2008; bool mi; int gi; + bool crcp; } DisasContext; #define DISAS_STOP DISAS_TARGET_0 @@ -181,6 +182,8 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel); +void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, + int crc32c); extern TCGv cpu_gpr[32], cpu_PC; #if defined(TARGET_MIPS64) From patchwork Tue Nov 12 16:41:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 13872689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A26C7D42BB7 for ; Tue, 12 Nov 2024 17:39:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAupg-0003La-L8; Tue, 12 Nov 2024 12:37:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAtyO-0000LU-5B for qemu-devel@nongnu.org; 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([193.104.68.137]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cf03c8130dsm6137004a12.88.2024.11.12.08.42.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 08:42:28 -0800 (PST) From: Aleksandar Rakic X-Google-Original-From: Aleksandar Rakic To: qemu-devel@nongnu.org Cc: aleksandar.rakic@htecgroup.com, djordje.todorovic@htecgroup.com, cfu@mips.com, arikalo@gmail.com, peter.maydell@linaro.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, kwolf@redhat.com, hreitz@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, pierrick.bouvier@linaro.org, berrange@redhat.com, Faraz Shahbazker Subject: [PATCH v3 2/4] Skip NaN mode check for soft-float Date: Tue, 12 Nov 2024 17:41:28 +0100 Message-Id: <20241112164130.2396737-4-aleksandar.rakic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> References: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=rakicaleksandar1999@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 12 Nov 2024 12:37:38 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Skip NaN mode check for soft-float since NaN mode is irrelevant if an ELF binary's FPU mode is soft-float, i.e. it doesn't utilize a FPU. Cherry-picked 63492a56485f6b755fccf7ad623f7a189bfc79b6 from https://github.com/MIPS/gnutools-qemu Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- linux-user/mips/cpu_loop.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 462387a073..07c1ebe287 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -304,8 +304,10 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) if (env->insn_flags & ISA_NANOMIPS32) { return; } - if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != - ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { + if (info->fp_abi != MIPS_ABI_FP_SOFT + && ((info->elf_flags & EF_MIPS_NAN2008) != 0) != + ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) + { if ((env->active_fpu.fcr31_rw_bitmask & (1 << FCR31_NAN2008)) == 0) { fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); From patchwork Tue Nov 12 16:41:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 13872690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3884D42BB7 for ; Tue, 12 Nov 2024 17:39:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAuph-0003Ln-1S; Tue, 12 Nov 2024 12:37:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAtyO-0000LX-5s for qemu-devel@nongnu.org; Tue, 12 Nov 2024 11:42:38 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tAtyL-0007NZ-2K for qemu-devel@nongnu.org; Tue, 12 Nov 2024 11:42:35 -0500 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-5c937982445so141335a12.2 for ; Tue, 12 Nov 2024 08:42:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731429751; x=1732034551; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f+1BQf8G2eZx/1JinIHQgfkNWVxgozYsbBIWJv0+lgk=; b=OmNQt2srF2PwwWbrMnxmoquqqmRSOT0sstN8lkl+aIRKLre43lGgw12M+0QIBAozbR 1QXpIndiw9BrrDLy2Ar7baXDllsEGBhf8fjPjwV9FWgqccd4o7EmSxX/FRbiu6Ehwg+c HzOLItf3/gPrdO98Hc1OwYSVB+0Pagj2Vq4LEDfYoAtaNiFZUSxl9lDsltljo8MssY/D QSzbmQCxL7Tnz6kTPR1Vy/BuxLvNK7ujMFvsDJd/Eu2RZDbEz6g31sY3Gm6BZdz6PFMl R51e/QDITS3NgBkQZ96fR2EuUj9cxDQbpOQE3Le3kzf6XxufzGh30GGVHB93tNygq2sX GCpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731429751; x=1732034551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f+1BQf8G2eZx/1JinIHQgfkNWVxgozYsbBIWJv0+lgk=; b=iCBYA2FRVTwVwxztkBgUDZ9JBJdhmokAH+Dduf/8r5LGVRpwmkVUqr6xVWc4BtY+ED ExJH07pzq2MMLz5IeNfzpsVlSUqUspZ/2sZrIcyb2dr01VHhVPIAsK7Oyc28KK6IKrAw VAdxjNcUBIe0/JzhiisADevraCBTcLE/GUZgUDrA+mOaSEp49VVY0qBoOQzirt3WwCXU rBzD1Bndq2SSUxk9+kMw1HPrWgHpFBbtA7aZlcPVRp+C9lf/WX/gBtlA/WDclSvHBB1c wrFzjPKmftPnGEjgNNEWmoVkGMe/PYT2Y/83xjU0wQf+opLBYTaOMzlpGLjZj8roRjeC wo4A== X-Gm-Message-State: AOJu0YwBMRQyZyC07y54Rg0gGvUahQNjXgcejh75Vkpyuw3aK+v+jonh tR+XLFrUDU3zbdaMURjx53uJnWnyvsDGI4TlEE0lm8laJp3sWe3L+5s+lhLL X-Google-Smtp-Source: AGHT+IExJQ3f831p0cGzbLoPqrRATvDEd164hjnR4PzOXE6kSKaCbXgeZPoDYQO2bcIBVSsBpfFscQ== X-Received: by 2002:a05:6402:5213:b0:5ce:fa24:fbaf with SMTP id 4fb4d7f45d1cf-5cf0a45c722mr5456386a12.9.1731429750874; Tue, 12 Nov 2024 08:42:30 -0800 (PST) Received: from L-H2N0CV05D839062.. ([193.104.68.137]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cf03c8130dsm6137004a12.88.2024.11.12.08.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 08:42:30 -0800 (PST) From: Aleksandar Rakic X-Google-Original-From: Aleksandar Rakic To: qemu-devel@nongnu.org Cc: aleksandar.rakic@htecgroup.com, djordje.todorovic@htecgroup.com, cfu@mips.com, arikalo@gmail.com, peter.maydell@linaro.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, kwolf@redhat.com, hreitz@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, pierrick.bouvier@linaro.org, berrange@redhat.com Subject: [PATCH v3 3/4] target/mips: Enable MSA ASE using a CLI flag Date: Tue, 12 Nov 2024 17:41:29 +0100 Message-Id: <20241112164130.2396737-5-aleksandar.rakic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> References: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=rakicaleksandar1999@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 12 Nov 2024 12:37:38 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable MSA ASE using a CLI flag -cpu ,msa=on. Signed-off-by: Aleksandar Rakic --- target/mips/cpu.c | 16 ++++++++++++++++ target/mips/cpu.h | 1 + target/mips/internal.h | 2 +- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d0a43b6d5c..8e12d303de 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -494,8 +494,24 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static bool mips_get_msa_on(Object *obj, Error **errp) +{ + MIPSCPU *cpu = MIPS_CPU(obj); + CPUMIPSState *env = &cpu->env; + return env->msa_on; +} + +static void mips_set_msa_on(Object *obj, bool value, Error **errp) +{ + MIPSCPU *cpu = MIPS_CPU(obj); + CPUMIPSState *env = &cpu->env; + env->msa_on = value; +} + static void mips_cpu_initfn(Object *obj) { + object_property_add_bool(obj, "msa", mips_get_msa_on, mips_set_msa_on); + object_property_set_bool(obj, "msa", false, NULL); MIPSCPU *cpu = MIPS_CPU(obj); CPUMIPSState *env = &cpu->env; MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f6877ece8b..3e636535c6 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1191,6 +1191,7 @@ typedef struct CPUArchState { QEMUTimer *timer; /* Internal timer */ Clock *count_clock; /* CP0_Count clock */ target_ulong exception_base; /* ExceptionBase input to the core */ + bool msa_on; /* Enable MSA using a CLI flag -cpu ...,msa=on/off */ } CPUMIPSState; /** diff --git a/target/mips/internal.h b/target/mips/internal.h index 91c786cff8..bbe2acffe2 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -399,7 +399,7 @@ static inline void compute_hflags(CPUMIPSState *env) } } if (ase_msa_available(env)) { - if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { + if ((env->CP0_Config5 & (1 << CP0C5_MSAEn)) || (env->msa_on)) { env->hflags |= MIPS_HFLAG_MSA; } } From patchwork Tue Nov 12 16:41:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Rakic X-Patchwork-Id: 13872686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BB37D42BB7 for ; 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([193.104.68.137]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cf03c8130dsm6137004a12.88.2024.11.12.08.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 08:42:32 -0800 (PST) From: Aleksandar Rakic X-Google-Original-From: Aleksandar Rakic To: qemu-devel@nongnu.org Cc: aleksandar.rakic@htecgroup.com, djordje.todorovic@htecgroup.com, cfu@mips.com, arikalo@gmail.com, peter.maydell@linaro.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, kwolf@redhat.com, hreitz@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, pierrick.bouvier@linaro.org, berrange@redhat.com, Faraz Shahbazker Subject: [PATCH v3 4/4] target/mips: Enable MSA ASE for mips64R2-generic Date: Tue, 12 Nov 2024 17:41:30 +0100 Message-Id: <20241112164130.2396737-6-aleksandar.rakic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> References: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=rakicaleksandar1999@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 12 Nov 2024 12:37:38 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable MSA ASE for mips64R2-generic CPU. Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f from https://github.com/MIPS/gnutools-qemu Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- target/mips/cpu-defs.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 922fc39138..e77a327422 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -678,7 +678,9 @@ const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | + (1 << CP0C3_VInt) | (1 << CP0C3_MSAP), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32,