From patchwork Wed Nov 13 02:02:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ragavendra B.N." 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Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by: Ragavendra Nagraj --- drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c index 29e24098bf5f..04a0419cab4e 100644 --- a/drivers/clk/sophgo/clk-cv18xx-pll.c +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c @@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - u32 val; + u32 val = 0; struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); return ipll_find_rate(pll->pll_limit, req->best_parent_rate,